Preface Introduction The purpose of Power Electronics Handbook second edition is to provide an uptodate reference tha...
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Preface Introduction The purpose of Power Electronics Handbook second edition is to provide an uptodate reference that is both concise and useful for engineering students and practicing professionals. It is designed to cover a wide range of topics that make up the ﬁeld of power electronics in a wellorganized and highly informative manner. The Handbook is a careful blend of both traditional topics and new advancements. Special emphasis is placed on practical applications, thus, this Handbook is not a theoretical one, but an enlightening presentation of the usefulness of the rapidly growing ﬁeld of power electronics. The presentation is tutorial in nature in order to enhance the value of the book to the reader and foster a clear understanding of the material. The contributors to this Handbook span the globe, with ﬁftyfour authors from twelve different countries, some of whom are the leading authorities in their areas of expertise. All were chosen because of their intimate knowledge of their subjects, and their contributions make this a comprehensive stateoftheart guide to the expanding ﬁeld of power electronics and its applications covering: •
•
•
the characteristics of modern power semiconductor devices, which are used as switches to perform the power conversions from ac–dc, dc–dc, dc–ac, and ac–ac; both the fundamental principles and indepth study of the operation, analysis, and design of various power converters; and examples of recent applications of power electronics.
Power Electronics Backgrounds The ﬁrst electronics revolution began in 1948 with the invention of the silicon transistor at Bell Telephone Laboratories by Bardeen, Bratain, and Shockley. Most of today’s advanced electronic technologies are traceable to that invention, and modern microelectronics has evolved over the years from these silicon semiconductors. The second electronics revolution began with the development of a commercial thyristor by the General
Electric Company in 1958. That was the beginning of a new era of power electronics. Since then, many different types of power semiconductor devices and conversion techniques have been introduced. The demand for energy, particularly in electrical forms, is everincreasing in order to improve the standard of living. Power electronics helps with the efﬁcient use of electricity, thereby reducing power consumption. Semiconductor devices are used as switches for power conversion or processing, as are solid state electronics for efﬁcient control of the amount of power and energy ﬂow. Higher efﬁciency and lower losses are sought for devices for a range of applications, from microwave ovens to highvoltage dc transmission. New devices and power electronic systems are now evolving for even more efﬁcient control of power and energy. Power electronics has already found an important place in modern technology and has revolutionized control of power and energy. As the voltage and current ratings and switching characteristics of power semiconductor devices keep improving, the range of applications continues to expand in areas such as lamp controls, power supplies to motion control, factory automation, transportation, energy storage, multimegawatt industrial drives, and electric power transmission and distribution. The greater efﬁciency and tighter control features of power electronics are becoming attractive for applications in motion control by replacing the earlier electromechanical and electronic systems. Applications in power transmission include highvoltage dc (VHDC) converter stations, ﬂexible ac transmission system (FACTS), and staticvar compensators. In power distribution these include dctoac conversion, dynamic ﬁlters, frequency conversion, and Custom Power System. Almost all new electrical or electromechanical equipment, from household air conditioners and computer power supplies to industrial motor controls, contain power electronic circuits and/or systems. In order to keep up, working engineers involved in control and conversion of power and energy into applications ranging from several hundred voltages at a fraction of an ampere for display devices to about 10,000 V at highvoltage dc transmission, should have a working knowledge of power electronics.
xv
xvi
Preface
Organization
Locating Your Topic
The Handbook starts with an introductory chapter and moves on to cover topics on power semiconductor devices, power converters, applications, and peripheral issues. The book is organized into six areas, the ﬁrst of which includes Chapters 2 to 9 on operation and characterizations of power semiconductor devices: Power Diode, Thyristor, Gate Turnoff Thyristor (GTO), Power Bipolar Transistor (BJT), Power MOSFET, Insulated Gate Bipolar Transistor, MOS Controlled Thyristor (MCT), and Static Induction Devices. The next topic area includes Chapters 10 to 20 covering various types of power converters, the principles of operation, and the methods for the analysis and design of power converters. This also includes gate drive circuits and control methods for power converters. The next 13 chapters 21 to 33 cover applications in power supplies, electronics ballasts, renewable energy soruces, HVDC transmission, VAR compensation, and capacitor charging. Power Electronics in Capacitor Charging Applications, Electronic Ballasts, Power Supplies, Uninterruptible Power Supplies, Automotive Applications of Power Electronics, Solar Power Conversion, Power Electronics for Renewable Energy Sources, Fuelcell Power Electronics for Distributed Generation, Wind Turbine Applications, HVDC Transmission, Flexible AC Transmission Systems, Drives Types and Speciﬁcations, Motor Drives. The following four chapters 34 to 37 focus on the Operation, Theory, and Control Methods of Motor Drives, and Automotive Systems. We then move on to three chapters 38 to 40 on Power Quality Issues, Active Filters, and EMI Effects of Power Converters and two chapters 41 to 42 on Computer Simulation, Packaging and Smart Power Systems.
A table of contents is presented at the front of the book, and each chapter begins with its own table of contents. The reader should look over these tables of contents to become familiar with the structure, organization, and content of the book.
Audience The Handbook is designed to provide both students and practicing engineers with answers to questions involving the wide spectrum of power electronics. The book can be used as a textbook for graduate students in electrical or systems engineering, or as a reference book for senior undergraduate students and for engineers who are interested and involved in operation, project management, design, and analysis of power electronics equipment and motor drives.
Acknowledgments This Handbook was made possible through the expertise and dedication of outstanding authors from throughout the world. I gratefully acknowledge the personnel at Academic Press who produced the book, including Jane Phelan. In addition, special thanks are due to Joel D. Claypool, the executive editor for this book. Finally, I express my deep appreciation to my wife, Fatema Rashid, who graciously puts up with my publication activities. Muhammad H. Rashid, EditorinChief
1 Introduction Philip T. Krein, Ph.D. Department of Electrical and Computer Engineering, University of Illinois, Urbana, Illinois, USA
1.1 Power Electronics Deﬁned ........................................................................ 1.2 Key Characteristics ..................................................................................
1 2
1.2.1 The Efﬁciency Objective – The Switch • 1.2.2 The Reliability Objective – Simplicity and Integration
1.3 Trends in Power Supplies ......................................................................... 1.4 Conversion Examples ..............................................................................
4 4
1.4.1 SingleSwitch Circuits • 1.4.2 The Method of Energy Balance
1.5 Tools for Analysis and Design ...................................................................
7
1.5.1 The Switch Matrix • 1.5.2 Implications of Kirchhoff’s Voltage and Current Laws • 1.5.3 Resolving the Hardware Problem – Semiconductor Devices • 1.5.4 Resolving the Software Problem – Switching Functions • 1.5.5 Resolving the Interface Problem – Lossless Filter Design
1.6 Summary .............................................................................................. 13 References ............................................................................................. 13
1.1 Power Electronics Deﬁned1 It has been said that people do not use electricity, but rather they use communication, light, mechanical work, entertainment, and all the tangible beneﬁts of both energy and electronics. In this sense, electrical engineering as a discipline is much involved in energy conversion and information. In the general world of electronics engineering, the circuits engineers design and use are intended to convert information. This is true of both analog and digital circuit design. In radio frequency applications, energy and information are sometimes on more equal footing, but the main function of any circuit is information transfer. What about the conversion and control of electrical energy itself? Energy is a critical need in every human endeavor. The capabilities and ﬂexibility of modern electronics must be brought to bear to meet the challenges of reliable, efﬁcient energy. It is essential to consider how electronic circuits and systems can be applied to the challenges of energy conversion and management. This is the framework of power electronics, a discipline deﬁned in terms of electrical
1 Portions of this chapter are from P. T. Krein, Elements of Power
Electronics. New York: Oxford University Press, 1998. Copyright © 1998, Oxford University Press. Used by permission.
Copyright © 2007, 2001, Elsevier Inc. All rights reserved.
energy conversion, applications, and electronic devices. More speciﬁcally, DEFINITION Power electronics involves the study of electronic circuits intended to control the ﬂow of electrical energy. These circuits handle power ﬂow at levels much higher than the individual device ratings. Rectiﬁers are probably the most familiar examples of circuits that meet this deﬁnition. Inverters (a general term for dc–ac converters) and dc–dc converters for power supplies are also common applications. As shown in Fig. 1.1, power electronics represents a median point at which the topics of energy systems, electronics, and control converge and combine [1]. Any useful circuit design for an energy application must address issues of both devices and control, as well as of the energy itself. Among the unique aspects of power electronics are its emphasis on large semiconductor devices, the application of magnetic devices for energy storage, special control methods that must be applied to nonlinear systems, and its fundamental place as a vital component of today’s energy systems. In any study of electrical engineering, power electronics must be placed on a level with digital, analog, and radiofrequency electronics to reﬂect the distinctive design methods and unique challenges. Applications of power electronics are expanding exponentially. It is not possible to build practical computers, cell phones, cars, airplanes, industrial processes, and a host of 1
2
P. T. Krein
rol
m ste Sy ration e Op
Ut Netwility ork s
itc h Sw trol Con
ec
s
tro
M P er S e m ow ctors ic o n d u
n ic s
and
n ag
et
vi c De
Energy
C El
u it
Power converter
Electrical load
d
Moto Drive r s
POWER ELECTRONICS
ir c
Electrical energy source
Po we r
an
an d Fee d Con bac tr o k l
nt
r we Po plies p Su
Systems
Co
ic s
es
FIGURE 1.1 Control, energy, and power electronics are interrelated.
other everyday products without power electronics. Alternative energy systems such as wind generators, solar power, fuel cells, and others require power electronics to function. Technology advances such as hybrid vehicles, laptop computers, microwave ovens, plasma displays, and hundreds of other innovations were not possible until advances in power electronics enabled their implementation. While no one can predict the future, it is certain that power electronics will be at the heart of fundamental energy innovations. The history of power electronics [2–5] has been closely allied with advances in electronic devices that provide the capability to handle high power levels. Since about 1990, devices have become so capable that a transition is being made from a “devicedriven” ﬁeld to an “applicationsdriven” ﬁeld. This transition has been based on two factors: advanced semiconductors with suitable power ratings exist for almost every application of wide interest; and the general push toward miniaturization is bringing advanced power electronics into a growing variety of products. While the devices continue to improve, their development now tends to follow innovative applications.
1.2 Key Characteristics All power electronic circuits manage the ﬂow of electrical energy between an electrical source and a load. The parts in a circuit must direct electrical ﬂows, not impede them. A general power conversion system is shown in Fig. 1.2. The function of the power converter in the middle is to control the energy ﬂow between a source and a load. For our purposes, the power converter will be implemented with a power
FIGURE 1.2 General system for electric power conversion. (From Reference [2], copyright © 1998, Oxford University Press, Inc.; used by permission.)
electronic circuit. Since a power converter appears between a source and a load, any energy used within the converter is lost to the overall system. A crucial point emerges: to build a power converter, we should consider only lossless components. A realistic converter design must approach 100% efﬁciency. A power converter connected between a source and a load also affects system reliability. If the energy source is perfectly reliable (it is on all the time), then a failure in the converter affects the user (the load) just as if the energy source had failed. An unreliable power converter creates an unreliable system. To put this in perspective, consider that a typical American household loses electric power only a few minutes a year. Energy is available 99.999% of the time. A converter must be better than this to prevent system degradation. An ideal converter implementation will not suffer any failures over its application lifetime. Extreme high reliability can be a more difﬁcult objective than high efﬁciency.
1.2.1 The Efﬁciency Objective – The Switch A circuit element as simple as a light switch reminds us that the extreme requirements in power electronics are not especially novel. Ideally, when a switch is on, it has zero voltage drop and will carry any current imposed on it. When a switch is off, it blocks the ﬂow of current regardless of the voltage across it. The device power, the product of the switch voltage and current, is identically zero at all times. A switch therefore controls energy ﬂow with no loss. In addition, reliability is also high. Household light switches perform over decades of use and perhaps 100,000 operations. Unfortunately, a mechanical light switch does not meet all practical needs. A switch in a power supply must often function 100,000 times each second. Even the best mechanical switch will not last beyond a few million cycles. Semiconductor switches (without this limitation) are the devices of choice in power converters. A circuit built from ideal switches will be lossless. As a result, switches are the main components of power converters, and many people equate power electronics with the study of switching power converters. Magnetic transformers and lossless storage elements such as capacitors and inductors are also valid components for use in power converters. The complete concept, shown in Fig. 1.3, illustrates a power electronic system. Such a system consists of an electrical energy source, an
1
3
Introduction
Electrical energy source
Power electronic circuit
Electrical load
Control circuit
FIGURE 1.3 A basic power electronic system. (From Reference [2], copyright © 1998, Oxford University Press, Inc.; used by permission.)
electrical load, a power electronic circuit, and a control function. The power electronic circuit contains switches, lossless energy storage elements, and magnetic transformers. The controls take information from the source, the load, and the designer, and then determine how the switches operate to achieve the desired conversion. The controls are built up with conventional lowpower analog and digital electronics. Switching devices are selected based on their power handling rating – the product of their voltage and current ratings – rather than on power dissipation ratings. This is in contrast to other applications of electronics, in which power dissipation ratings dominate. For instance, a typical stereo receiver performs a conversion from ac line input to audio output. Most audio ampliﬁers do not use the techniques of power electronics, and the semiconductor devices do not act as switches. A commercial 100 W ampliﬁer usually is designed with transistors big enough to dissipate the full 100 W. The semiconductor devices are used primarily to reconstruct the audio information rather than to manipulate the energy ﬂows. The sacriﬁce in energy is large – a home theater ampliﬁer often functions at less than 10% energy efﬁciency. In contrast, emerging switching ampliﬁers do use the techniques of power electronics. They provide dramatic efﬁciency improvements. A home theater system implemented with switching ampliﬁers can exceed 90% energy efﬁciency in a smaller, cooler package. The ampliﬁers can even be packed inside the loudspeaker. Switches can reach extreme power levels, far beyond what might be expected for a given size. Consider the following examples. EXAMPLE 1.1 The NTP30N20 is a metal oxide semiconductor ﬁeld effect transistor (MOSFET) with a drain current rating of 30 A, a maximum drain source breakdown voltage of 200 V, and rated power dissipation of up to 200 W under ideal conditions. Without a heat sink, however, the device can handle less than 2.5 W of dissipation. For power electronics purposes, the power handling rating is 30 A × 200 V = 6 kW. Several manufacturers have developed controllers for domestic refrigerators, air conditioners, and highend machine tools based on this device and its relatives. The second
part of the deﬁnition of power electronics in Section 1.1 points out that the circuits handle power at levels much higher than that of the ratings of individual devices. Here a device is used to handle 6000 W – as compared with its individual rating of no more than 200 W. The ratio 30:1 is high, but not unusual in power electronics contexts. In contrast, the same ratio in a conventional audio ampliﬁer is close to unity. EXAMPLE 1.2 The IRGPS60B120KD is an insulated gate bipolar transistor (IGBT) – a relative of the bipolar transistor that has been developed speciﬁcally for power electronics – rated for 1200 V and 120 A. Its power handling rating is 144 kW. This is sufﬁcient to control an electric or hybrid car.
1.2.2 The Reliability Objective – Simplicity and Integration Highpower applications lead to interesting issues. In an inverter, the semiconductors often manipulate 30 times their power dissipation capability or more. This implies that only about 3% of the power being controlled is lost. A small design error, unexpected thermal problem, or minor change in layout could alter this somewhat. For instance, if the loss turns out to be 4% rather than 3%, the device stresses are 33% higher, and quick failure is likely to occur. The ﬁrst issue for reliability in power electronic circuits is that of managing device voltage, current, and power dissipation levels to keep them well within rating limits. This can be challenging when power handling levels are high. The second issue for reliability is simplicity. It is well established in electronics design that the more parts there are in a system, the more likely it is to fail. Power electronic circuits tend to have few parts, especially in the main energy ﬂow paths. Necessary operations must be carried out through shrewd use of these parts. Often, this means that sophisticated control strategies are applied to seemingly simple conversion circuits. The third issue for reliability is integration. One way to avoid the reliabilitycomplexity tradeoff is to integrate multiple components and functions on a single substrate. A microprocessor, for example, might contain more than a million gates. All interconnections and signals ﬂow within a single chip, and the reliability is nearly to that of a single part. An important parallel trend in power electronic devices involves the integrated module [6]. Manufacturers seek ways to package several switching devices, with their interconnections and protection components, together as a unit. Control circuits for converters are also integrated as much as possible to keep the reliability high. The package itself becomes a fourth issue for reliability, and one that is a subject of active research. Many semiconductor packages include small bonding wires that can be susceptible to thermal or vibration damage.
4
The small geometries tend to enhance electromagnetic interference among the internal circuit components.
1.3 Trends in Power Supplies Two distinct trends drive electronic power supplies, one of the major classes of power electronic circuits. At the high end, microprocessors, memory chips, and other advanced digital circuits require increasing power levels and increasing performance at very low voltage. It is a challenge to deliver 100 A or more efﬁciently at voltages that can be less than 1 V. These types of power supplies are asked to deliver precise voltages even though the load can change by an order of magnitude in a few nanoseconds. At the other end is the explosive growth of portable devices with rechargeable batteries. The power supplies for these devices, for televisions, and for many other consumer products must be cheap and efﬁcient. Losses in lowcost power supplies are a problem today; often lowend power supplies and battery chargers draw energy even when their load is off. It is increasingly important to use the best possible power electronics design techniques for these supplies to save energy while minimizing the costs. Efﬁciency standards such as the EnergyStar® program place increasingly stringent requirements on a wide range of lowend power supplies. In the past, bulky “linear” power supplies were designed with transformers and rectiﬁers from the ac line frequency to provide low level dc voltages for electronic circuits. Late in the 1960s, use of dc sources in aerospace applications led to the development of power electronic dc–dc conversion circuits for power supplies. In a welldesigned power electronics arrangement today, called a switchmode power supply, an ac source from a wall outlet is rectiﬁed without direct transformation. The resulting high dc voltage is converted through a dc–dc converter to the 3, 5, and 12 V, or other level required. Switchmode power supplies to continue to supplant linear supplies across the full spectrum of circuit applications. A personal computer commonly requires three different 5 V supplies, a 3.3 V supply, two 12 V supplies, a −12 V supply, a 24 V supply, and a separate converter for 1 V delivery to the microprocessor. This does not include supplies for the video display or peripheral devices. Only a switchmode supply can support such complex requirements with acceptable costs. Switchmode supplies often take advantage of MOSFET semiconductor technology. Trends toward high reliability, low cost, and miniaturization have reached the point at which a 5 V power supply sold today might last 1,000,000 h (more than a century), provide 100 W of output in a package with volume less than 15 cm3 , and sell for a price approaching US$ 0.10 per watt. This type of supply brings an interesting dilemma: the ac line cord to plug it in takes up more space than the power supply itself. Innovative concepts such as integrating a power supply within a connection cable will be used in the future.
P. T. Krein
Device technology for power supplies is also being driven by expanding needs in the automotive and telecommunications industries as well as in markets for portable equipment. The automotive industry is making a transition to higher voltages to handle increasing electric power needs. Power conversion for this industry must be cost effective, yet rugged enough to survive the high vibration and wide temperature range to which a passenger car is exposed. Global communication is possible only when sophisticated equipment can be used almost anywhere. This brings a special challenge, because electrical supplies are neither reliable nor consistent throughout much of the world. While in North America voltage swings in the domestic ac supply are often ±5% around a nominal value, in many developing nations the swing can be ±25% – when power is available. Power converters for communications equipment must tolerate these swings, and must also be able to make use of a wide range of possible backup sources. Given the enormous size of worldwide markets for telephones and consumer electronics, there is a clear need for ﬂexiblesource equipment. Designers are challenged to obtain maximum performance from small batteries, and to create equipment with minimal energy requirements.
1.4 Conversion Examples 1.4.1 SingleSwitch Circuits Electrical energy sources take the form of dc voltage sources at various values, sinusoidal ac sources, polyphase sources, and many others. A power electronic circuit might be asked to transfer energy between two different dc voltage levels, between an ac source and a dc load, or between sources at different frequencies. It might be used to adjust an output voltage or power level, drive a nonlinear load, or control a load current. In this section, a few basic converter arrangements are introduced and energy conservation provides a tool for analysis. EXAMPLE 1.3 Consider the circuit shown in Fig. 1.4. It contains an ac source, a switch, and a resistive load. It is a simple but complete power electronic system.
+
Vac
R
Vout −
FIGURE 1.4 A simple power electronic system. (From Reference [2], copyright © 1998, Oxford University Press, Inc.; used by permission.)
1
5
Introduction 1
Relative voltage
0.5
0 0
180
360
540
720
900
1080
Angle (degrees)
−0.5
1260
1440
ac input voltage Output voltage
−1
FIGURE 1.5 Input and output waveforms for Example 1.4.
Let us assign a (somewhat arbitrary) control scheme to the switch. What if the switch is turned on whenever Vac > 0, and turned off otherwise? The input and output voltage waveforms are shown in Fig. 1.5. The input has a time average of√0, and rootmeansquare (RMS) value equal to Vpeak / 2, where Vpeak is the maximum value of Vac . The output has a nonzero average value given by vout (t ) =
1 2π
π/2 −π/2
Vpeak cos θdθ +
Vac
Vd
R
−
3π/2
L
+
0dθ π/2
(1.1)
Vpeak = = 0.3183Vpeak π and an RMS value equal to Vpeak /2. Since the output has nonzero dc voltage content, the circuit can be used as an ac–dc converter. To make it more useful, a lowpass ﬁlter would be added between the output and the load to smooth out the ac portion. This ﬁlter needs to be lossless, and will be constructed from only inductors and capacitors. The circuit in Example 1.3 acts as a halfwave rectiﬁer with a resistive load. With the hypothesized switch action, a diode can substitute for the ideal switch. The example conﬁrms that a simple switching circuit can perform power conversion functions. But, notice that a diode is not, in general, the same as an ideal switch. A diode places restrictions on the current direction, while a true switch would not. An ideal switch allows control over whether it is on or off, while a diode’s operation is constrained by circuit variables. Consider a second halfwave circuit, now with a series L–R load, shown in Fig. 1.6. EXAMPLE 1.4 A series diode L–R circuit has ac voltage source input. This circuit operates much differently than the halfwave rectiﬁer with resistive load. A diode will be on if forward biased, and off if reverse biased. In this circuit, an off diode will give current of zero. Whenever
FIGURE 1.6 Halfwave rectiﬁer with L–R load for Example 1.5.
the diode is on, the circuit is the ac source with L–R load. Let the ac voltage be V0 cos(ωt ). From Kirchhoff’s Voltage Law (KVL), V0 cos(ωt ) = L
di + Ri dt
Let us assume that the diode is initially off (this assumption is arbitrary, and we will check it as the example is solved). If the diode is off, the diode current i = 0, and the voltage across the diode will be vac . The diode will become forwardbiased when vac becomes positive. The diode will turn on when the input voltage makes a zerocrossing in the positive direction. This allows us to establish initial conditions for the circuit: i(t0 ) = 0, t0 = −π/(2ω). The differential equation can be solved in a conventional way to give
ωL π −t − exp i(t ) = V0 R 2 + ω2 L 2 τ 2ωτ R + 2 cos(ωt ) R + ω2 L 2 ωL + 2 sin(ωt ) R + ω2 L 2
(1.2)
6
P. T. Krein
Relative voltage and current
1
0.5
0 0
π
−0.5
2π
3π
6π
5π
4π Angle (rad)
ac input voltage Current Vd
−1
FIGURE 1.7 Input and output waveforms for Example 1.5.
where τ is the time constant L/R. What about diode turn off? One ﬁrst guess might be that the diode turns off when the voltage becomes negative, but this is not correct. From the solution, the current is not zero when the voltage ﬁrst becomes negative. If the switch attempts to turn off, it must drop the inductor current to zero instantly. The derivative of current in the inductor, di/dt, would become negative inﬁnite. The inductor voltage L(di/dt) similarly becomes negative inﬁnite – and the devices are destroyed. What really happens is that the falling current allows the inductor to maintain forward bias on the diode. The diode will turn off only when the current reaches zero. A diode has deﬁnite properties that determine the circuit action, and both the voltage and current are relevant. Figure 1.7 shows the input and output waveforms for a time constant τ equal to about onethird of the ac waveform period.
1.4.2 The Method of Energy Balance Any circuit must satisfy conservation of energy. In a lossless power electronic circuit, energy is delivered from source to load, possibly through an intermediate storage step. The energy ﬂow must balance over time such that the energy drawn from the source matches that delivered to the load. The converter in Fig. 1.8 serves as an example of how the method of energy balance can be used to analyze circuit operation. EXAMPLE 1.5 The switches in the circuit of Fig. 1.8 are controlled cyclically to operate in alternation: when the left switch is on, the right one is off, and so on. What does the circuit do if each switch operates half the time? The inductor and capacitor have large values. When the left switch is on, the source voltage Vin appears across the inductor. When the right switch is on,
i Vin
+ C
L
R
Vout −
FIGURE 1.8 Energy transfer switching circuit for Example 1.5. (From Reference [2], copyright © 1998, Oxford University Press, Inc.; used by permission.)
the output voltage Vout appears across the inductor. If this circuit is to be a useful converter, we want the inductor to receive energy from the source, then deliver it to the load without loss. Over time, this means that energy does not build up in the inductor (instead it ﬂows through on average). The power into the inductor therefore must equal the power out, at least over a cycle. Therefore, the average power in should equal the average power out of the inductor. Let us denote the inductor current as i. The input is a constant voltage source. Since L is large, this constant voltage source will not be able to change the inductor current quickly, and we can assume that the inductor current is also constant. The average power into L over the cycle period T is
Pin =
1 T
0
T /2
Vin i dt =
Vin i 2
(1.3)
For the average power out of L, we must be careful about current directions. The current out of the inductor will
1
7
Introduction
have a value −i. The average output power is
Pout
1 = T
The result is
T
Vout i −iVout dt = − 2 T /2
(1.4)
Pout =
1 T
=− For this circuit to be useful as a converter, there is net energy ﬂow from the source to the load over time. The power conservation relationship Pin = Pout requires that Vout = −Vin . The method of energy balance shows that when operated as described in the example, the circuit of Fig. 1.8 serves as a polarity reverser. The output voltage magnitude is the same as that of the input, but the output polarity is negative with respect to the reference node. The circuit is often used to generate a negative supply for analog circuits from a single positive input level. Other output voltage magnitudes can be achieved at the output if the switches alternate at unequal times. If the inductor in the polarity reversal circuit is moved instead to the input, a stepup function is obtained. Consider the circuit of Fig. 1.9 in the following example. EXAMPLE 1.6 The switches of Fig. 1.9 are controlled cyclically in alternation. The left switch is on for twothird of each cycle, and the right switch for the remaining onethird of each cycle. Determine the relationship between Vin and Vout . The inductor’s energy should not build up when the circuit is operating normally as a converter. A power balance calculation can be used to relate the input and output voltages. Again, let i be the inductor current. When the left switch is on, power is injected into the inductor. Its average value is 1 Pin = T
2T /3
Vin i dt =
0
2Vin i 3
(1.5)
Power leaves the inductor when the right switch is on. Care must be taken with respect to polarities, and the current should be set negative to represent output power.
T
−(Vin − Vout )i dt
2T /3
Vin i Vout i + 3 3
(1.6)
When the input and output power are equated, Vout i Vout i 2Vin i =− + , 3 3 3
and
3Vin = Vout
(1.7)
and the output voltage is found to be triple the input. Many seasoned engineers ﬁnd the dc–dc stepup function of Fig. 1.9 to be surprising. Yet Fig. 1.9 is just one example of such action. Others (including ﬂyback circuits related to Fig. 1.8) are used in systems ranging from CRT electron guns to spark ignitions for automobiles. The circuits in the preceding examples have few components, provide useful conversion functions, and are efﬁcient. If the switching devices are ideal, each circuit is lossless. Over the history of power electronics, development has tended to ﬂow around the discovery of such circuits: a circuit with a particular conversion function is discovered, analyzed, and applied. As the circuit moves from laboratory testing to a complete commercial product, control, and protection functions are added. The power portion of the circuit remains close to the original idea. The natural question arises as to whether a systematic approach to conversion is possible. Can we start with a desired function and design an appropriate converter, rather than starting from the converter and working backwards toward the application? What underlying principles can be applied to design and analysis? In this introductory chapter, a few of the key concepts are introduced. Keep in mind that while many of the circuits look deceptively simple, all are nonlinear systems with unusual behavior.
1.5 Tools for Analysis and Design 1.5.1 The Switch Matrix
L
i +
Vin
C
R
Vout −
FIGURE 1.9 Switching converter Example 1.6. (From Reference [2], copyright © 1998, Oxford University Press, Inc.; used by permission.)
The most readily apparent difference between a power electronic circuit and other types of electronic circuits is the switch action. In contrast to a digital circuit, the switches do not indicate a logic level. Control is effected by determining the times at which switches should operate. Whether there is just one switch or a large group, there is a complexity limit: if a converter has m inputs and n outputs, even the densest possible collection of switches would have a single switch between each input line and each output line. The m × n switches in the circuit can be arranged according to their connections. The pattern suggests a matrix, as shown in Fig. 1.10.
8
P. T. Krein 1,1
2,1
m input lines
1,2
1,3
1,n
,,,
2,2 ..
3,1
,,,
va m×n switches
.
...
vb ,,,
m,1
m,n
vc
n output lines
Dc load
FIGURE 1.10 The general switch matrix.
FIGURE 1.12 Threephase bridge rectiﬁer circuit, a 3×2 switch matrix.
Power electronic circuits fall into two broad classes: 1. Direct switch matrix circuits. In these circuits, energy storage elements are connected to the matrix only at the input and output terminals. The storage elements effectively become part of the source or the load. A rectiﬁer with an external lowpass ﬁlter is an example of a direct switch matrix circuit. In the literature, these circuits are sometimes called matrix converters. 2. Indirect switch matrix circuits, also termed embedded converters. These circuits, like the polarityreverser example, have energy storage elements connected within the matrix structure. There are usually very few storage elements. Indirect switch matrix circuits are most commonly analyzed as a cascade connection of direct switch matrix circuits with the storage in between. The switch matrices in realistic applications are small. A 2 × 2 switch matrix, for example, covers all possible cases with a singleport input source and a twoterminal load. The matrix is commonly drawn as the Hbridge shown in Fig. 1.11. A more complicated example is the threephase bridge rectiﬁer shown in Fig. 1.12. There are three possible inputs, and the two terminals of the dc circuit provide outputs, which gives
1,2
1,1 Input Source
Load 2,1
2,2
FIGURE 1.11 Hbridge conﬁguration of a 2 × 2 switch matrix.
a 3 × 2 switch matrix. In a personal computer power supply, there are commonly ﬁve separate dc loads, and the switch matrix is 2 × 10. Very few practical converters have more than 24 switches, and most designs use fewer than 12. A switch matrix provides a way to organize devices for a given application. It also helps to focus the effort into three major task areas. Each of these areas must be addressed effectively in order to produce a useful power electronic system. •
•
•
The “Hardware” Task – Build a switch matrix. This involves the selection of appropriate semiconductor switches and the auxiliary elements that drive and protect them. The “Software” Task – Operate the matrix to achieve the desired conversion. All operational decisions are implemented by adjusting switch timing. The “Interface” Task – Add energy storage elements to provide the ﬁlters or intermediate storage necessary to meet the application requirements. Unlike most ﬁlter applications, lossless ﬁlters with simple structures are required.
In a rectiﬁer or other converter, we must choose the electronic parts, how to operate them, and how best to ﬁlter the output to satisfy the needs of the load.
1.5.2 Implications of Kirchhoff’s Voltage and Current Laws A major challenge of switch circuits is their capacity to “violate” circuit laws. Consider ﬁrst the simple circuits of Fig. 1.13. The circuit of Fig. 1.13a is something we might try for ac–dc conversion. This circuit has problems. Kirchhoff’s Voltage Law (KVL) tells us that the “sum of voltage drops around a closed loop is zero.” However, with the switch closed,
1
9
Introduction
(a)
(b) I2 Vac
Switch muct remain open
I1
Vdc
Switch muct remain open
FIGURE 1.13 Hypothetical power converters: (a) possible ac–dc converter and (b) possible dc–dc converter. (From [2], copyright © 1998, Oxford University Press Inc.; used by permission.)
the sum of voltages around the loop is not zero. In reality, this is not a valid result. Instead, a very large current will ﬂow and cause a large I ·R drop in the wires. KVL will be satisﬁed by the wire voltage drop, but a ﬁre or, better yet, fuse action, might result. There is, however, nothing that would prevent an operator from trying to close the switch. KVL, then, implies a crucial restriction: a switch matrix must not attempt to interconnect unequal voltage sources directly. Notice that a wire, or dead short, can be thought of as a voltage source with V = 0, so KVL is a generalization for avoiding shorts across an individual voltage source. A similar constraint holds for Kirchhoff’s Current Law (KCL). The law states that “currents into a node must sum to zero.” When current sources are present in a converter, we must avoid any attempts to violate KCL. In Fig. 1.13b, if the current sources are different and if the switch is opened, the sum of the currents into the node will not be zero. In a real circuit, high voltages will build up and cause an arc to create another current path. This situation has real potential for damage, and a fuse will not help. As a result, KCL implies the restriction that a switch matrix must not attempt to interconnect unequal current sources directly. An open circuit can be thought of as a current source with I = 0, so KCL applies to the problem of opening an individual current source. In contrast to conventional circuits, in which KVL and KCL are automatically satisﬁed, switches do not “know” KVL or KCL. If a designer forgets to check, and accidentally shorts two voltages or breaks a current source connection, some problem or damage will result. On the other hand, KVL and KCL place necessary constraints on the operating strategy of a switch matrix. In the case of voltage sources, switches must not act to create shortcircuit paths among unlike sources. In the case of KCL, switches must act to provide a path for currents. These constraints drastically reduce the number of valid switch operating conditions in a switch matrix, and lead to manageable operating design problems. When energy storage is included, there are interesting implications of the current law restrictions. Figure 1.14 shows two “circuit law problems.” In Fig. 1.14a, the voltage source will cause the inductor current to ramp up indeﬁnitely, since
(a)
(b)
FIGURE 1.14 Shortterm KVL and KCL problems in energy storage circuits: (a) an inductor cannot sustain dc voltage indeﬁnitely and (b) a capacitor cannot sustain dc current indeﬁnitely.
V = L di/dt . We might consider this to be a “KVL problem,” since the longterm effect is similar to shorting the source. In Fig. 1.14b, the current source will cause the capacitor voltage to ramp towards inﬁnity. This causes a “KCL problem;” eventually, an arc will be formed to create an additional current path, just as if the current source had been opened. Of course, these connections are not problematic if they are only temporary. However, it should be evident that an inductor will not support dc voltage, and a capacitor will not support dc current. On average over an extended time interval, the voltage across an inductor must be zero, and the current into a capacitor must be zero.
1.5.3 Resolving the Hardware Problem – Semiconductor Devices A switch is either on or off. An ideal switch, when on, will carry any current in any direction. When off, it will never carry current, no matter what voltage is applied. It is entirely lossless, and changes from its onstate to its offstate instantaneously. A real switch can only approximate an ideal switch. Those aspects of real switches that differ from the ideal include the following: • •
limits on the amount and direction of onstate current; a nonzero onstate voltage drop (such as a diode forward voltage);
10
P. T. Krein • • •
some level of leakage current when the device is supposed to be off; limitations on the voltage that can be applied when off; and operating speed. The duration of transition between the on and offstates can be important.
The degree to which the properties of an ideal switch must be met by a real switch depends on the application. For example, a diode can easily be used to conduct dc current; the fact that it conducts only in one direction is often an advantage, not a weakness. Many different types of semiconductors have been applied in power electronics. In general, these fall into three groups: – Diodes, which are used in rectiﬁers, dc–dc converters, and in supporting roles. – Transistors, which in general are suitable for control of singlepolarity circuits. Several types of transistors are applied to power converters. The most recent type, the IGBT, is unique to power electronics and has good characteristics for applications such as inverters. – Thyristors, which are multijunction semiconductor devices with latching behavior. Thyristors in general can be switched with short pulses, and then maintain their
TABLE 1.1
state until current is removed. They act only as switches. The characteristics are especially well suited to controllable rectiﬁers, although thyristors have been applied to all power conversion applications. Some of the features of the most common power semiconductors are listed in Table 1.1. The table shows a wide variety of speeds and rating levels. As a rule, faster speeds apply to lower ratings. For each device type, cost tends to increase both for faster devices and for devices with higher powerhandling capacity. Conducting direction and blocking behavior are fundamentally tied to the device type, and these basic characteristics constrain the choice of device for a given conversion function. Consider again a diode. It carries current in only one direction and always blocks current in the other. Ideally, the diode exhibits no forward voltage drop or offstate leakage current. Although it lacks many features of an ideal switch, the ideal diode is an important switching device. Other real devices operate with polarity limits on current and voltage and have corresponding ideal counterparts. It is convenient to deﬁne a special type of switch to represent this behavior: the restricted switch. DEFINITION A restricted switch is an ideal switch with the addition of restrictions on the direction of current
Semiconductor devices used in power electronics
Device type
Characteristics of power devices
Diode
Current ratings from under 1 A to more than 5000 A. Voltage ratings from 10 V to 10 kV or more. The fastest power devices switch in less than 20 ns, while the slowest require 100 µs or more. The function of a diode applies in rectiﬁers and dc–dc circuits.
BJT
(Bipolar junction transistor) Conducts collector current (in one direction) when sufﬁcient base current is applied. Power device current ratings from 0.5 to 500 A or more; voltages from 30 to 1200 V. Switching times from 0.5 to 100 µs. The function applies to dc–dc circuits; combinations with diodes are used in inverters. Power BJTs are being supplanted by FETs and IGBTs.
FET
(Field effect transistor) Conducts drain current when sufﬁcient gate voltage is applied. Power FETs (nearly always enhancementmode MOSFETs) have a parallel connected reverse diode by virtue of their construction. Ratings from about 0.5 A to about 150 A and 20 V up to 1000 V. Switching times are fast, from 50 ns or less up to 200 ns. The function applies to dc–dc conversion, where the FET is in wide use, and to inverters.
IGBT
(Insulated gate bipolar transistor) A special type of power FET that has the function of a BJT with its base driven by an FET. Faster than a BJT of similar ratings, and easy to use. Ratings from 10 A to more than 600 A, with voltages of 600 to 2500 V. The IGBT is popular in inverters from about 1 to 200 kW or more. It is found almost exclusively in power electronics applications.
SCR
(Silicon controlled rectiﬁer) A thyristor that conducts like a diode after a gate pulse is applied. Turns off only when current becomes zero. Prevents current ﬂow until a pulse appears. Ratings from 10 A up to more than 5000 A, and from 200 V up to 6 kV. Switching requires 1 to 200 µs. Widely used for controlled rectiﬁers. The SCR is found almost exclusively in power electronics applications, and is the most common member of the thyristor family.
GTO
(Gate turnoff thyristor) An SCR that can be turned off by sending a negative pulse to its gate terminal. Can substitute for BJTs in applications where power ratings must be very high. The ratings approach those of SCRs, and the speeds are similar as well. Used in inverters rated above about 100 kW.
TRIAC
A semiconductor constructed to resemble two SCRs connected in reverse parallel. Ratings from 2 to 50 A and 200 to 800 V. Used in lamp dimmers, home appliances, and hand tools. Not as rugged as many other device types, but very convenient for many ac applications.
MCT
(MOSFET controlled thyristor) A special type of SCR that has the function of a GTO with its gate driven from an FET. Much faster than conventional GTOs, and easier to use. These devices and relatives such as the IGCT (integrated gate controlled thyristor) are supplanting GTOs in some application areas.
1
11
Introduction
TABLE 1.2
The types of restricted switches
Action
Device
Carries current in one direction, blocks in the other (forwardconducting reverseblocking)
Diode
Quadrants
Restricted switch symbol
Device symbol
I V
Carries or blocks current in one direction (forwardconducting forwardblocking)
BJT
I V
Carries in one direction or blocks in both directions (forwardconducting bidirectionalblocking)
GTO
I V
Carries in both directions, but blocks only in one direction (bidirectionalcarrying forwardblocking)
FET
I V
Fully bidirectional
Ideal switch
I V
ﬂow and voltage polarity. The ideal diode is one example of a restricted switch. The diode always permits current ﬂow in one direction, while blocking ﬂow in the other. It therefore represents a forwardconducting reverseblocking (FCRB) restricted switch, and operates in one quadrant on a graph of device current vs. voltage. This FCRB function is automatic – the two diode terminals provide all the necessary information for switch action. Other restricted switches require a third gate terminal to determine their state. Consider the polarity possibilities given in Table 1.2. Additional functions such as bidirectionalconducting reverseblocking can be obtained by reverse connection of one of the ﬁve types in the table. The quadrant operation shown in the table indicates polarities. For example, the current in a diode will be positive when on and the voltage will be negative when off. This means diode operation is restricted to the single quadrant comprising the upper vertical (current) axis and the left horizontal (voltage) axis. The other combinations appear in the table. Symbols for restricted switches can be built up by interpreting the diode’s triangle as the currentcarrying direction and the bar as the blocking direction. The ﬁve types can be drawn as in Table 1.2. These symbols are used infrequently, but are valuable for showing the polarity behavior of switching devices. A circuit drawn with restricted switches represents an idealized power converter. Restricted switch concepts guide the selection of devices. For example, consider an inverter intended to deliver ac load
current from a dc voltage source. A switch matrix built to perform this function must be able to manipulate ac current and dc voltage. Regardless of the physical arrangement of the matrix, we would expect bidirectionalconducting forwardblocking switches to be useful for this conversion. This is a correct result: modern inverters operating from dc voltage sources are built with FETs, or with IGBTs arranged with reverseparallel diodes. As new power devices are introduced to the market, it is straightforward to determine what types of converters will use them.
1.5.4 Resolving the Software Problem – Switching Functions The physical m × n switch matrix can be associated with a mathematical m × n switch state matrix. Each element of this matrix, called a switching function, shows whether the corresponding physical device is on or off. DEFINITION A switching function, q(t ), has a value of 1 when the corresponding physical switch is on and 0 when it is off. Switching functions are discretevalued functions of time, and control of switching devices can be represented with them. Figure 1.15 shows a typical switching function. It is periodic, with period T , representing the most likely repetitive switch action in a power converter. For convenience, it is drawn on a relative time scale that begins at 0 and draws out the square
12
P. T. Krein Absolute time reference
1
0 0
t0 DT T
3T T+DT 2T Relative Time  Period T
4T
5T
FIGURE 1.15 A generic switching function with period T , duty ratio D, and time reference t0 .
wave period by period. The actual timing is arbitrary, so the center of the ﬁrst pulse is deﬁned as a speciﬁed time t0 in the ﬁgure. In many converters, the switching function is generated as an actual control voltage signal that might drive the gate of either a MOSFET or some other semiconductor switching device. The timing of switch action is the only alternative for control of a power converter. Since switch action can be represented with a discretevalued switching function, timing can be represented within the switching function framework. Based on Fig. 1.15, a generic switching function can be characterized completely with three parameters: 1. The duty ratio, D, is the fraction of time during which the switch is on. For control purposes, the pulse width can be adjusted to achieve a desired result. We can term this adjustment process pulsewidth modulation (PWM), perhaps the most important process for implementing control in power converters. 2. The frequency fswitch = 1/T (with radian frequency ω = 2πfswitch ) is most often constant, although not in all applications. For control purposes, frequency can be adjusted. This strategy is sometimes used in lowpower dc–dc converters to manage wide load ranges. In other converters, frequency control is unusual because the operating frequency is often dictated by the application. 3. The time delay t0 or phase ϕ0 = ωt0 . Rectiﬁers often make use of phase control to provide a range of adjustment. A few specialized ac–ac converter applications use phase modulation. With just three parameters to vary, there are relatively few possible ways to control any power electronic circuit. Dc–dc converters usually rely on duty ratio adjustment (PWM) to alter their behavior. Phase control is common in controlled rectiﬁer applications. Many types of inverters use PWM. Switching functions are powerful tools for the general representation of converter action [7]. The most widely used control approaches derive from averages of switching functions [2, 8]. Their utility comes from their application in writing circuit equations. For example, in the boost converter of Fig. 1.9, the loop and node equations change depending on which switch is
acting at a given moment. The two possible circuit conﬁgurations each have distinct equations. Switching functions allow them to be combined. By assigning switching functions q1 (t ) and q2 (t ) to the left and right switching devices, respectively, we obtain di L q1 Vin − L =0 , dt dvC vC q1 C + = 0 , left switch on (1.8) dt R di L q2 Vin − L = vC , dt dvC vC q2 C (1.9) + = iL , right switch on dt R Because the switches alternate, and the switching functions must be 0 or 1, these sets of equations can be combined to give Vin − L
di L = q2 vC , dt
C
dvC vC + = q2 iL dt R
(1.10)
The combined expressions are simpler and easier to analyze than the original equations. For control purposes, the average of equations such as (1.10) often proceeds with the replacement of switching functions q with duty ratios d. The discrete time action of a switching function thus will be represented by an average duty cycle parameter. Switching functions, the advantages gained by averaging, and control approaches such as PWM are discussed at length in several chapters in this handbook.
1.5.5 Resolving the Interface Problem – Lossless Filter Design Lossless ﬁlters for power electronic applications are sometimes called smoothing ﬁlters [9]. In applications in which dc outputs are of interest, such ﬁlters are commonly implemented as simple lowpass LC structures. The analysis is facilitated because in most cases the residual output waveform, termed ripple, has a known shape. Filter design for rectiﬁers or dc–dc converters is a question of choosing storage elements large enough to keep ripple low, but not so large that the whole circuit becomes unwieldy or expensive. Filter design is more challenging when ac outputs are desired. In some cases, this is again an issue of lowpass ﬁlter design. In many applications, lowpass ﬁlters are not adequate to meet low noise requirements. In these situations, active ﬁlters can be used. In power electronics, the term active ﬁlter refers to lossless switching converters that actively inject or remove energy momentbymoment to compensate for distortion. The circuits (discussed elsewhere in this handbook)
1
13
Introduction
are not related to the linear active ﬁlter opamp circuits used in analog signal processing. In ac cases, there is a continuing opportunity for innovation in ﬁlter design.
1.6 Summary Power electronics is the study of electronic circuits for the control and conversion of electrical energy. The technology is a critical part of our energy infrastructure, and is a key driver for a wide range of uses of electricity. It is becoming increasingly important as an essential tool for efﬁcient, convenient energy conversion, and management. For power electronics design, we consider only those circuits and devices that, in principle, introduce no loss and achieve nearperfect reliability. The two key characteristics of high efﬁciency and high reliability are implemented with switching circuits, supplemented with energy storage. Switching circuits can be organized as switch matrices. This facilitates their analysis and design. In a power electronic system, the three primary challenges are the hardware problem of implementing a switch matrix, the software problem of deciding how to operate that matrix, and the interface problem of removing unwanted distortion and providing the user with the desired clean power source. The hardware is implemented with a few special types of power semiconductors. These include several types of transistors, especially MOSFETs and IGBTs, and several types of thyristors, especially SCRs and GTOs. The software problem can be represented in terms of switching functions. The frequency, duty ratio, and phase of switching functions are available for operational purposes. The interface problem is addressed by means of lossless ﬁlter circuits. Most often, these are lossless LC passive ﬁlters to smooth out ripple or reduce harmonics. Active ﬁlter circuits also have been applied to make dynamic corrections in power conversion waveforms. Improvements in devices and advances in control concepts have led to steady improvements in power electronic circuits and systems. This is driving tremendous expansion of
their application. Personal computers, for example, would be unwieldy and inefﬁcient without power electronic dc supplies. Portable communication devices and laptop computers would be impractical. Highperformance lighting systems, motor controls, and a wide range of industrial controls depend on power electronics. Strong growth is occurring in automotive applications, in dc power supplies for communication systems, in portable devices, and in highend converters for advanced microprocessors. In the near future, power electronics will be the enabler for alternative and renewable energy resources. During the next generation, we will reach a time when almost all electrical energy is processed through power electronics somewhere in the path from generation to end use.
References 1. J. Motto, ed., Introduction to Solid State Power Electronics. Youngwood, PA: Westinghouse, 1977. 2. P. T. Krein, Elements of Power Electronics. New York: Oxford University Press, 1998. 3. T. M. Jahns and E. L. Owen, “Ac adjustablespeed drives at the millenium: how did we get here?” in Proc. IEEE Applied Power Electronics Conf., 2000, pp. 18–26. 4. C. C. Herskind and W. McMurray, “History of the static power converter committee,” IEEE Trans. Industry Applications, vol. IA20, no. 4, pp. 1069–1072, July 1984. 5. E. L. Owen, “Origins of the inverter,” IEEE Industry Applications Mag., vol. 2, p. 64, January 1996. 6. J. D. Van Wyk and F. C. Lee, “Power electronics technology at the dawn of the new millennium – status and future,” in Rec., IEEE Power Electronics Specialists Conf., 1999, pp. 3–12. 7. P. Wood, Switching Power Converters. New York: Van Nostrand Reinhold, 1981. 8. R. Erickson, Fundamentals of Power Electronics. New York: Chapman and Hall, 1997. 9. P. T. Krein and D. C. Hamill, “Smoothing circuits,” in J. Webster (ed.), Wiley Encyclopedia of Electrical and Electronics Engineering. New York: John Wiley, 1999.
2 The Power Diode Ali I. Maswood, Ph.D. School of EEE Nanyang Technological University, Nanyang Avenue, Singapore
2.1 2.2 2.3 2.4
Diode as a Switch.................................................................................... Properties of PN Junction ........................................................................ Common Diode Types............................................................................. Typical Diode Ratings..............................................................................
15 15 17 17
2.4.1 Voltage Ratings • 2.4.2 Current Ratings
2.5 2.6 2.7 2.8
Snubber Circuits for Diode ....................................................................... Series and Parallel Connection of Power Diodes ........................................... Typical Applications of Diodes .................................................................. Standard Datasheet for Diode Selection ...................................................... References .............................................................................................
2.1 Diode as a Switch Among all the static switching devices used in power electronics (PE), the power diode is perhaps the simplest. Its circuit symbol is shown in Fig. 2.1. It is a two terminal device, and terminal A is known as the anode whereas terminal K is known as the cathode. If terminal A experiences a higher potential compared to terminal K, the device is said to be forward biased and a current called forward current (IF ) will ﬂow through the device in the direction as shown. This causes a small voltage drop across the device (>
−500V
60ms
70ms
80ms
FIGURE 2.5b The waveforms.
90 ms
Current
−0V 500V
0.2 = 22.36 A 1
Ipeak = 50 A
FIGURE 2.5a The circuit.
400V
0.2 = 10 A 1
50A
0.2 ms
0
1 2 Time (ms)
3
FIGURE 2.6 The current waveform.
2
19
The Power Diode
2.5 Snubber Circuits for Diode Snubber circuits are essential for diodes used in switching circuits. It can save a diode from overvoltage spikes, which may arise during the reverse recovery process. A very common snubber circuit for a power diode consists of a capacitor and a resistor connected in parallel with the diode as shown in Fig. 2.7. When the reverse recovery current decreases, the capacitor by virtue of its property will try to hold the voltage across it, which, approximately, is the voltage across the diode. The resistor on the other hand will help to dissipate some of the energy stored in the inductor, which forms the IRR loop. The dv/dt across a diode can be calculated as: dv 0.632 × VS 0.632 × VS = = dt τ RS × C S
(2.2)
where VS is the voltage applied across the diode. Usually the dv/dt rating of a diode is given in the manufacturers datasheet. Knowing dv/dt and the RS , one can choose the value of the snubber capacitor CS . The RS can be calculated from the diode reverse recovery current: RS =
VS IRR
(2.3)
The designed dv/dt value must always be equal or lower than the dv/dt value found from the datasheet.
Cs Vs Rs
FIGURE 2.7 A typical snubber circuit.
2.6 Series and Parallel Connection of Power Diodes For speciﬁc applications, when the voltage or current rating of a chosen diode is not enough to meet the designed rating, diodes can be connected in series or parallel. Connecting them in series will give the structure a high voltage rating that may be necessary for highvoltage applications. However, one must ensure that the diodes are properly matched especially in terms of their reverse recovery properties. Otherwise, during reverse recovery there may be a large voltage imbalances between the
D1
Vs
R1
C1
R2 C2
D2
D3 R3
C3
FIGURE 2.8 Series connected diodes with necessary protection.
series connected diodes. Additionally, due to the differences in the reverse recovery times, some diodes may recover from the phenomenon earlier than the other causing them to bear the full reverse voltage. All these problems can effectively be overcome by connecting a bank of a capacitor and a resistor in parallel with each diode as shown in Fig. 2.8. If a selected diode cannot match the required current rating, one may connect several diodes in parallel. In order to ensure equal current sharing, the designer must choose diodes with the same forward voltage drop properties. It is also important to ensure that the diodes are mounted on similar heat sinks and are cooled (if necessary) equally. This will affect the temperatures of the individual diodes, which in turn may change the forward characteristics of diode.
Tutorial 2.1
Reverse Recovery and Overvoltages
Figure 2.9 shows a simple switch mode power supply. The switch (12) is closed at t = 0 s. When the switch is open, a freewheeling current IF = 20 A ﬂows through the load (RL), freewheeling diode (DF), and the large load circuit inductance (LL). The diode reverse recovery current is 20 A and it then decays to zero at the rate of 10 A/µs. The load is rated at 10 and the forward onstate voltage drop is neglected. (a) Draw the current waveform during the reverse recovery (IRR ) and ﬁnd its time (trr ). (b) Calculate the maximum voltage across the diode during this process (IRR ). SOLUTION. (a) A typical current waveform during reverse recovery process is shown in Fig. 2.10 for an ideal diode. When the switch is closed, the steadystate current is, ISS = 200 V/10 = 20 A, since under steadystate condition, the inductor is shorted. When the switch is open, the reverse recovery current ﬂows in the righthand side
20
A. I. Maswood
From t2 to t3 , the current decays to zero at the rate of 20 A/µs. The required time:
I L= 10uH
LL 2
1
t3 − t2 =
+ ldf −
Vs = 200 V
RL
DF Is
FIGURE 2.9 A simple switch mode power supply with freewheeling diode.
Hence the actual reverse recovery time: trr = t3 − t1 = (1 + 1 + 2) − 1 = 3 µs. (b) The diode experiences the maximum voltage just when the switch is open. This is because both the source voltage 200 V and the newly formed voltage due to the change in current through the inductor L. The voltage across the diode: VD = −V +L
diS = −200+(10×10−6 )(−20×106 ) = −400V dt
Tutorial 2.2
20 A 0 s t3 time (s)
t1 20 A t2
FIGURE 2.10 Current through the freewheeling diode during reverse recovery.
loop consisting of the LL, RL, and DF. The load inductance, LL is assumed to be shorted. Hence, when the switch is closed, the loop equation is: V =L
diS dt
from which V 200 diS = = = 20 A/µs dt L 10 At the moment the switch is open, the same current keeps ﬂowing in the righthand side loop. Hence,
t2 − t 1 =
20 A = 1 µs 20 A/µs
Ideal Diode Operation, Mathematical Analysis, and PSPICE Simulation
This tutorial illustrates the operation of a diode circuit. Most of the PE applications operate at a relative high voltage, and in such cases, the voltage drop across the power diode usually is small. It is quite often justiﬁable to use the ideal diode model. An ideal diode has a zero conduction drop when it is forward biased and has zero current when it is reverse biased. The explanation and the analysis presented below is based on the ideal diode model. Circuit Operation A circuit with a single diode and an RL load is shown in Fig. 2.11. The source VS is an alternating sinusoidal source. If VS = Esin(ωt ), then VS is positive when 0 < ωt < π, and VS is negative when π < ωt < 2π. When VS starts becoming positive, the diode starts conducting and the positive source keeps the diode in conduction till ωt reaches π radians. At that instant, deﬁned by ωt = π radians, the current through the circuit is not zero and there is some energy stored in the inductor. The voltage across an inductor is positive when the current through it is increasing and becomes negative when the current through it tends to fall. When the
did diS =− = −20 A/µs dt dt from time zero to time t1 the current will decay at a rate of 20 A/s and will be zero at t1 = 20/20 = 1 µs. The reverse recovery current starts at this point and, according to the given condition, becomes 20 A at t2 . From this point on, the rate of change remains unchanged at 20 A/µs. Period t2 – t1 is found as:
20 A = 2 µs 10 A/µs
Diode
Inductor
VL + VSin −−
VR
FIGURE 2.11 Circuit diagram.
Resistor
2
21
The Power Diode Diode
Inductor +
VL
−−
+ Vsin −−
VR
Resistor
i
FIGURE 2.12 Current increasing, 0 < ωt < π/2.
Diode
Inductor −−
VL
+
+ VSin −−
VR
Resistor
i
FIGURE 2.13 Current decreasing, π/2 < ωt < π.
voltage across the inductor is negative, it is in such a direction as to forward bias the diode. The polarity of voltage across the inductor is as shown in Fig. 2.12 or 2.13. When VS changes from a positive to a negative value, there is current through the load at the instant ωt = π radians and the diode continues to conduct till the energy stored in the inductor becomes zero. After that the current tends to ﬂow in the reverse direction and the diode blocks conduction. The entire applied voltage now appears across the diode.
Mathematical Analysis An expression for the current through the diode can be obtained as shown in the equations. It is assumed that the current ﬂows for 0 < ωt < β, where β > π, when the diode conducts, the driving function for the differential equation is the sinusoidal function deﬁning the source voltage. During the period deﬁned by β < ωt < 2π, the diode blocks current and acts as an open switch. For this period, there is no equation deﬁning the behavior of the circuit. For 0 < ωt < β, Eq. (2.4) applies. di L + R × i = E × sin(θ), where − 0 ≤ θ ≤ β dt di L +R×i =0 dt
di +R×i =0 dθ
(2.6)
i(θ) = A × e −Rθ/ωL
(2.7)
ωL
Given a linear differential equation, the solution is found out in two parts. The homogeneous equation is deﬁned by Eq. (2.5). It is preferable to express the equation in terms of the angle θ instead of “t.” Since θ = ωt , we get that dθ = ω·dt. Then Eq. (2.5) gets converted to Eq. (2.6). Equation (2.7) is the solution to this homogeneous equation and is called the complementary integral. The value of constant A in the complimentary solution is to be evaluated later. The particular solution is the steadystate response and Eq. (2.8) expresses the particular solution. The steadystate response is the current that would ﬂow in steady state in a circuit that contains only the source, resistor, and inductor shown in the circuit, the only element missing being the diode. This response can be obtained using the differential equation or the Laplace transform or the ac sinusoidal circuit analysis. The total solution is the sum of both the complimentary and the particular solution and it is shown in Eq. (2.9). The value of A is obtained using the initial condition. Since the diode starts conducting at ωt = 0 and the current starts building up from zero, i(0) = 0. The value of A is expressed by Eq. (2.10). Once the value of A is known, the expression for current is known. After evaluating A, current can be evaluated at different values of ωt , starting from ωt = π. As ωt increases, the current would keep decreasing. For some values of ωt , say β, the current would be zero. If ωt > β, the current would evaluate to a negative value. Since the diode blocks current in the reverse direction, the diode stops conducting when ωt reaches. Then an expression for the average output voltage can be obtained. Since the average voltage across the inductor has to be zero, the average voltage across the resistor and average voltage at the cathode of the diode are the same. This average value can be obtained as shown in Eq. (2.11). E i(θ) = sin(ωt − α) (2.8) Z where ωl and Z 2 = R 2 + ωl 2 α = a tan R i(θ) = A × e (−Rθ/ωL) + A=
E sin(θ − α) Z
E sin(α) Z
(2.9)
(2.10)
Hence, the average output voltage: (2.4) (2.5)
VOAVG
E = 2π
β sinθ · dθ = 0
E × [1 − cos(β)] 2π
(2.11)
22
A. I. Maswood LT
DT 1
2
V2
3 10 mH
+
RT
Dbreak 5
−
0
FIGURE 2.14 PSPICE model to study an R–L diode circuit.
PSPICE Simulation For simulation using PSPICE, the circuit used is shown in Fig. 2.14. Here the nodes are numbered. The ac source is connected between the nodes 1 and 0. The diode is connected between the nodes 1 and 2 and the inductor links the nodes 2 and 3. The resistor is connected from the node 3 to the reference node, that is, node 0. The circuit diagram is shown in Fig. 2.14. The PSPICE program in textform is presented below. ∗ Halfwave
Rectiﬁer with RL Load exercise to ﬁnd the diode current VIN 1 0 SIN(0 100 V 50 Hz) D1 1 2 Dbreak L1 2 3 10 mH R1 3 0 5 Ohms ∗ An
.MODEL Dbreak D(IS=10N N=1 BV=1200 IBV=10E3 VJ=0.6) .TRAN 10 uS 100 mS 60 mS 100 uS .PROBE .OPTIONS (ABSTOL=1N RELTOL=.01 VNTOL=1MV) .END The diode is described using the MODEL statement. The TRAN statement simulates the transient operation for a period of 100 ms at an interval of 10 ms. The OPTIONS statement sets limits for tolerances. The output can be viewed on the screen because of the PROBE statement. A snapshot of various voltages/currents is shown in Fig. 2.15. From Fig. 2.15, it is evident that the current lags the source voltage. This is a typical phenomenon in any inductive circuit and is associated with the energy storage property of the inductor. This property of the inductor causes the current tochange slowly, governed by the time constant τ = tan−1 ωl/R . Analytically, this is calculated by the expression in Eq. (2.8).
2.7 Typical Applications of Diodes A. In rectiﬁcation Four diodes can be used to fully rectify an ac signal as shown in Fig. 2.16. Apart from other rectiﬁer circuits, this topology does not require an input transformer. However, they are used for isolation and protection. The direction of the current is decided by two diodes conducting at any given time. The direction of the current through the load is always the same. This rectiﬁer topology is known as the full bridge rectiﬁer.
100 Current through the diode (Note the phase shift between V and I)
Input voltage 100 00V
V(V2:+)
I(DT)∗5 Voltage across R
Voltage across L L>> 00V
FIGURE 2.15 Voltage/current waveforms at various points in the circuit.
2
23
The Power Diode
D1
D3
D4
D2
RL
VS
D1, D2 Conducting
0ms
D3, D4 Conducting
80ms
70ms
90ms
FIGURE 2.16 Full bridge rectiﬁer and its output dc voltage.
C. As voltage multiplier Connecting diode in a predetermined manner, an ac signal can be doubled, tripled, and even quadrupled. This is shown in Fig. 2.18. As evident, the circuit will yield a dc voltage equal to 2Vm . The capacitors are alternately charged to the maximum value of the input voltage.
The average rectiﬁer output voltage: Vdc =
2Vm , where Vm is the peak input voltage π
The rms rectiﬁer output voltage: Vm Vrms = √ 2 This rectiﬁer is twice as efﬁcient as compared to a single phase one.
Doubler Quadrupler
The output voltage is clamped between zero and 2Vm .
FIGURE 2.18 Voltage doubler and quadrupler circuit.
Vc −
+
2Vm Vm
−
Vo Vm cos(ωt)
+2Vm−−
+2Vm−−
Vo = Vc + Vi = Vm (1 + sin(ωt ))
+
+2Vm−−
+Vm−−
Vm sin(ωt)
B. For voltage clamping Figure 2.17 shows a voltage clamper. The negative pulse of the sinusoidal input voltage charges the capacitor to its maximum value in the direction shown. After charging, the capacitor cannot discharge, since it is open circuited by the diode. Hence the output voltage:
−
0
FIGURE 2.17 Voltage clamping with diode.
Vo
Vi
24
A. I. Maswood
2.8 Standard Datasheet for Diode Selection In order for a designer to select a diode switch for speciﬁc applications, the following tables and standard test results can be used. A power diode is primarily chosen based on
forward current (IF ) and the peak inverse (VRRM ) voltage. For example, the designer chooses the diode type V30 from the table in Fig. 2.19 because it closely matches their calculated values of IF and VRRM without going over. However, if for some reason only the VRRM matches but the calculated value of IF comes higher, one should go for diode H14, and so on. Similar concept is used for VRRM .
GeneralUse Rectifier Diodes Glass Molded Diodes IF(AV) (A) 0.4 1.0 1.1 1.3 2.5 3.0
VRRM(V) Type V30 H14 V06 V03 U05 U15
50 100 200 300 400 500 600 800 1000 1300 1500 
 yes yes yes yes yes yes yes yes  yes  yes yes  yes  yes  yes yes  yes

yes yes yes yes


yes yes
yes yes yes yes
yes yes 
yes 
yes 



FIGURE 2.19 Table of diode selection based on average forward current, IF (AV ) and peak inverse voltage, VRRM (courtesy of Hitachi semiconductors).
ABSOLUTE MAXIMUM RATINGS Item
Type
V30J
V30L
V30M
V30N
Repetitive Peak Reverse Voltage
VRRM
V
800
1000
1300
1500
NonRepetitive Peak Reverse Voltage
VRSM
V
1000
1300
1600
1800
Average Forward Current
IF(AV)
A
Surge(NonRepetitive) Forward Current
IFSM
A
I2t Limit Value
I2t
A2s
3.6 (Time = 2 ~ 10 ms, I = RMS value)
Operating Junction Temperature
Tj
°C
−50 ~ +150
Storage Temperature
Ts1g
°C
−50 ~ +150
Notes
Singlephase half sine wave 180° conduction 0.4 TL = 100°C, Lead length = 10 mm
(
)
30 (Without PIV, 10 ms conduction, Tj = 150°C start)
(1) Lead Mounting: Lead temperature 300°C max. to 3.2 mm from body for 5 sec. max. (2) Mechanical strength: Bending 90° × 2 cycles or 180° × 1 cycle, Tensile 2kg, Twist 90° × l cycle.
CHARACTERISTICS (TL=25°C) Symbols
Units
Min.
Typ.
Max.
Peak Reverse Current
IRRM
µA
–
0.6
10
All class Rated VRRM
Peak Forward Voltage
VFM
V
–
–
1.3
IFM = 0.4 Ap, Singlephase half sine wave 1 cycle
trr
µs
–
3.0
–
°C/W
–
–
80 50
Item
Reverse Recovery Time Steady State Thermal Impedance
Rth(ja) Rth(j1)
Test Conditions
IF = 2 mA, VR =−15 V Lead length = 10 mm
FIGURE 2.20 Details of diode characteristics for diode V30 selected from Fig. 2.19.
25
The Power Diode
In addition to the above mentioned diode parameters, one should also calculate parameters like the peak forward voltage, reverse recovery time, case and junction temperatures, etc. and check them against the datasheet values. Some of these datasheet values are provided in Fig. 2.20 for the selected diode V30. Figures 2.21–2.23 give the standard experimental relationships between voltages, currents, power, and case temperatures for our selected V30 diode. These characteristics help a designer to understand the safe operating area for the diode, and to make a decision whether or not to use a snubber or a heat sink. If one is particularly interested in the actual reverse recovery time measurement, the circuit given in Fig. 2.24 can be constructed and experimented upon. Forward characteristic
200
Singlephase half sine wave 180° conduction (50 Hz)
160 L = 10 mm 20 mm 25 mm
120
80 L
L
40 PC board (100x180x1.6t) Copper foil (5.5)
0
0
0.1 0.2 0.3 0.4 0.5 Average forward current (A)
Singlephase half sine wave Conduction : 10ms 1 cycle
10
Reverse recovery time(trr) test circuit
TL = 150°C
50 µf
TL = 25°C
D.U.T 0 2mA
22 µs
600 Ω
0.1Irp
lrp
15 V trr
0
1 2 3 4 Peak forward voltage drop (V)
5
FIGURE 2.24 Reverse recovery time (trr ) measurement.
FIGURE 2.21 Variation of peak forward voltage drop with peak forward current. Max. average forward power dissipation (Resistive or inductive load) Max. average forward power dissipation (W)
t
−15 V
1.0
0.1
0.6
FIGURE 2.23 Maximum allowable case temperature with variation of average forward current.
100
Peak forward current (A)
Max. allowable ambient temperature (Resistive or inductive load) Max. allowable ambient temperature (°C)
2
1. N. Lurch, Fundamentals of Electronics, 3rd ed., John Wiley & Sons Ltd., New York, 1981. 2. R. Tartar, SolidState Power Conversion Handbook, John Wiley & Sons Ltd., New York, 1993. 3. R.M. Marston, Power Control Circuits Manual, Newnes circuits manual series. Butterworth Heinemann Ltd., New York, 1995. 4. Internet information on “Hitachi Semiconductor Devices,” http://semiconductor.hitachi.com. 5. International rectiﬁer, Power Semiconductors Product Digest, 1992/93. 6. Internet information on, “Electronic Devices & SMPS Books,” http://www.smpstech.com/books/booklist.htm.
0.8 DC
0.6 Singlephase(50Hz)
0.4
0.2
0
0
0.1 0.2 0.3 0.4 0.5 Average forward current (A)
References
0.6
FIGURE 2.22 Variation of maximum forward power dissipation with average forward current.
3 Power Bipolar Transistors Marcelo Godoy Simoes, Ph.D. Engineering Division, Colorado School of Mines, Golden, Colorado, USA
3.1 3.2 3.3 3.4 3.5 3.6 3.7
Introduction .......................................................................................... Basic Structure and Operation................................................................... Static Characteristics ............................................................................... Dynamic Switching Characteristics............................................................. Transistor Base Drive Applications............................................................. SPICE Simulation of Bipolar Junction Transistors ........................................ BJT Applications..................................................................................... Further Reading .....................................................................................
3.1 Introduction The ﬁrst transistor was discovered in 1948 by a team of physicists at the Bell Telephone Laboratories and soon became a semiconductor device of major importance. Before the transistor, ampliﬁcation was achieved only with vacuum tubes. Even though there are now integrated circuits with millions of transistors, the ﬂow and control of all the electrical energy still require single transistors. Therefore, power semiconductors switches constitute the heart of modern power electronics. Such devices should have larger voltage and current ratings, instant turnon and turnoff characteristics, very low voltage drop when fully on, zero leakage current in blocking condition, ruggedness to switch highly inductive loads which are measured in terms of safe operating area (SOA) and reversebiased second breakdown (ES/b), high temperature and radiation withstand capabilities, and high reliability. The right combination of such features restrict the devices suitability to certain applications. Figure 3.1 depicts voltage and current ranges, in terms of frequency, where the most common power semiconductors devices can operate. The plot gives actually an overall picture where power semiconductors are typically applied in industries: high voltage and current ratings permit applications in large motor drives, induction heating, renewable energy inverters, high voltage DC (HVDC) converters, static VAR compensators, and active ﬁlters, while low voltage and highfrequency applications concern switching mode power supplies, resonant converters, and motion control systems, low frequency with high current and voltage devices are restricted to cycloconverterfed and multimegawatt drives.
27 28 29 32 33 36 37 39
Powernpn or pnp bipolar transistors are used to be the traditional component for driving several of those industrial applications. However, insulated gate bipolar transistor (IGBT) and metal oxide ﬁeld effect transistor (MOSFET) technology have progressed so that they are now viable replacements for the bipolar types. Bipolarnpn or pnp transistors still have performance areas in which they may be still used, for example they have lower saturation voltages over the operating temperature range, but they are considerably slower, exhibiting long turnon and turnoff times. When a bipolar transistor is used in a totempole circuit the most difﬁcult design aspects to overcome are the based drive circuitry. Although bipolar transistors have lower input capacitance than that of MOSFETs and IGBTs, they are current driven. Thus, the drive circuitry must generate high and prolonged input currents. The high input impedance of the IGBT is an advantage over the bipolar counterpart. However, the input capacitance is also high. As a result, the drive circuitry must rapidly charge and discharge the input capacitor of the IGBT during the transition time. The IGBTs low saturation voltage performance is analogous to bipolar powertransistor performance, even over the operatingtemperature range. The IGBT requires a –5 to 10 V gate–emitter voltage transition to ensure reliable output switching. The MOSFET gate and IGBT are similar in many areas of operation. For instance, both devices have high input impedance, are voltagedriven, and use less silicon than the bipolar power transistor to achieve the same drive performance. Additionally, the MOSFET gate has high input capacitance, which places the same requirements on the gatedrive circuitry as the IGBT employed at that stage. The IGBTs 27 Copyright © 2001 by Academic Press
28
M. G. Simoes 1 Mhz
100 kHz 10 kHz
Power Mosfet IGBT
Frequency
Frequency
1 Mhz
BJT
100 kHz 10 kHz
Power Mosfet MCT IGBT
MCT 1 kHz
BJT
1 kHz
GTO
GTO
Thyristor 1 kV
2 kV 3 kV Voltage
Thyristor 4 kV
5 kV
1 kA
(a)
3 kA
2 kA Current
(b)
FIGURE 3.1 Power semiconductor operating regions; (a) voltage vs frequency and (b) current vs frequency.
outperform MOSFETs when it comes to conduction loss vs supplyvoltage rating. The saturation voltage of MOSFETs is considerably higher and less stable over temperature than that of IGBTs. For such reasons, during the 1980s, the insulated gate bipolar transistor took the place of bipolar junction transistors (BJTs) in several applications. Although the IGBT is a cross between the bipolar and MOSFET transistor, with the output switching and conduction characteristics of a bipolar transistor, but voltagecontrolled like a MOSFET, early IGBT versions were prone to latch up, which was largely eliminated. Another characteristic with some IGBT types is the negative temperature coefﬁcient, which can lead to thermal runaway and making the paralleling of devices hard to effectively achieve. Currently, this problem is being addressed in the latest generations of IGBTs. It is very clear that a categorization based on voltage and switching frequency are two key parameters for determining whether a MOSFET or IGBT is the better device in an application. However, there are still difﬁculties in selecting a component for use in the crossover region, which includes voltages of 250–1000 V and frequencies of 20–100 kHz. At voltages below 500 V, the BJT has been entirely replaced by MOSFET in power applications and has been also displaced in higher voltages, where new designs use IGBTs. Most of regular industrial needs are in the range of 1–2 kV blocking voltages, 200–500 A conduction currents, and switching speed of 10–100 ns. Although on the last few years, new high voltage projects displaced BJTs towards IGBT, and it is expected to see a decline in the number of new power system designs that incorporate BJTs, there are still some applications for BJTs; in addition the huge builtup history of equipments installed in industries make the BJT yet a lively device.
3.2 Basic Structure and Operation The bipolar junction transistor (BJT) consists of a threeregion structure of ntype and ptype semiconductor materials, it
vCE _ +
Forwardbiased junction iE vBE Emitter
N
P
N
_ +
iC Reversebiased junction
iB Base
Collector
holes flow
electrons injection
FIGURE 3.2 Structure of a planar bipolar junction transistor.
can be constructed as npn as well as pnp. Figure 3.2 shows the physical structure of a planar npn BJT. The operation is closely related to that of a junction diode where in normal conditions the pn junction between the base and collector is forwardbiased (VBE > 0) causing electrons to be injected from the emitter into the base. Since the base region is thin, the electrons travel across arriving at the reversebiased base– collector junction (VBC < 0) where there is an electric ﬁeld (depletion region). Upon arrival at this junction the electrons are pulled across the depletion region and draw into the collector. These electrons ﬂow through the collector region and out the collector contact. Because electrons are negative carriers, their motion constitutes positive current ﬂowing into the external collector terminal. Even though the forwardbiased base–emitter junction injects holes from base to emitter they do not contribute to the collector current but result in a net current ﬂow component into the base from the external base terminal. Therefore, the emitter current is composed of those two components: electrons destined to be injected across the base–emitter junction, and holes injected from the base into the emitter. The emitter current is exponentially related to the base–emitter voltage by the equation: iE = iE0 (e VBE /ηVT − 1)
(3.1)
3
29
Power Bipolar Transistors
where iE is the saturation current of the base–emitter junction which is a function of the doping levels, temperature, and the area of the base–emitter junction, VT is the thermal voltage Kt/q, and η is the emission coefﬁcient. The electron current arriving at the collector junction can be expressed as a fraction α of the total current crossing the base–emitter junction iC = αiE
(3.2)
Since the transistor is a three terminals device, iE is equal to iC + iB , hence the base current can be expressed as the remaining fraction iB = (1 − α)iE
(3.3)
The collector and base currents are thus related by the ratio α iC =β = iB 1−α
(3.4)
The values of α and β for a given transistor depend primarily on the doping densities in the base, collector, and emitter regions, as well as on the device geometry. Recombination and temperature also affect the values for both parameters. A power transistor requires a large blocking voltage in the off state and a high current capability in the on state, and a vertically oriented four layers structures as shown in Fig. 3.3 is preferable because it maximizes the crosssectional area through which the current ﬂows, enhancing the onstate resistance and power dissipation in the device. There is an intermediate collector region with moderate doping, the emitter region is controlled so as to have an homogenous electrical ﬁeld. Optimization of doping and base thickness are required to achieve high breakdown voltage and ampliﬁcation capabilities.
Base
Power transistors have their emitters and bases interleaved to reduce parasitic ohmic resistance in the base current path and also improving the device for second breakdown failure. The transistor is usually designed to maximize the emitter periphery per unit area of silicon, in order to achieve the highest current gain at a speciﬁc current level. In order to ensure those transistors have the greatest possible safety margin, they are designed to be able to dissipate substantial power and, thus, have low thermal resistance. It is for this reason, among others, that the chip area must be large and that the emitter periphery per unit area is sometimes not optimized. Most transistor manufacturers use aluminum metalization, since it has many attractive advantages, among these are ease of application by vapor deposition and ease of deﬁnition by photolithography. A major problem with aluminum is that only a thin layer can be applied by normal vapor deposition techniques. Thus, when high currents are applied along the emitter ﬁngers, a voltage drop occurs along them, and the injection efﬁciency on the portions of the periphery that are furthest from the emitter contact is reduced. This limits the amount of current each ﬁnger can conduct. If copper metalization is substituted for aluminum, then it is possible to lower the resistance from the emitter contact to the operating regions of the transistors (the emitter periphery). From a circuit point of view, the Eqs. (3.1)–(3.4) are used to relate the variables of the BJT input port (formed by base (B) and emitter (E)) to the output port (collector (C) and emitter (E)). The circuit symbols are shown in Fig. 3.4. Most of the power electronics applications use npn transistor because electrons move faster than holes, and therefore, npn transistors have considerable faster commutation times. Collector Base
Base
Emitter N+
P
N+
N
Collector
FIGURE 3.3 Power transistor vertical structure.
Emitter
Emitter (a)
Collector (b)
FIGURE 3.4 Circuit symbols: (a) npn transistor and (b) pnp transistor.
3.3 Static Characteristics Device static ratings determine the maximum allowable limits of current, voltage, and power dissipation. The absolute voltage limit mechanism is concerned to the avalanche such that thermal runaway does not occur. Forward current ratings are speciﬁed at which the junction temperature does not exceed a rated value, so leads and contacts are not evaporated. Power dissipated in a semiconductor device produces
30
M. G. Simoes iB
iC
VCE, sat Increasing base current
VBE
VCE
Vf Saturation region (a)
Constantcurrent (active) region iC =
iB (b)
FIGURE 3.5 Family of current–voltage characteristic curves: (a) base–emitter input port and (b) collector–emitter output port.
Current Gain ( )
a temperature rise and are related to the thermal resistance. A family of voltage–current characteristic curves is shown in Fig. 3.5. Figure 3.5a shows the base current iB plotted as a function of the base–emitter voltage VBE and Fig. 3.5b depicts the collector current iC as a function of the collector–emitter voltage VCE with iB as the controlling variable. Figure 3.5 shows several curves distinguished each other by the value of the base current. The active region is deﬁned where ﬂat, horizontal portions of voltage–current curves show “constant” iC current, because the collector current does not change signiﬁcantly with VCE for a given iB . Those portions are used only for small signal transistor operating as linear ampliﬁers. Switching power electronics systems on the other hand require transistors to operate in either the saturation region where VCE is small or in the cut off region where the current is zero and the voltage is uphold by the device. A small base current drives the ﬂow of a much larger current between collector and emitter, such gain called beta (Eq. (3.4)) depends upon temperature, VCE and iC . Figure 3.6 shows current gain increase with increased collector voltage; gain falls off at both high and low current levels.
VCE = 2 V (125 °C) VCE = 400 V (25 °C)
VCE = 2 V (25 °C)
log(iC)
FIGURE 3.6 Current gain depends on temperature, VCE and iC.
T1
T2 D1
FIGURE 3.7 Darlington connected BJTs.
High voltage BJTs typically have low current gain, and hence Darlington connected devices, as indicated in Fig. 3.7 are commonly used. Considering gains β1 and β2 for each one of those transistors, the Darlington connection will have an increased gain of β1 + β2 + β1 β2 , diode D1 speedsup the turnoff process, by allowing the base driver to remove the stored charge on the transistor bases. Vertical structure power transistors have an additional region of operation called quasisaturation, indicated in the characteristics curve of Fig. 3.8. Such feature is a consequence of the lightly doped collector drift region where the collector–base junction supports a low reverse bias. If the transistor enters in the hardsaturation region the onstate power dissipation is minimized, but has to be traded off with the fact that in quasisaturation the stored charges are smaller. At high collector currents beta gain decreases with increased temperature and with quasisaturation operation such negative feedback allows careful device paralleling. Two mechanisms on microelectronic level determine the fall off in beta, namely
3
31
Power Bipolar Transistors
iC
i C limit
quasisaturation iC breakdown
hard saturation
PulsedSOA P tot limit
iCM
constantcurrent
Secondary breakdown limit
iB
iB
VCE
VCE limit (VCEO)
cutoff BVSUS BVCEO BVCBO
VCE
FIGURE 3.8 Voltage–current characteristics for a vertical power transistor.
BVCE0
FIGURE 3.9 Forwardbias safe operating area (FBSOA).
conductivity modulation and emitter crowding. One can note that there is a region called primary breakdown due to conventional avalanche of the C–B junction and the attendant large ﬂow of current. The BVSUS is the limit for primary breakdown, it is the maximum collector–emitter voltage that can be sustained across the transistor when it is carrying high collector current. The BVSUS is lower than BVCEO or BVCBO which measure the transistor’s voltage standoff capability when the base current is zero or negative. The bipolar transistor have another potential failure mode called second breakdown, which shows as a precipitous drop in the collector–emitter voltage at large currents. Because the power dissipation is not uniformly spread over the device but it is rather concentrated on regions make the local gradient of temperature can rise very quickly. Such thermal runaway brings hot spots which can eventually melt and recrystallize the silicon resulting in the device destruction. The key to avoid second breakdown is to (1) keep power dissipation under control, (2) use a controlled rate of change of base current during turnoff, (3) use of protective snubbers circuitry, and (4) positioning the switching trajectory within the safe operating area (SOA) boundaries. In order to describe the maximum values of current and voltage, to which the BJT should be subjected two diagrams, are used: the forwardbias safe operating area (FBSOA) given in Fig. 3.9 and the reversebias safe operating area (RBSOA) shown in Fig. 3.10. In the FBSOA the current ICM is the maximum current of the device, there is a boundary deﬁning the maximum thermal dissipation and a margin deﬁning the second breakdown limitation. Those regions are expanded for switching mode operation. Inductive load generates a higher peak energy at turnoff than its resistive counterpart. It is then possible to have a secondary breakdown failure if RBSOA is exceeded. A reverse base current helps the cut off characteristics expanding RBSOA. The RBSOA curve shows that for voltages below VCEO the safe area is independent of reverse bias voltage VEB and is only limited by the device collector current, whereas above VCEO the collector current must be
iC
Reversebias voltage VEB
VCE VCE0
VCB0
FIGURE 3.10 Reversebias safe operating area (RBSOA).
under control depending upon the applied reversebias voltage, in addition temperature effects derates the SOA. Ability for the transistor to switch high currents reliably is thus determined by its peak power handling capabilities. This ability is dependent upon the transistor’s current and thermal density throughout the active region. In order to optimize the SOA capability, the current density and thermal density must be low. In general, it is the hot spots occurring at the weakest area of the transistor that will cause a device to fail due to second breakdown phenomena. Although a wide base width will limit the current density across the base region, good heat sinking directly under the collector will enable the transistor to withstand high peak power. When the power and heat are spread over a large silicon area, all of these destructive tendencies are held to a minimum, and the transistor will have the highest SOA capability. When the transistor is on, one can ignore the base current losses and calculate the power dissipation on the on state (conduction losses) by Eq. (3.5). Hard saturation minimizes
32
M. G. Simoes
Base current
Switching characteristics are important to deﬁne the device velocity in changing from conduction (on) to blocking (off) states. Such transition velocity is of paramount importance also because most of the losses are due to highfrequency switching. Figure 3.11 shows typical waveforms for a resistive load. Index “r” refers to the rising time (from 10 to 90% of maximum value), for example tri is the current rise time which depends upon the base current. The falling time is indexed by “f”; the parameter tﬁ is the current falling time, i.e. when the transistor is blocking such time corresponds to crossing from the saturation to the cut off state. In order to improve tﬁ the base current for blocking must be negative and the device must be kept in quasisaturation to minimize the stored charges. The delay time is denoted by td , corresponding to the time to discharge the capacitance of base–emitter junction, which can be reduced with a larger current base with high slope. Storage time (ts ) is a very important parameter for BJT transistor, it is the required time to neutralize the carriers stored in the collector and base. Storage time and switching losses are key points to deal extensively with bipolar power transistors. Switching losses occur at both turnon and turnoff and for high frequency operation the rising and falling times for voltage and current transitions play important role as indicated by Fig. 3.12. A typical inductive load transition is indicated in Fig. 3.13. The ﬁgure indicates a turnoff transition. Current and voltage are interchanged at turnon and an approximation based upon on straight line switching intervals (resistive load) gives the
ts
Collector current
3.4 Dynamic Switching Characteristics
td
tri ton
tfv
tfv
VCE, SAT
Switching losses Conduction losses
FIGURE 3.12 Inductive load switching characteristics.
switching losses by Eq. (3.6). Ps =
90%
tf
toff
Voltage VCE
(3.5)
Power
PON = IC VCE(sat )
Base voltage
collector–emitter voltage, decreasing onstate losses.
VS IM τfs 2
(3.6)
Base current 10% td
tn
ts
90%
tf 90%
Collector current 10%
10% ton
toff
90% VCE, SAT
Voltage VCE 10%
FIGURE 3.11 Resistive load dynamic response.
where τ is the period of the switching interval, and VS and IM are the maximum voltage and current levels as shown in Fig. 3.10. Most advantageous operation is achieved when fast transitions are optimized. Such requirement minimizes switching losses. Therefore, a good bipolar drive circuit highly inﬂuences the transistor performance. A base drive circuit should provide a high forward base drive current (IB1 ) as indicated in Fig. 3.14 to ensure the power semiconductor turnon quickly. Base drive current should keep the BJT fully saturated to minimize forward conduction losses, but a level IB2 would maintain the transistor in quasisaturation avoiding excess of charges
3
33
Power Bipolar Transistors
Voltage, Current
Voltage, Current
(a)
(b)
FIGURE 3.13 Turnoff voltage and current switching transition: (a) inductive load and (b) resistive load.
dIB dt
IB1 IB2
dIB +Vcc
dt IBR
T2
FIGURE 3.14 Recommended base current for BJT driving.
in base. Controllable slope and reverse current IBR sweeps out stored charges in the transistor base, speeding up the device turnoff.
R2
R1
D1
Tp
T3
T1
R3
R4
3.5 Transistor Base Drive Applications –Vcc
A plethora of circuits have been suggested to successfully command transistors for operating in power electronics switching systems. Such base drive circuits try to satisfy the following requirements: supply the right collector current, adapt the base current to the collector current, and extract a reverse current from base to speed up the device blocking. A good base driver reduces the commutation times and total losses, increasing efﬁciency and operating frequency. Depending upon the grounding requirements between the control and the power circuits, the base drive might be isolated or nonisolated types. Fig. 3.15 shows a nonisolated circuit. When T1 is switched on T2 is driven and diode D1 is forwardbiased providing a reversebias keeping T3 off. The base current IB is positive and saturates the power transistor TP . When T1 is switched off, T3 switches on due to the negative path provided by R3 , and –VCC , providing a negative current for switching off the power transistor TP . When a negative power supply is not provided for the base drive, a simple circuit like Fig. 3.16 can be used in low power applications (step per motors, small dc–dc converters, relays, pulsed circuits). When the input signal is high, T1 switches on and a positive current goes to TP keeping the capacitor charged with the zener voltage, when the input signal goes low
FIGURE 3.15 Nonisolated base driver.
+Vcc R1
T1
C1 Tp Z1
T2
FIGURE 3.16 Base command without negative power supply.
34
M. G. Simoes
D1 TR1 D2
TP
D3 Tp
D4
R1
R2 T1
R1 D1
FIGURE 3.17 Antisaturation diodes (Baker’s clamp) improve power transistor storage time.
T2 provides a path for the discharge of the capacitor, imposing a pulsed negative current from the base–emitter junction of TP . A combination of large reverse base drive and antisaturation techniques may be used to reduce storage time to almost zero. A circuit called Baker’s clamp may be employed as illustrated in Fig. 3.17. When the transistor is on, its base is two diode drops below the input. Assuming that diodes D2 and D3 have a forwardbias voltage of about 0.7 V, then the base will be 1.4 V below the input terminal. Due to diode D1 the collector is one diode drop, or 0.7 V below the input. Therefore, the collector will always be more positive than the base by 0.7 V, staying out of saturation, and because collector voltage increases, the gain β also increases a little bit. Diode D4 provides a negative path for the reverse base current. The input base current can be supplied by a driver circuit similar to the one discussed in Fig. 3.15. Several situations require ground isolation, offline operation, ﬂoating transistor topology, in addition safety needs may call for an isolated base drive circuit. Numerous circuits have been demonstrated in switching power supplies isolated topologies, usually integrating base drive requirements with their power transformers. Isolated base drive circuits may provide either constant current or proportional current excitation. A very popular base drive circuit for ﬂoating switching transistor is shown in Fig. 3.18. When a positive voltage is impressed on the secondary winding (VS ) of TR1 a positive current ﬂows into the base of the power transistor TP which switches on (resistor R1 limits the base current). The capacitor C1 is charged by (VS –VD1 –VBE ) and T1 is kept blocked because the diode D1 reverse biases T1 base–emitter. When VS is zipped off, the capacitor voltage VC brings the emitter of T1 to a negative potential with respect to its base. Therefore, T1 is excited so as to switch on and start pulling a reverse current from TP base. Another very effective circuit is shown in
C1
FIGURE 3.18 Isolated base drive circuit.
R1
TP R2
T1
D1
FIGURE 3.19 Transformer coupled base drive with tertiary winding transformer.
Fig. 3.19 with a minimum number of components. The base transformer has a tertiary winding which uses the energy stored in the transformer to generate the reverse base current during the turnoff command. Other conﬁgurations are also possible by adding to the isolated circuits the Baker clamp diodes, or zener diodes with paralleled capacitors. Sophisticated isolated base drive circuits can be used to provide proportional base drive currents where it is possible to control the value of β, keeping it constant for all collector currents leading to shorter storage time. Figure 3.20 shows one of the possible ways to realize a proportional base drive circuit. When transistor T1 turns on, the transformer TR1 is in negative saturation and the power transistor TP is off. During the time that T1 is on, a current ﬂows through winding N1 , limited by resistor R1 , storing energy in the transformer, holding
3
35
Power Bipolar Transistors +Vcc N1
N2
C1
R1 D1
Tp
T1
Z1 N3
N4
R2
FIGURE 3.20 Proportional base drive circuit.
it into saturation. When the transistor T1 turns off, the energy stored in N1 is transferred to winding N4 , pulling the core from negative to positive saturation. The windings N2 and N4 will withstand as a current source, the transistor TP will stay on and the gain β will be imposed by the turns ratio given by Eq. (3.7). β=
N4 N2
R
D1
Tp
(3.7)
In order to use the proportional drive given in Fig. 3.20 careful design of the transformer must be done, so as to have ﬂux balanced which will keep core under saturation. The transistor gain must be somewhat higher than the value imposed by the transformer turns ratio, which requires cautious device matching. The most critical portion of the switching cycle occurs during transistor turnoff, since normally reverse base current is made very large in order to minimize storage time, such conditions may avalanche the base–emitter junction leading to destruction. There are two options to prevent this from happening: turning off the transistor at low values of collector–emitter voltage (which is not practical in most of the applications) or reducing collector current with rising collector voltage, implemented by RC protective networks called snubbers. Therefore, an RC snubber network can be used to divert the collector current during the turnoff improving the RBSOA in addition the snubber circuit dissipates a fair amount of switching power relieving the transistor. Figure 3.21 shows a turnoff snubber network; when the power transistor is off, the capacitor C is charged through diode D1 . Such collector current ﬂows temporarily into the capacitor as the collectorvoltage rises; as the power transistor turns on,
D
C
FIGURE 3.21 Turnoff snubber network.
the capacitor discharges through the resistor R back into the transistor. It is not possible to fully develop all the aspects regarding simulation of BJT circuits. Before giving an example some comments are necessary regarding modeling and simulation of BJT circuits. There are a variety of commercial circuit simulation programs available on the market, extending from a set of functional elements (passive components, voltage controlled current sources, semiconductors) which can be used to model devices, to other programs with the possibility of
36
M. G. Simoes
implementation of algorithm relationships. Those streams are called subcircuit (building auxiliary circuits around a SPICE primitive) and mathematical (deriving models from internal device physics) methods. Simulators can solve circuit equations exactly, given models for the nonlinear transistors, and predict the analog behavior of the node voltages and currents in continuous time. They are costly in computer time and such programs have not been written to usually serve the needs of designing power electronic circuits, rather for designing lowpower and lowvoltage electronic circuits. Therefore, one has to decide which approach should be taken for incorporating BJT power transistor modeling, and a tradeoff between accuracy and simplicity must be considered. If precise transistor modeling are required subcircuit oriented programs should be used. On the other hand, when simulation of complex power electronic system structures, or novel power electronic topologies are devised, the switch modeling should be rather simple, by taking in consideration fundamental switching operations, and a mathematical oriented simulation program should be used.
3.6 SPICE Simulation of Bipolar Junction Transistors SPICE is a generalpurpose circuit program that can be applied to simulate electronic and electrical circuits and predict the circuit behavior. SPICE was originally developed at the Electronics Research Laboratory of the University of California, Berkeley (1975), the name stands for: Simulation Program for Integrated Circuits Emphasis. A circuit must be speciﬁed in terms of element names, element values, nodes, variable parameters, and sources. SPICE can do several types of circuit analyses: • • • • • • • •
Nonlinear dc analysis, calculating the dc transference. Nonlinear transient analysis: calculates signals as a function of time. Linear ac analysis: computes a bode plot of output as a function of frequency. Noise analysis. Sensitivity analysis. Distortion analysis. Fourier analysis. MonteCarlo analysis.
In addition, PSpice has analog and digital libraries of standard components such as operational ampliﬁers, digital gates, ﬂipﬂops. This makes it a useful tool for a wide range of analog and digital applications. An input ﬁle, called source ﬁle, consists of three parts: (1) data statements, with description of the components and the interconnections, (2) control statements, which tells SPICE what type of analysis to perform on the circuit, and (3) output statements, with speciﬁcations of what
outputs are to be printed or plotted. Two other statements are required: the title statement and the end statement. The title statement is the ﬁrst line and can contain any information, while the end statement is always .END. This statement must be a line be itself, followed by a carriage return. In addition, there are also comment statements, which must begin with an asterisk (*) and are ignored by SPICE. There are several model equations for BJTs. SPICE has builtin models for the semiconductor devices, and the user need to specify only the pertinent model parameter values. The model for the BJT is based on the integralcharge model of Gummel and Poon. However, if the Gummel–Poon parameters are not speciﬁed, the model reduces to piecewiselinear EbersMoll model as depicted in Fig. 3.22. In either case, chargestorage effects, ohmic resistances, and a currentdependent output conductance may be included. The forward gain characteristics is deﬁned by the parameters IS and BF , the reverse characteristics by IS and BR . Three ohmic resistances RB , RC , and RE are also included. The two diodes are modeled by voltage sources, exponential equations of Shockley can be transformed into logarithmic ones. A set of device model parameters is deﬁned on a separate .MODEL card and assigned a unique model name. The device element cards in SPICE then reference the model name. This scheme lessens the need to specify all of the model parameters on each device element card. Parameter values are deﬁned by appending the parameter name, as given below for each model type, followed by an equal sign and the parameter value. Model parameters that are not given a value are assigned the default values given below for each model type. As an example, the
Collector iC RC
CBC
F iE
RB
Base iB
CBE
R iC
iE
RE
Emitter FIGURE 3.22 Ebers–Moll transistor model.
3
37
Power Bipolar Transistors iS
VY 1
2
L
3
Q1
io
4
R
6 VS
+ _
RB
DIII Vg 7
+ VD _
+
C
VC _
+ _
5 VX
0
FIGURE 3.23 BJT buck chopper.
model parameters for the 2N2222A NPN transistor is given below: .MODEL Q2N2222A NPN (IS=14.34F XTI=3 EG=1.11 VAF= 74.03 BF=255.9 NE=1.307 ISE=14.34F IKF=.2847 XTB=1.5 BR=6.092 NC=2 ISC=0 IKR=0 RC=1 CJC=7.306P MJC=.3416 VJC=.75 FC=.5 CJE=22.01P MJE=.377 VJE=.75 TR=46.91N TF=411.1P ITF=.6 VTF=1.7 XTF=3 RB=10)
Figure 3.23 shows a BJT buck chopper. The dc input voltage is 12 V, the load resistance R is 5 , the ﬁlter inductance L is 145.84 µH, and the ﬁlter capacitance C is 200 µF. The chopping frequency is 25 kHz and the duty cycle of the chopper is 42% as indicated by the control voltage statement (VG ). The listing below plots the instantaneous load current (IO ), the input current (IS ), the diode voltage (VD ), the output voltage (VC ), and calculate the Fourier coefﬁcients of the input current (IS ). It is suggested for the careful reader to have more details and enhancements on using SPICE for simulations on specialized literature and references. *SOURCE VS 1 0 VY 1 2
DC DC
VG 7 3 *CIRCUIT RB 7 6
250
R L C VX
5 3 5 4
0 4 0 5
12V 0V
;Voltage source to measure input current PULSE 0V 30V 0.1NS 0/1Ns 16.7US 40US)
5 145.8UH 200UF IC=3V DC 0V
;Transistor base resistance
;Initial voltage ;Source to inductor current DM 0 3 DMOD ;Freewheeling diode .MODEL DMOD D(IS=2.22E–15 BV=1200V CJO=O TT=O) Q1 2 6 3 3 2N6546 ;BJT switch .MODEL 2N6546 NPN (IS=6.83E–14 BF=13 CJE=1PF CJC=607.3PF TF=26.5NS)
*ANALYSIS .TRAN 2US 2.1MS 2MS UIC ;Transient analysis .PROBE ;Graphics postprocessor .OPTIONS ABSTOL=1.OON RELTOL=0.01 VNTOL=0.1 ITL5=40000 .FOUR 25KHZ I (VY) ;Fourier analysis .END
3.7 BJT Applications Bipolar junction power transistors are applied to a variety of power electronic functions, switching mode power supplies, dc motor inverters, PWM inverters just to name a few. To conclude the present chapter, three applications are next illustrated. A ﬂyback converter is exempliﬁed in Fig. 3.24. The switching transistor is required to withstand the peak collector voltage at turnoff and peak collector currents at turnon. In order to limit the collector voltage to a safe value, the duty cycle must be kept relatively low, normally below 50%, i.e. 6. < 0.5. In practice, the duty cycle is taken around 0.4, which limits the peak collector. A second design factor which the transistor must meet is the working collector current at turnon, dependent on the primary transformerchoke peak current, the primarytosecondary turns ratio, and the output load current. When the transistor turns on the primary current builds up in the primary winding, storing energy, as the transistor turns off, the diode at the secondary winding is forward biasing, releasing such stored energy into the output capacitor and load. Such transformer operating as a coupled inductor is actually deﬁned as a transformerchoke. The design of the transformerchoke of the ﬂyback converter must be done carefully to avoid saturation because the operation is unidirectional on the B–H characteristic curve. Therefore, a core with a relatively large volume and air gap must be used. An advantage of the ﬂyback circuit is the simplicity by which a multiple output switching power supply may
38
M. G. Simoes On
Off
On
V1 2VIN
D
VIN
VCE C
IL
IS
IP
VIN
RL
IP VCE
IS
V1 IL
IOUT T T
FIGURE 3.24 Flyback converter.
On
Off
On
V1 L
D2
VIN
2VIN C
IP
D3
V1
VIN
IL
IP
D1 VCE
VCE
RL
IDI
ID1
IL
IOUT T T
FIGURE 3.25 Isolated forward converter.
be realized. This is because the isolation element acts as a common choke to all outputs, thus only a diode and a capacitor are needed for an extra output voltage. Figure 3.25 shows the basic forward converter and its associated waveforms. The isolation element in the forward converter is a pure transformer which should not store energy, and therefore, a second inductive element L is required at the output for proper and efﬁcient energy transfer. Notice that
the primary and secondary windings of the transformer have the same polarity, i.e. the dots are at the same winding ends. When the transistor turns on, current builds up in the primary winding. Because of the same polarity of the transfo rmer secondary winding, such energy is forward transferred to the output and also stored in inductor L through diode D2 which is forwardbiased. When the transistor turns off, the transformer winding voltage reverses, backbiasing diode D2
3
39
Power Bipolar Transistors
IS
VCE
IA
IS
VS IA
LA, RA
VCE IF
VA EG
LF , RF
_
VIN T
T
+
VF
Dm
VA
T
FIGURE 3.26 Chopperfed dc drive.
and the ﬂywheel diode D3 is forwardbiased, conducting current in the output loop and delivering energy to the load through inductor L. The tertiary winding and diode D, provide transformer demagnetization by returning the transformer magnetic energy into the output dc bus. It should be noted that the duty cycle of the switch must be kept below 50%, so that when the transformer voltage is clamped through the tertiary winding, the integral of the voltseconds between the input voltage and the clamping level balances to zero. Duty cycles above 50%, i.e. 6 > 0.5, will upset the voltseconds balance, driving the transformer into saturation, which in turn produces high collector current spikes that may destroy the switching transistor. Although the clamping action of the tertiary winding and the diode limit the transistor peak collector voltage to twice the dc input, care must be taken during construction to couple the tertiary winding tightly to the primary (biﬁlar wound) to eliminate voltage spikes caused by leakage inductance. Chopper drives are connected between a ﬁxedvoltage dc source and a dc motor to vary the armature voltage. In addition to armature voltage control, a dc chopper can provide regenerative braking of the motors and can return energy back to the supply. This energysaving feature is attractive to transportation systems as mass rapid transit (MRT), chopper drives are
also used in battery electric vehicles. A dc motor can be operated in one of the four quadrants by controlling the armature or ﬁeld voltages (or currents). It is often required to reverse the armature or ﬁeld terminals in order to operate the motor in the desired quadrant. Figure 3.26 shows a circuit arrangement of a chopperfed dc separately excited motor. This is a onequadrant drive, the waveforms for the armature voltage, load current, and input current are also shown. By varying the duty cycle, the power ﬂow to the motor (and speed) can be controlled.
Further Reading 1. B. K. Bose, Power Electronics and Ac Drives, PrenticeHall, Englewood Cliffs, NJ; 1986. 2. G. C. Chryssis, High Frequency Switching Power Supplies: Theory and Design, McGrawHill, NY; 1984 3. N. Mohan, T. M. Undeland, and W. P. Robbins, Power Electronics: Converters, Applications, and Design, John Wiley & Sons, NY; 1995. 4. M. H. Rashid, Power Electronics: Circuits, Devices, and Applications, PrenticeHall, Englewood Cliffs, NJ; 1993. 5. B.W. Williams, Power Electronics: Devices, Drivers and Applications, John Wiley & Sons, NY; 1987.
4 The Power MOSFET Issa Batarseh, Ph.D. School of Electrical Engineering and Computer Science, University of Central Florida, 4000 Central Florida Blvd., Orlando, Florida, USA
4.1 Introduction .......................................................................................... 41 4.2 Switching in Power Electronic Circuits ....................................................... 42 4.3 General Switching Characteristics .............................................................. 44 4.3.1 The Ideal Switch • 4.3.2 The Practical Switch
4.4 The Power MOSFET ............................................................................... 48 4.4.1 MOSFET Structure • 4.4.2 MOSFET Regions of Operation • 4.4.3 MOSFET Switching Characteristics • 4.4.4 MOSFET PSPICE Model • 4.4.5 MOSFET Largesignal Model • 4.4.6 Current MOSFET Performance
4.5 Future Trends in Power Devices ................................................................ 68 References ............................................................................................. 69
4.1 Introduction In this chapter, an overview of power MOSFET (metal oxide semiconductor ﬁeld effect transistor) semiconductor switching devices will be given. The detailed discussion of the physical structure, fabrication, and physical behavior of the device and packaging is beyond the scope of this chapter. The emphasis here will be given on the terminal i–v switching characteristics of the available device, turnon, and turnoff switching characteristics, PSPICE modeling and its current, voltage, and switching limits. Even though, most of today’s available semiconductor power devices are made of silicon or germanium materials, other materials such as gallium arsenide, diamond, and silicon carbide are currently being tested. One of the main contributions that led to the growth of the power electronics ﬁeld has been the unprecedented advancement in the semiconductor technology, especially with respect to switching speed and power handling capabilities. The area of power electronics started by the introduction of the silicon controlled rectiﬁer (SCR) in 1958. Since then, the ﬁeld has grown in parallel with the growth of the power semiconductor device technology. In fact, the history of power electronics is very much connected to the development of switching devices and it emerged as a separate discipline when high power bipolar junction transistors (BJTs) and MOSFETs devices where introduced in the 1960s and 1970s. Since then, the introduction of new devices has been accompanied with dramatic improvement in power rating and switching
Copyright © 2007, 2001, Elsevier Inc. All rights reserved.
performance. Because of their functional importance, drive complexity, fragility, cost, power electronic design engineer must be equipped with the thorough understanding of the device operation, limitation, drawbacks, and related reliability and efﬁciency issues. In the 1980s, the development of power semiconductor devices took an important turn when new process technology was developed that allowed the integration of MOS and BJT technologies on the same chip. Thus far, two devices using this new technology have been introduced: integrated gate bipolar transistor (IGBT) and MOS controlled thyristor (MCT). Many of the IC processing methods and equipment have been adopted for the development of power devices. However, unlike microelectronic IC’s which process information, power devices IC’s process power, hence, their packaging and processing techniques are quite different. Power semiconductor devices represent the “heart” of modern power electronics, with two major desirable characteristics of power semiconductor devices that guided their development are: the switching speed and power handling capabilities. The improvement of semiconductor processing technology along with manufacturing and packaging techniques has allowed power semiconductor development for high voltage and high current ratings and fast turnon and turnoff characteristics. Today, switching devices are manufactured with amazing power handling capabilities and switching speeds as will be shown later. The availability of different devices with different switching speed, power handling capabilities, size, cost, . . . etc. make it possible to cover many power 41
42
I. Batarseh
electronics applications. As a result, tradeoffs are made when it comes to selecting power devices.
4.2 Switching in Power Electronic Circuits As stated earlier, the heart of any power electronic circuit is the semiconductorswitching network. The question arises here is do we have to use switches to perform electrical power conversion from the source to the load? The answer of course is no, there are many circuits which can perform energy conversion without switches such as linear regulators and power ampliﬁers. However, the need for using semiconductor devices to perform conversion functions is very much related to the converter efﬁciency. In power electronic circuits, the semiconductor devices are generally operated as switches, i.e. either in the onstate or the offstate. This is unlike the case in power ampliﬁers and linear regulators where semiconductor devices operate in the linear mode. As a result, very large amount of energy is lost within the power circuit before the processed energy reaches the output. The need to use semiconductor switching devices in power electronic circuits is their ability to control and manipulate very large amounts of power from the input to the output with a relatively very low power dissipation in the switching device. Hence, resulting in a very high efﬁcient power electronic system. Efﬁciency is considered as an important ﬁgure of merit and has signiﬁcant implications on the overall performance of the system. Low efﬁcient power systems means large amounts of power being dissipated in a form of heat, resulting in one or more of the following implications: 1. Cost of energy increases due to increased consumption. 2. Additional design complications might be imposed, especially regarding the design of device heat sinks. 3. Additional components such as heat sinks increase cost, size, and weight of the system, resulting in low power density. 4. High power dissipation forces the switch to operate at low switching frequency, resulting in limited bandwidth, slow response, and most importantly, the size and weight of magnetic components (inductors and transformers), and capacitors remain large. Therefore, it is always desired to operate switches at very high frequencies. But, we will show later that as the switching frequency increases, the average switching power dissipation increases. Hence, a tradeoff must be made between reduced size, weight, and cost of components vs reduced switching power dissipation, which means inexpensive low switching frequency devices. 5. Reduced component and device reliability.
For more than forty years, it has been shown that in order to achieve high efﬁciency, switching (mechanical or electrical) is the best possible way to accomplish this. However, unlike mechanical switches, electronic switches are far more superior because of their speed and power handling capabilities as well as reliability. We should note that the advantages of using switches don’t come at no cost. Because of the nature of switch currents and voltages (square waveforms), normally high order harmonics are generated in the system. To reduce these harmonics, additional input and output ﬁlters are normally added to the system. Moreover, depending on the device type and power electronic circuit topology used, driver circuit control and circuit protection can signiﬁcantly increase the complexity of the system and its cost. EXAMPLE 4.1 The purpose of this example is to investigate the efﬁciency of four different power circuits whose functions are to take in power from 24 volts dc source and deliver a 12 volts dc output to a 6 resistive load. In other words, the tasks of these circuits are to serve as dc transformer with a ratio of 2:1. The four circuits are shown in Fig. 4.1a–d representing voltage divider circuit, zenerregulator, transistor linear regulator, and switching circuit, respectively. The objective is to calculate the efﬁciency of those four power electronic circuits. SOLUTION. Voltage Divider DC Regulator The ﬁrst circuit is the simplest forming a voltage divider with R = RL = 6 and Vo = 12 volts. The efﬁciency deﬁned as the ratio of the average load power, PL , to the average input power, Pin
η= =
PL % Pin RL % = 50% RL + R
In fact efﬁciency is simply Vo /Vin %. As the output voltage becomes smaller, the efﬁciency decreases proportionally.
Zener DC Regulator Since the desired output is 12 V, we select a zener diode with zener breakdown VZ = 12 V. Assume the zener diode has the i–v characteristic shown in Fig. 4.1e since RL = 6 , the load current, IL , is 2 A. Then we calculate R for IZ = 0.2 A (10% of the load current). This results in R = 5.27 . Since the input power is Pin = 2.2 A × 24 V = 52.8 W and the output power is Pout = 24 W. The efﬁciency of
4
43
The Power MOSFET R
R + Vin
IL
vo
RL
Vin
RL
(b)
(a) vCE
vo _
_
+
+
_ IL +
IL +
S
IB Vin
RL
Control
vo
RL
Vin
_
vo _
(c)
(d)
i(A)
−12V
v(V) 0.01
(e) switch
ON 0
ON
OFF DT
t
T
vo Vin Vo,ave
0
DT
t
T
(f) FIGURE 4.1 (a) Voltage divider; (b) zener regulator; (c) transistor regulator; (d) switching circuit; (e) i–v zener diode characteristics; and (f) switching waveform for S and corresponding output waveform.
44
I. Batarseh
the circuit is given by, η=
24 W % 52.8 W
= 45.5% Transistor DC Regulator It is clear from Fig. 4.1c that for Vo = 12 V, the collector emitter voltage must be around 12 V. Hence, the control circuit must provide base current, IB to put the transistor in the active mode with VCE ≈ 12 V. Since the load current is 2 A, then collector current is approximately 2 A (assume small IB ). The total power dissipated in the transistor can be approximated by the following equation: Pdiss = VCE IC + VBE IB ≈ VCE IC ≈ 12 × 2 = 24 watts Therefore, the efﬁciency of the circuit is 50%. Switching DC Regulator Let us consider the switching circuit of Fig. 4.1d by assuming the switch is ideal and periodically turned on and off is shown in Fig. 4.1f. The output voltage waveform is shown in Fig. 4.1f. Even though the output voltage is not constant or pure dc, its average value is given by,
Vo,ave
1 = T
T0 Vin dt = Vin D 0
where D is the duty ratio equals the ratio of the ontime to the switching period. For Vo,ave = 12 V, we set D = 0.5, i.e. the switch has a duty cycle of 0.5 or 50%. In case, the average output power is 48 W and the average input power is also 48 W, resulting in 100% efﬁciency! This is of course because we assumed the switch is ideal. However, let us assume a BJT switch is used in the above circuit with VCE,sat = 1 V and IB is small, then the average power loss across the switch is approximately 2 W, resulting in overall efﬁciency of 96%. Of course the switching circuit given in this example is over simpliﬁed, since the switch requires additional driving circuitry that was not shown, which also dissipates some power. But still, the example illustrates that high efﬁciency can be acquired by switching power electronic circuits when compared to the efﬁciency of linear power electronic circuits. Also, the difference between the linear circuit in Figs. 4.1b and c and the switched circuit of Fig. 4.1d is that the power delivered to the load in the later case in pulsating between zero and 96 watts. If the application calls for constant
power delivery with little output voltage ripple, then an LC ﬁlter must be added to smooth out the output voltage. The ﬁnal observation is regarding what is known as load regulation and line regulation. The line regulation is deﬁned as the ratio between the change in output voltage, Vo , with respect to the change in the input voltage Vin . This is a very important parameter in power electronics since the dc input voltage is obtained from a rectiﬁed line voltage that normally changes by ±20%. Therefore, any offline power electronics circuit must have a limited or speciﬁed range of line regulation. If we assume the input voltage in Figs. 4.1a,b is changed by 2 V, i.e. Vin = 2 V, with RL unchanged, the corresponding change in the output voltage Vo is 1 V and 0.55 V, respectively. This is considered very poor line regulation. Figures 4.1c,d have much better line and load regulations since the closedloop control compensate for the line and load variations.
4.3 General Switching Characteristics 4.3.1 The Ideal Switch It is always desired to have the power switches perform as close as possible to the ideal case. Device characteristically speaking, for a semiconductor device to operate as an ideal switch, it must possess the following features: 1. No limit on the amount of current (known as forward or reverse current) the device can carry when in the conduction state (onstate); 2. No limit on the amount of the devicevoltage ((known as forward or reverse blocking voltage) when the device is in the nonconduction state (offstate); 3. Zero onstate voltage drop when in the conduction state; 4. Inﬁnite offstate resistance, i.e. zero leakage current when in the nonconduction state; and 5. No limit on the operating speed of the device when changes states, i.e. zero rise and fall times. The switching waveforms for an ideal switch is shown in Fig. 4.2, where isw and vsw are the current through and the voltage across the switch, respectively. Both during the switching and conduction periods, the power loss is zero, resulting in a 100% efﬁciency, and with no switching delays, an inﬁnite operating frequency can be achieved. In short, an ideal switch has inﬁnite speed, unlimited power handling capabilities, and 100% efﬁciency. It must be noted that it is not surprising to ﬁnd semiconductorswitching devices that can almost, for all practical purposes, perform as ideal switches for number of applications.
4
45
The Power MOSFET is w
power gain, surge capacity, and over voltage capacity must be considered when addressing speciﬁc devices for speciﬁc applications. A useful plot that illustrates how switching takes place from on to off and vice versa is what is called switching trajectory, which is simply a plot of isw vs vsw . Figure 4.3b shows several switching trajectories for the ideal and practical cases under resistive loads.
+ vsw _
vsw Voff Von
time
isw Ion
Ioff
time
p(t)
time
FIGURE 4.2 Ideal switching current, voltage, and power waveforms.
4.3.2 The Practical Switch The practical switch has the following switching and conduction characteristics: 1. Limited power handling capabilities, i.e. limited conduction current when the switch is in the onstate, and limited blocking voltage when the switch is in the offstate. 2. Limited switching speed that is caused by the ﬁnite turnon and turnoff times. This limits the maximum operating frequency of the device. 3. Finite onstate and offstate resistance’s i.e. there exists forward voltage drop when in the onstate, and reverse current ﬂow (leakage) when in the offstate. 4. Because of characteristics 2 and 3 above, the practical switch experiences power losses in the on and the off states (known as conduction loss), and during switching transitions (known as switching loss). Typical switching waveforms of a practical switch are shown in Fig. 4.3a. The average switching power and conduction power losses can be evaluated from these waveforms. We should point out the exact practical switching waveforms vary from one device to another device, but Fig. 4.3a is a reasonably good representation. Moreover, other issues such as temperature dependence,
EXAMPLE 4.2 Consider a linear approximation of Fig. 4.3a as shown in Fig. 4.4a: (a) Give a possible circuit implementation using a power switch whose switching waveforms are shown in Fig. 4.4a, (b) Derive the expressions for the instantaneous switching and conduction power losses and sketch them, (c) Determine the total average power dissipated in the circuit during one switching frequency, and (d) The maximum power. SOLUTION. (a) First let us assume that the turnon time, ton , and turnoff time, toff , the conduction voltage VON , and the leakage current, IOFF , are part of the switching characteristics of the switching device and have nothing to do with circuit topology. When the switch is off, the blocking voltage across the switch is VOFF that can be represented as a dc voltage source of value VOFF reﬂected somehow across the switch during the offstate. When the switch is on, the current through the switch equals ION , hence, a dc current is needed in series with the switch when it is in the onstate. This suggests that when the switch turns off again, the current in series with the switch must be diverted somewhere else (this process is known as commutation). As a result, a second switch is needed to carry the main current from the switch being investigated when it’s switched off. However, since isw and vsw are linearly related as shown in Fig. 4.4b, a resistor will do the trick and a second switch is not needed. Figure 4.4 shows a oneswitch implementation with S, the switch and R represents the switchedload. (b) The instantaneous current and voltage waveforms during the transition and conduction times are given as follows
isw (t ) =
t (ION − IOFF ) + IOFF tON
0 ≤ t ≤ tON
ION − t −Ts (I ON − IOFF ) + IOFF t
Ts − tOFF ≤ t ≤ Ts
tON ≤ t ≤ Ts − tOFF
OFF
V OFF − VON − tON × (t − tON ) + VON VON vsw (t ) = VOFF − VON tOFF × t − (Ts − t OFF ) + VON
0 ≤ t ≤ tON tON ≤ t ≤ Ts − tOFF Ts − tOFF ≤ t ≤ Ts
isw + vsw _ vsw
Forward voltage drop Voff
Von
time TurnOFF switching delays
TurnON switching delays
isw Ion
Ioff
time
Leakage current p(t) switching losses Pmax
time
conduction losses Ts
(a)
isw
Typical practical waveform
(Highly inductive load) ON
ION
OFF
OFF ON ON
ON OFF
(Ideal switch) OFF
OFF ON (Resistive load)
(b)
ON
OFF
vsw VOFF
FIGURE 4.3 (a) Practical switching current, voltage, and power waveforms and (b) switching trajectory.
4
47
The Power MOSFET vsw
Vof
isw
f Ion
isw + vsw
Ioff Von
t t=0
_
ton
toff Ts
(a) isw + vsw −
S
Vof
Vof
R
Load
f
f
(b) Psw(t)
IonVoff 4 t 0 ton 2
ton tmax
Ts– toff
(c)
Ts
toff 2
FIGURE 4.4 Linear approximation of typical current and voltage switching waveforms.
It can be shown that if we assume ION IOFF and VOFF VON , then the instantaneous power, p(t) = isw vsw can be given as follows, 0 ≤ t ≤ tON − VOFF2 ION (t − tON ) t tON VON ION tON ≤ t ≤ Ts − tOFF p(t ) = V ION (t − (Ts − tOFF )) (t − Ts ) Ts − tOFF ≤ t ≤ Ts − OFF 2 tOFF
(c) The total average dissipated power is given by
Pave =
1 Ts
Ts 0
t ON 1 VOFF ION p(t )dt = − (t −tON )t dt 2 Ts tON 0
Ts −tOFF
+
VON ION dt tON
Figure 4.4c shows a plot of the instantaneous power where the maximum power during turnon and off is VOFF ION /4.
Ts + Ts −tOFF
−
VOFF ION (t −(Ts −tOFF ))(t −Ts )dt 2 tOFF
48
I. Batarseh
The evaluation of the above integral gives Pave
VOFF ION = Ts +
tON + tOFF 6
Drain(D) D
iD −
VON ION (Ts − tOFF − tON ) Ts
The ﬁrst expression represents the total switching loss, whereas the second expression represents the total conduction loss over one switching cycle. We notice that as the frequency increases, the average power increases linearly. Also the power dissipation increases with the increase in the forward conduction current and the reverse blocking voltage. (d) The maximum power occurs at the time when the ﬁrst derivative of p(t) during switching is set to zero, i.e.
+ VDS
VGD +
−
(G)
Gate(G) +
VGS
(S)
Source(S)
−
(b)
(a)
dp(t ) =0 dt t =tmax
D
D
solve the above equation for tmax , we obtain values at turn on and off, respectively, tmax =
trise 2
tmax = T −
G
G
tfall 2
Solving for the maximum power, we obtain
S
(c) Pmax
Voff Ion = 4
S
(d)
FIGURE 4.5 Device symbols: (a) nchannel enhancementmode; (b) pchannel enhancementmode; (c) nchannel depletionmode; and (d) pchannel depletionmode.
4.4 The Power MOSFET Unlike the bipolar junction transistor (BJT), the MOSFET device belongs to the Unipolar Device family, since it uses only the majority carriers in conduction. The development of the metal oxide semiconductor technology for microelectronic circuits opened the way for developing the power metal oxide semiconductor ﬁeld effect transistor (MOSFET) device in 1975. Selecting the most appropriate device for a given application is not an easy task, requiring knowledge about the device characteristics, its unique features, innovation, and engineering design experience. Unlike low power (signal devices), power devices are more complicated in structure, driver design, and understanding of their operational i–v characteristics. This knowledge is very important for power electronics engineer to design circuits that will make these devices close to ideal. The device symbol for a p and nchannel enhancement and depletion types are shown in Fig. 4.5. Figure 4.6 shows the i–v characteristics for the
nchannel enhancementtype MOSFET. It is the fastest power switching device with switching frequency more than 1 MHz, with voltage power ratings up to 1000 V and current rating as high as 300 A. MOSFET regions of operations will be studied shortly.
4.4.1 MOSFET Structure Unlike the lateral channel MOSFET devices used in many IC technology in which the gate, source, and drain terminals are located in the same surface of the silicon wafer, power MOSFET use vertical channel structure in order to increase the device power rating [1]. In the vertical channel structure, the source and drain are in opposite side of the silicon waver. Figure 4.7a shows vertical crosssectional view for a power MOSFET. Figure 4.7b shows a more simpliﬁed representation. There are several discrete types of the vertical structure power MOSFET available commercially today such as VMOSFET,
4
49
The Power MOSFET Drain (D)
+ vDS
Gate (G)
_
+ v G
S
−
Source (S)
(a) iD
Triode (linear region) vDS < vGS– VTh
Saturation region (active region) vDS > vGS– VTh
VGS increases VGS = VTh+1
VGS < VTh vDS
(b) FIGURE 4.6 (a) nChannel enhancementmode MOSFET and (b) its iD vs vDS characteristics.
UMOSFET, DMOSFET, and SMOSFET [1, 2]. The P–N junction between pbase (also referred to as body or bulk region) and the ndrift region provide the forward voltage blocking capabilities. The source metal contact is connected directly to the pbase region through a break in the n+ source region in order to allow for a ﬁxed potential to pbase region during the normal device operation. When the gate and source terminal are set the same potential (VGS = 0), no channel is established in the pbase region, i.e. the channel region remain unmodulated. The lower doping in the ndrift region is needed in order to achieve higher drain voltage blocking capabilities. For the drain–source current, ID , to ﬂow, a conductive path must be established between the n+ and n− regions through the pbase diffusion region. A. Onstate Resistance When the MOSFET is in the onstate (triode region), the channel of the device behaves like a
constant resistance, RDS(on) , that is linearly proportional to the change between vDS and iD as given by the following relation: RDS(ON ) =
∂vDS ∂iD VGS=Constant
(4.1)
The total conduction (onstate) power loss for a given MOSFET with forward current ID and onresistance RDS(on) is given by, Pon,diss = ID2 RDS(on)
(4.2)
The value of RDS(on) can be signiﬁcant and it varies between tens of milliohms and a few ohms for lowvoltage and highvoltage MOSFETS, respectively. The onstate resistance is an important data sheet parameter, since it determines the forward voltage drop across the device and its total power losses.
50
I. Batarseh GATE
SOURCE
D
Metal SiO2
n+
Body diode
n+
P
P G n− n+ S
(a)
DRAIN
(a)
To cancel the body diode
GATE SOURCE
Fast recovery diode SiO2
D
n+
n+ p
p
n−
G
n+ S
(b)
DRAIN
FIGURE 4.7 (a) Vertical crosssectional view for a power MOSFET and (b) simpliﬁed representation.
Unlike the currentcontrolled bipolar device, which requires base current to allow the current to ﬂow in the collector, the power MOSFET device is a voltagecontrolled unipolar device and requires only a small amount of input (gate) current. As a result, it requires less drive power than the BJT. However, it is a nonlatching current like the BJT i.e. a gate source voltage must be maintained. Moreover, since only majority carriers contribute to the current ﬂow, MOSFETs surpass all other devices in switching speed with switching speeds exceeding a few megahertz. Comparing the BJT and the MOSFET, the BJT has higher power handling capabilities and smaller switching speed, while the MOSFET device has less power handling capabilities and relatively fast switching speed. The MOSFET device has higher onstate resistor than the bipolar transistor. Another difference is that the BJT parameters are more sensitive to junction temperature when compared to the MOSFET, and unlike the BJT, MOSFET devices do not suffer from second breakdown voltages, and sharing current in parallel devices is possible.
(b) FIGURE 4.8 (a) MOSFET Internal body diode and (b) implementation of a fast body diode.
B. Internal Body Diode The modern power MOSFET has an internal diode called a body diode connected between the source and the drain as shown in Fig. 4.8a. This diode provides a reverse direction for the drain current, allowing a bidirectional switch implementation. Even though the MOSFET body diode has adequate current and switching speed ratings, in some power electronic applications that require the use of ultrafast diodes, an external fast recovery diode is added in antiparallel fashion after blocking the body diode by a slow recovery diode as shown in Fig. 4.8b. C. Internal Capacitors Another important parameter that effect the MOSFET’s switching behavior is the parasitic capacitance between the device’s three terminals, namely, gatetosource, Cgs , gatetodrain, Cgd , and draintosource (Cds ) capacitance as shown in Fig. 4.9a. Figure 4.9b shows the physical representation of these capacitors. The values of these capacitances are nonlinear and a function of device structure, geometry, and bias voltages. During turn on, capacitor Cgd and Cgs must be charged through the gate, hence, the design
4
51
The Power MOSFET
In power electronics, the aim is to use powerswitching devices to operate at higher and higher frequencies. Hence, size and weight associated with the output transformer, inductors, and ﬁlter capacitors will decrease. As a result, MOSFETs are used extensively in power supply design that requires high switching frequencies including switching and resonant mode power supplies and brushless dc motor drives. Because of its large conduction losses, its power rating is limited to a few kilowatts. Because of its many advantages over the BJT devices, modern MOSFET devices have received high market acceptance.
Cgd
Cds
Cgs (a) G S
S
4.4.2 MOSFET Regions of Operation
SiO2 n+
n+
Cgs Cds
p
Cgd
n− n+
D (b)
FIGURE 4.9 (a) Equivalent MOSFET representation including junction capacitances and (b) representation of this physical location.
of the gate control circuit must take into consideration the variation in this capacitance (Fig. 4.9b). The largest variation occurs in the gatetodrain capacitance as the draintogate voltage varies. The MOSFET parasitic capacitance are given in terms of the device data sheet parameters Ciss , Coss , and Crss as follows, Cgd = Crss Cgs = Ciss − Crss Cds = Coss − Crss where Crss = smallsignal reverse transfer capacitance. Ciss = smallsignal input capacitance with the drain and source terminals are shorted. Coss = smallsignal output capacitance with the gate and source terminals are shorted. The MOSFET capacitances Cgs , Cgd , and Cds are nonlinear and function of the dc bias voltage. The variations in Coss and Ciss are signiﬁcant as the draintosource and gatetosource voltages cross zero, respectively. The objective of the drive circuit is to charge and discharge the gatetosource and gatetodrain parasitic capacitance to turn on and off the device, respectively.
Most of the MOSFET devices used in power electronics applications are of the nchannel, enhancementtype like that which is shown in Fig. 4.6a. For the MOSFET to carry drain current, a channel between the drain and the source must be created. This occurs when the gatetosource voltage exceeds the device threshold voltage, VTh . For vGS > VTh , the device can be either in the triode region, which is also called “constant resistance” region, or in the saturation region, depending on the value of vDS . For given vGS , with small vDS (vDS < vGS − VTh ), the device operates in the triode region(saturation region in the BJT), and for larger vDS (vDS > vGS − VTh ), the device enters the saturation region (active region in the BJT). For vGS < VTh , the device turns off, with drain current almost equals zero. Under both regions of operation, the gate current is almost zero. This is why the MOSFET is known as a voltagedriven device, and therefore, requires simple gate control circuit. The characteristic curves in Fig. 4.6b show that there are three distinct regions of operation labeled as triode region, saturation region, and cutoffregion. When used as a switching device, only triode and cutoff regions are used, whereas, when it is used as an ampliﬁer, the MOSFET must operate in the saturation region, which corresponds to the active region in the BJT. The device operates in the cutoff region (offstate) when vGS < VTh , resulting in no induced channel. In order to operate the MOSFET in either the triode or saturation region, a channel must ﬁrst be induced. This can be accomplished by applying gatetosource voltage that exceeds VTh , i.e. vGS > VTh Once the channel is induced, the MOSFET can either operate in the triode region (when the channel is continuous with no pinchoff, resulting in the drain current proportioned to the channel resistance) or in the saturation region (the channel pinches off, resulting in constant ID ). The gatetodrain bias voltage (vGD ) determines whether the induced channel enter pinchoff or not. This is subject to the following restriction.
52
I. Batarseh
For triode mode of operation, we have
iD
vGD > VTh vGD < VTh And for the saturation region of operation, Pinchoff occurs when vGD = VTh . In terms of vDS , the above inequalities may be expressed as follows: 1. For triode region of operation vDS < vGS − VTh
and
vGS > VTh
and
vGS > VTh
FIGURE 4.10 Input transfer characteristics for a MOSFET device when operating in the saturation region.
iD
(4.4)
+
+ k(vGS–VTh)2
vGS
(4.5)
iD = K (vGS − VTh )2
−
FIGURE 4.11 Large signal equivalent circuit model.
1 W where, K = µn COX 2 L µn = electron mobility COX = oxide capacitance per unit area L = length of the channel W = width of the channel. Typical values for the above parameters are given in the PSPICE model discussed later. At the boundary between the saturation (active) and triode regions, we have,
iD =
is shown in Fig. 4.11. The drain current is represented by a current source as the function of VTh and vGS . If we assume that once the channel is pinchedoff, the drain– source current will no longer be constant but rather depends on the value of vDS as shown in Fig. 4.12. The increased value of vDS results in reduced channel length, resulting in a phenomenon known as channellength modulation [3, 4]. If the vDS –iD lines are extended as shown in Fig. 4.12, they all intercept the vDS axis at a single point labeled –1/λ, where λ is a positive constant MOSFET parameter. The term (1 + λ vDS ) is added to the iD equation in order to account for the increase in iD due to the channellength modulation, i.e. iD is given by,
(4.8) iD = k(vGS − VTh )2 (1 + λvDS )
Resulting in the following equation for iD , 2 kvDS
S
(4.6)
Saturation Region (4.7)
vDS = vGS − VTh
vDS
−
It can be shown that drain current, iD , can be mathematically approximated as follows: 2 iD = K [2(vGS − VTh )vDS − vDS ] Triode Region
D
G
3. For cutoff region of operation vGS < VTh
vGS
(4.3)
2. For saturation region of operation vDS > vGS − VTh
VTh
(4.9)
The input transfer characteristics curve for iD and vS . vGS is when the device is operating in the saturation region shown in Fig. 4.10. The large signal equivalent circuit model for a nchannel enhancementtype MOSFET operating in the saturation mode
Saturation Region (4.10)
From the deﬁnition of the ro given in Eq. (4.1), it is easy to show the MOSFET output resistance which can be expressed as follows: ro =
1 λk(vGS − VTh )
(4.11)
If we assume the MOSFET is operating under small signal condition, i.e. the variation in vGS on iD vs vGS is in the
4
53
The Power MOSFET
i
D
vGS
Increasing
1 Slope = rO
− 1/ λ
0
vDS
FIGURE 4.12 MOSFET characteristics curve including output resistance.
neighborhood of the dc operating point Q at iD and vGS as shown in Fig. 4.13. As a result, the iD current source can be represented by the product of the slope gm and vGS as shown in Fig. 4.14.
4.4.3 MOSFET Switching Characteristics
D
G +
gmvgs
vGS
rO
−
Since the MOSFET is a majority carrier transport device, it is inherently capable of a high frequency operation [5–8]. But still the MOSFET has two limitations: 1. High input gate capacitances. 2. Transient/delay due to carrier transport through the drift region. As stated earlier the input capacitance consists of two components: the gatetosource and gatetodrain capacitances. The input capacitances can be expressed in terms of the device
S
FIGURE 4.14 Smallsignal equivalent circuit including MOSFET output resistance.
junction capacitances by applying Miller theorem to Fig. 4.15a. Using Miller theorem, the total input capacitance, Cin , seen between the gatetosource is given by, Cin = Cgs + (1 + gm RL )Cgd
iD
(4.12)
Slope = gm Q ID
VTh
VGS
VGS
FIGURE 4.13 Linearized iD vs vGS curve with operating dc point (Q).
The frequency response of the MOSFET circuit is limited by the charging and discharging times of Cin . Miller effect is inherent in any feedback transistor circuit with resistive load that exhibits a feedback capacitance from the input and output. The objective is to reduce the feedback gatetodrain resistance. The output capacitance between the draintosource, Cds , does not affect the turnon and turnoff MOSFET switching characteristics. Figure 4.16 shows how Cgd and Cgs vary under increased drainsource, vDs , voltage.
54
I. Batarseh Cgd G
D + Vgs 
Cgs
gmVgs
rO
S
(a) D
G
+ Vgs Cgs
(1+gmRL)Cgd
gmVgs
rO

S
(b) FIGURE 4.15 (a) Smallsignal model including parasitic capacitances and (b) equivalent circuit using Miller theorem.
Capacitance
The ﬂy back diode D is used to pick up the load current when the switch is off. To simplify the analysis we will assume the load inductance is L0 large enough so that the current through it is constant as shown in Fig. 4.17b.
Cgs
Cgd
Voltage
FIGURE 4.16 Variation of Cgd and Cgs as a function of vDS .
In power electronics applications, the power MOSFETs are operated at high frequencies in order to reduce the size of the magnetic components. In order to reduce the switching losses, the power MOSFETs are maintained in either the onstate (conduction state) or the offstate (forward blocking) state. It is important we understand the internal device behavior; therefore, the parameters that govern the device transition from the onstate and offstates. To investigate the on and off switching characteristics, we consider the simple power electronic circuit shown in Fig. 4.17a under inductive load.
A. Turnon Analysis Let us assume initially the device is off, the load current, I0 , ﬂows through D as shown in the Fig. 4.18a vGG = 0. The voltage vDS = VDD and iG = iD . At t = t0 , the voltage vGG is applied as shown in Fig. 4.19a. The voltage across CGS starts charging through RG . The gate– source voltage, vGS , controls the ﬂow of the draintosource current iD . Let us assume that for t0 ≤ t < t1 , vGS < VTh , i.e. the MOSFET remains in the cutoff region with iD = 0, regardless of vDS . The time interval (t1 ,t0 ) represents the delay turnon time needed to change CGS from zero to VTh . The expression for the time interval t10 = t1 − t0 can be obtained as follows: The gate current is given by, iG =
vGG − vGS RG
= iCGS + iCGD = CGS
dvGS d(vG − vD ) − CGD dt dt
(4.13)
where vG and vD are gatetoground and draintoground voltages, respectively.
4
55
The Power MOSFET
From Eqs. (4.13) and (4.14), we obtain,
+VDD
dvGS VGG − vGS = (CGS + CGD ) RG dt L0
D
(4.15)
Solving Eq. (4.15) for vGS (t) for t > t0 with vGS (t0 ) = 0, we obtain,
iD
vGS (t ) = VGG (1 − e (t −t0 )/τ )
CGD
(4.16)
VDD RG iG vGG
+ 
CGS
IO
CGD
iC
D
GS
RG
+
G
(a) iG
GD
+VDD vGG=0 IO
iC
vDS +
CGS
+ 
D
vGS
S

D
(a)
iD
VDD CG D IO
CGD
RG
D
iG vGG
+ 
iCGS
CG S
D
RG
+
G iG
(b)
vGG=VGG
FIGURE 4.17 (a) Simpliﬁed equivalent circuit used to study turnon and turnoff characteristics of the MOSFET and (b) simpliﬁed equivalent circuit.
+ 
iCGD
vDS +
CGS
vGS
S

(b) Since we have vG = vGS , vD = +VDD , then iG is given by iG = CGS
dvGS dvGS dvGS + CGD = (CGS + CGD ) dt dt dt
(4.14)
FIGURE 4.18 Equivalent modes: (a) MOSFET is in the offstate for t < t0 , vGG = 0, vDS = VDD , iG = 0, iD = 0; (b) MOSFET in the offstate with vGS < VTh for t1 > t > t0 ; (c) vGS > VTh , iD < I0 for t1 < t < t2 ; (d) vGS > VTh , iD = I0 for t2 ≤ t < t3 ; and (e) VGS > VTh , iD = Io for t3 ≤ t < t4 .
56
I. Batarseh
where,
VDD
τ = RG (CGS + CGD ) IO
D
The gate current, iG , is given by, iD RG i G
iG =
CGD
As long as vGS < VTh , iD remains zero. At t = t1 , vGS reaches VTh causing the MOSFET to start conducting. Waveforms for iG and vGS are shown in Fig. 4.19. The time interval (t1 −t0 ) is given by,
(c)
+VDD
t10
IO
iGD iG
RG
G
iD ≈ IO
CDS
CGS
+ 
iGS=0
√ (∂iD /∂vGS ) 2 IDSS ID gm = = ID VTh
iD (t ) = gm (vGS − VTh )
IO iD D iG=0 G
VDS = IorDS (ON)
rON
+ 
(4.19)
As long as iD (t) < I0 , D remains on and vDS = VDD as shown in Fig. 4.18c. The equation for vGS (t) remains the same as in Eq. (4.16), hence, Eq. (4.19) results in iD (t) given by,
+VD
RG
(4.18)
The drain current can be approximately given as follows:
(d)
VGG
VTh = t1 − t0 = −τ ln 1 − VGG
t10 represents the ﬁrst delay interval in the turnon process. For t > t1 with vGS > VTh , the device starts conducting and its drain current is given as a function of vGS and VTh . In fact iD starts ﬂowing exponentially from zero as shown in Fig. 4.19d. Assume the input transfer characteristics for the MOSFET is limited as shown in Fig. 4.20 with slope of gm that is given by
D
CGD
VGG
(4.17)
VGG −(t −t0 )/τ iG = e RG
iDS = f(VDS,vGS) = gm(vDS – VTh) CGS
vGG + 
vGG − vGS RG
iD (t ) = gm (VGG − VTh ) − gm VGG e −(t −t1 )/τ
(4.20)
The gate current continues to decrease exponentially as shown in Fig. 4.19c. At t = t2 , iD reaches its maximum value of I0 , turning D off. The time interval t21 = (t2 − t1 ) is obtained from Eq. (4.20) by setting iD (t2 ) = I0 . t21 = τln
gm VGG gm (VGG − VTh ) − I0
(4.21)
S
For t > t2 , the diode turns off and iD ≈ I0 as shown in Fig. 4.18d. Since the drain current is nearly a constant, then
(e)
FIGURE 4.18 continued
4
57
The Power MOSFET
vGG
(a)
vGG
t0 vGG vGS
(b) VTh
t0
t1
t2
t
t3
iG
(c)
–
VGG–VTh RG iD iO
(d)
vDS VDD
(e) IOrDS(ON) t0
t1
t2
FIGURE 4.19 Turnon waveform switiching.
t3
t
time
58
I. Batarseh
Solving for vDS (t) for t > t2 , with vDS (t2 ) = VDD , we obtain
iD dc operating point
vDS (t ) = −
ID
Slope=gm
Q
ideal VTh
VGS
vGS
FIGURE 4.20 Input transfer characteristics.
VGG − VTh (t − t2 ) + VDD For t > t2 RG CGD
(4.25)
This is a linear discharge of CGD as shown in Fig. 4.19e The time interval t32 = (t3 −t2 ) is determined by assuming that at t = t3 , the draintosource voltage reaches its minimum value determined by its on resistance, vDS (ON ) i.e. vDS(ON ) is given by, vDS(ON ) ≈ I0 rDS(ON )
the gate–source voltage is also constant according to the input transfer characteristic of the MOSFET, i.e. iD = gm (vGS − VTh ) ≈ I0
(4.22)
For t > t3 , the gate current continues to charge CGD and since vDS is constant, vGS starts charging at the same rate as in interval t0 ≤ t < t1 , i.e.
(4.23)
vGS (t ) = VGG (1 − e −(t −t3 )/τ )
Hence, I0 + VTh gm
vGS (t ) = At t = t2 , iG (t) is given by, iG (t2 ) =
VGG − vGS (t2 ) VGG − (I0 /gm ) − VTh = VTh VTh
= constant
(4.24)
Since the time constant τ is very small, it is safe to assume vGS (t2 ) reaches its maximum, i.e. vGS (t2 ) ≈ VGG and
The gate voltage keeps increasing exponentially until t = t3 when it reaches VGG , at which iG = 0 and the device fully turns on as shown in Fig. 4.18e. The equivalent circuit model when the MOSFET is completely turned on is for t > t1 . At this time, the capacitors CGS and CGD are charged with VGG and (I0 rds(ON )−VGG ), respectively. The time interval t32 = (t3 − t2 ) is obtained by evaluating vDS at t = t3 as follows vDS (t3 ) = −
iG (t2 ) ≈ 0 For t2 ≤ t < t3 , the diode turns off the load current I0 (drain current iD ), which starts discharging the draintosource capacitance. Since vGS is constant, the entire gate current ﬂows through CGD , resulting in the following relation, iG (t ) = iCGD = CGD
d(vG − vD ) dt
Since vG is constant and vs = 0, we have iG (t ) = −CGD =−
dvDS dt
VGG − VTh RG
VGG − VTh (t3 − t2 ) + VDD RG CGD
(4.26)
= I0 rDS(ON ) Hence, t32 = (t3 −t2 ) is given by, t32 = t3 − t2 = RG CGD
VDD − ID rDS(ON ) VGG − VTh
(4.27)
The total delay in turning on the MOSFET is given by tON = t10 + t21 + t32
(4.28)
Notice the MOSFET sustains high voltage and current simultaneously during intervals t21 and t32 . This results in large power dissipation during turn on, that contributes to the overall switching losses. The smaller the RG , the smaller t21 and t32 become.
4
59
The Power MOSFET
B. Turnoff Characteristics To study the turnoff characteristic of the MOSFET, we will consider Fig. 4.17b again by assuming the MOSFET is ON and in steady state at t > t0 with the equivalent circuit of Fig. 4.18e. Therefore, at t = t0 we have the following initial conditions. vDS (t0 ) = ID rDS(ON ) vGS (t0 ) = VGG (4.29)
iG (t0 ) = 0 vCGS (t0 ) = VGG
At t = t0 , the gate voltage, vGG (t) is reduced to zero as shown in Fig. 4.21a. The equivalent circuit at t > t0 is shown in Fig. 4.22a. If we assume the draintosource voltage remains constant, CGS and CGD are discharging through RG as governed by the following relations
d(vGS − vDS ) dvDS dvGD = CGD = −CGD dt dt dt
vGS (t1 ) I0 1 = = + VTh RG RG gm
vGS (t1 ) 1 iG = = RG RG
I0 + VTh gm
Integrating both sides of the above equation from t1 to t with vDS (t1 ) = − vDS(ON ) , we obtain,
I0 + VTh (t − t1 ) gm
(4.34)
hence, vDS charges linearly until it reaches VDD . At t = t2 , the draintosource voltage becomes equal to VDD , forcing D to turn on as shown in Fig. 4.22c. The draintosource current is obtained from the transfer characteristics and given by
dvGS dvGD + CGD = CGS dt dt Since vDS is assumed constant, then iG becomes, −vGS RG
iDS (t ) = gm (vGS − VTh ) dvGS dt
(4.30)
where vGS (t) is obtained from the following equation iG = −
Hence, evaluating for vGS for t ≥ t0 , we obtain vGS (t ) = vGS (t0 )e −(t −t0 )/τ
(4.31)
vGS dvGS = (CGS + CGD ) RG dt
vGS (t0 ) = vGG τ = (CGS + CGD )RG
vGS (t ) =
As vGS continues to decrease exponentially, drawing current from CGD will reach a constant value at which drain current is ﬁxed, i.e. ID = I0 . From the input transfer characteristics, the value of vGS when ID = I0 is given by, I0 + VTh gm
(4.32)
The time interval t10 = t1 − t0 can be obtained easily by setting Eq. (4.31) to (4.32) at t = t1 .
(4.35)
Integrate both sides from t2 to t with v GS (t2 ) = (I0 /gm ) + VTh , we obtain the following expression for vGS (t),
where,
vGS =
(4.33)
Since, for t2 −t1 , the gatetosource voltage is constant and equals vGS (t1 ) = (I0 /gm ) + VTh as shown in Fig. 4.21b, then the entire gate current is being drawn from CGD , hence,
1 vDS (t ) = vDS(ON ) + RG CGD
−vG = iCGS + iCGD RG
= (CGS + CGD )
VGG − e −(t −t0 )/τ RG
Assuming iG constant at its initial value at t = t1 , i.e.
vCGD (t0 ) = VGG − I0 rDS(ON )
iG =
iG = −
iG = CGD
iDS (t0 ) = I0
iG =
The gate current during the t2 ≤ t < t1 is given by
I0 + VTh e −(t −t2 )/τ gm
(4.36)
Hence the gate current and draintosource current are given by, iG (t ) =
−1 RG
I0 + VTh e −(t −t2 )/τ gm
iDS (t ) = gm VTh (e −(t −t2 )/τ − 1) + I0 e −(t −t2 )/τ
(4.37) (4.38)
The time interval between t2 ≤ t < t3 is obtained by evaluating vGS (t3 ) = VTh , at which the drain current becomes
60
I. Batarseh vGG
(a) t t0 vGS VGG
(b) VTh
t
iG
(c)
0
t
iD IO
(d) t vDS
(e) VDD
VDS(ON) t0
t1
t2
t3
t4
t
FIGURE 4.21 Turnoff switching waveforms.
approximately zero and the MOSFET turn off hence,
For t > t3 , the gate voltage continues to decrease exponentially to zero, at which the gate current becomes zero and CGD charges to −VDD . Between t3 and t4 , ID discharges to zero as shown in the equivalent circuit Fig. 4.22d. The total turnoff time for the MOSFET is given by,
vGS (t3 ) = VTh
I0 = + VTh e −(t3 −t2 )/τ gm
toff = t10 + t21 + t32 + t43
Solving for t32 = t3 − t2 we obtain,
t32
I0 = t3 − t2 = τ ln 1 + VTh gm
≈ t21 + t32 (4.39)
(4.40)
The time intervals that most effect the power dissipation are t21 and t32 . It is clear that in order to reduce
4
61
The Power MOSFET +VD D VDD
IO IO
D
D
+
G RDS(ON)
iG
RG
iD
VDS=VDD
RG
VGG=0
S

VGG=0
+ VGS −
(a)
(c)
+VDD
VDD IO iO
iD=iO
iC =iG GD + VDD + iG
iD ≈ IO
VDS
iG= 0
RG VGG=0
RG
iCGS=0 VGG=0 IO + VGS = gm + VTh 
(b)
(d)
FIGURE 4.22 Equivalent circuits: (a) t0 ≤ t < t1 ; (b) t1 ≤ t < t2 ; (c) t2 ≤ t < t3 ; and (d) t3 ≤ t < t4 .
the MOSFET ton and toff times, the gate–drain capacitance must be reduced. Readers are encouraged to see the reference by Baliga for detailed discussion on the turnon and turnoff characteristics of the MOSFET and to explore various fabrication methods.
C. Safe Operation Area The safe operation area (SOA) of a device provides the current and voltage limits. The device must handle to avoid destructive failure. Typical SOA for a MOSFET device is shown in Fig. 4.23. The maximum current limit while the device is on is determined by the maximum
62
I. Batarseh iD Icmax Current limit
Max power (Pcmax)
rDS(ON) Second breakdown limit
SOA
Voltage limit vCE,max Temperature
vDS
FIGURE 4.25 The onstate resistance as a fraction of temperature.
FIGURE 4.23 Safe operation area for MOSFET.
power dissipation Pdiss,ON = IDS(ON ) RDS(ON ) As the drain–source voltage starts increasing, the device starts leaving the onstate and enters the saturation (linear) region. During the transition time, the device exhibits large voltage and current simultaneously. At higher drain–source voltage values that approach the avalanche breakdown it is observed that power MOSFET suffers from second breakdown phenomenon. The second breakdown occurs when the MOSFET is in the blocking state (off) and a further increase in vDS will cause a sudden drop in the blocking voltage. The source of this phenomenon in MOSFET is caused by the presence of a parasitic ntype bipolar transistor as shown in Fig. 4.24. The inherent presence of the body diode in the MOSFET structure makes the device attractive to application in which bidirectional current ﬂow is needed in the power switches.
Drain
npn BJT Gate
Source
FIGURE 4.24 MOSFET equivalent circuit including the parasitic BJT.
Today’s commercial MOSFET devices have excellent high operating temperatures. The effect of temperature is more prominent on the onstate resistance as shown in Fig. 4.25. As the onstate resistance increases, the conduction losses also increase. This large vDS(ON ) limits the use of the MOSFET in high voltage applications. The use of silicon carbide instead of silicon has reduced vDS(ON ) by many folds. As the device technology keeps improving in terms of improving switch speeds, increased power handling capabilities, it is expected that the MOSFET will continue to replace BJTs in all types of power electronics systems.
4.4.4 MOSFET PSPICE Model The PSPICE simulation package has been used widely by electrical engineers as an essential software tool for circuit design. With the increasing number of devices available in the market place, PSPICE allows for the accurate extraction and understanding of various device parameters and their variation effect on the overall design prior to their fabrication. Today’s PSPICE library is rich with numerous commercial MOSFET models. This section will give a brief overview of how the MOSFET model is implemented in PSPICE. A brief overview of the PSPICE modeling of the MOSFET device will be given here.
A. PSPICE Static Model There are four different types of MOSFET models that are also known as levels. The simplest MOSFET model is called LEVEL1 model and is shown in Fig. 4.26 [9, 10]. LEVEL2 model uses the same parameters as LEVEL1, but it provides a better model for Ids by computing the model coefﬁcients KP, VTO, LAMBDA, PHI, and GAMMA directly from the geometrical, physical, and technological parameters [10]. LEVEL3 is used to model the shortchannel devices and LEVEL4 represents the Berkeley Shortchannel IGFET model (BSIMmodel).
4
63
The Power MOSFET Drain iD rD iBD
VGD

+ RG
Gate iG
+
VBD
+ Bulk(substrate)
iDS
VDS

iB


VGS
VBS
+
iBS
RS IS Source
FIGURE 4.26 PSPICE LEVEL1 MOSFET static model.
The triode region, vGS > VTh and vDS < vGS and vDS < vGS – VTh the drain current is given by, iD =
vDS W KP vDS (1 + λvDS ) vGS − VTh − 2 2 L − 2Xjl (4.41)
In the saturation (linear) region, where vGS > VTh and vDS > vGS − VTh , the drain current is given by ID =
KP W (VGS − VTh )2 (1 + λVDS ) 2 L − 2Xjl
(4.42)
where KP is the transconductance and Xjl is the lateral diffusion. The threshold voltage, VTh , is given by, VTh = VT 0 + ∂
2φp − VBS − 2φp
(4.43)
where, VT 0 = Zerobias threshold voltage. δ = Bodyeffect parameter. φp = Surface inversion potential. Typically, Xij L and λ ≈ 0. The term (1 + λVDS ) is included in the model as empirical connection to model the effect of the output conductance when the MOSFET is operating in triode region. λ is known as the channellength modulation parameter.
When the bulk and source terminals are connected together, i.e. VBS = 0, the device threshold voltage equals the zerobias threshold voltage, i.e. VTh = VT 0 VT 0 is positive for the nchannel enhancementmode devices and negative for the nchannel depletionmode devices. The parameters KP , VT 0 , δ, φ are electrical parameters that can be either speciﬁed directly in the MODEL statement under the Pspice keywords KP, VTO, GAMMA, and PHI, respectively, as shown in Table 4.1. They also can be calculated when the geometrical and physical parameters are known. The twosubstrate currents that ﬂow from the bulk to the source, IBS and from the bulk to the drain, IBD are simply diode currents, which are given by, IBS = ISS e −(VBS /VT ) − 1
(4.44)
IBD = IDS e −(VBD /VT ) − 1
(4.45)
where ISS and IDS are the substrate source and substrate drain saturation currents. These currents are considered equal and given as IS in the MODEL statement with a default value of 10−14 A. Where the equation symbols and their corresponding PSPICE parameter names are shown in Table 4.1. In PSPICE, a MOSFET device is described by two statements: the ﬁrst statement start with the letter M and the
64 TABLE 4.1 Symbol
I. Batarseh PSPICE MOSFET parameters Name
Description
Default
Units
Level LEVEL VTO VTO λ LAMDA γ GAMMA
ρ PHI η ETA κ KAPPA µ0 UO Is IS Js JS JSSW JSSW N N PB PB PBSW PBSW RD RD RS RS RG RG RB RB Rds RDS Rsh RSH (b) Device process and dimensional parameters
Model type (1, 2, 3, or 4) Zerobias threshold voltage ∗ Channellength modulation 1,2 Bodyeffect (bulk) threshold parameter Surface inversion potential Static feedback3 Saturation ﬁeld factor3 Surface mobility Bulk saturation current Bulk saturation current/area Bulk saturation current/length Bulk emission coefﬁcient n Bulk junction voltage Bulk sidewall diffusion voltage Drain resistance Source resistance Gate resistance Bulk resistance Drain–source shunt resistance Drain and source diffusion sheet resistance
1 0 0 0 0.6 0 0.2 600 10−14 0 0 1 0.8 PB 0 0 0 0 α 0
– V v−1 v−1/2 V – – cm2 /V·s A A/m2 A/m – V V /m2
Nsub W L WD Xjl Kp tOX NSS NFS NA TPG
Substrate doping density Channel width Channel length Lateral Diffusion width Lateral Diffusion length Transconductance coefﬁcient Oxide thickness Surfacestate density Fast surfacestate density Substrate doping Gate material +1 Opposite of substrate −1 Same as substrate 0 Aluminum Metallurgical junction depth2,3 Surface mobility Mobility degradation critical ﬁeld2 Mobility degradation exponent2 Maximum drift velocity of carriers2 Channel charge coefﬁcient2 Width effect on threshold2,3 Mobility modulation3
None DEFW DEFL 0 0 20 µ 10−7 None 0 0 1 – – – 0 600 104 0 0 1 0 0
cm−3 m m m m A/v2 m cm−2 cm−2 cm−3 – – – – m cm2 /V·s V/cm – m/s – – –
Bulkdrain zerobias capacitance Bulksource zerobias capacitance Bulk zerobias bottom capacitance Bulk zerobias perimeter capacitance/length Bulk bottom grading coefﬁcient Bulk sidewall grading coefﬁcient Bulk forwardbias capacitance coefﬁcient Gate–source overlap capacitance/channel width Gate–drain overlap capacitance/channel width Gatebulk overlap capacitance/channel length Fraction of channel charge that associates with drain1,2 Flicker noise coefﬁcient Flicker noise exponent
0 0 0 0 0.5 0.33 0.5 0 0 0 0 0 0
F F F/m2 F/m – – – F/m F/m F/m – – –
(a) Device dc and parasitic parameters
NSUB W L WD LD KP TOX NSS NFS NSUB TPG
Xj XJ UO µ0 Uc UCRIT Ue UEXP Ut VMAX Neff NEFF δ DELTA θ THETA (c) Device capacitance parameters CBD CBS Cj Cjsw Mj Mjsw FC CGSO CGDO CGBO XQC KF αF
CBD CBS CJ CJSW MJ MJSW FC CGSO CGDO CGBO XQC KF AF
∗ These numbers indicate that this parameter is available in this level number, otherwise it is available in all levels.
4
65
The Power MOSFET
second statement starts with .Model that deﬁnes the model used in the ﬁrst statement. The following syntax is used: M<device_name> <Source_node_number><Substrate_node number> <Model_name> * [<param_1>=<param_2>= . . ..] .MODEL <Model_name> [(<param_1>= <param_2>= . . ...]
where the starting letter “M” in M<device_name> statement indicates that the device is a MOSFET and <device_name>is a user speciﬁed label for the given device, the <Model_name> is one of the hundreds of device models speciﬁed in the PSPICE library, <Model_name> the same name speciﬁed in the device name statement, is either NMOS of PMOS, depending on whether the device is nchannel or pchannel MOS, respectively, that follows by optional list of parameter types and their values. The length L and the width W and other parameters can be speciﬁed in the M<device_name>, in the .MODEL or .OPTION statements. User may select not to include any value, and PSPICE will use the speciﬁed default values in the model. For normal operation (physical construction of the MOS devices), the source and bulk substrate nodes must be connected together. In all the PSPICE library ﬁles, a default parameter values for L, W, AS, AD, PS, PD, NRD, and NDS are included, hence, user should not specify such values in the device “M” statement or in the OPTION statement. The power MOSFET device PSPICE models include relatively complete static and dynamic device characteristics given in the manufacturing data sheet. In general, the following effects are speciﬁed in a given PSPICE model: dc transfer curves, onresistance, switching delays, and gate drive characteristics and reversemode “bodydiode” operation. The device characteristics that are not included in the model are noise, latchups, maximum voltage, and power ratings. Please see OrCAD Library Files. EXAMPLE 4.3 Let us consider an example of using IRF MOSFET that was connected as shown in Fig. 4.27. It was decided that the device should have a blocking voltage (VDSS ) of 600 V and drain current, id , of 3.6 A. The device selected is IRF CC30 with case TO220. This device is listed in PSPICE library under model number IRFBC30 as follows: ∗ Library of Power MOSFET Models ∗ Copyright OrCAD, Inc. 1998 All Rights Reserved. ∗
L
D 4 3
S1 5
0
FIGURE 4.27 Example of a power electronic circuit that uses a power MOSFET.
The PSPICE code for the MOS device labeled S1 used in Fig. 4.27 is given by, MS1 3 5 0 0 IRFBC30 .MODEL IRFBC30 .Model IRFBC30 NMOS(Level=3 Gamma=0 Delta=0 Eta=0 Theta=0 Kappa=0.2 Vmax=0 Xj=0 + Tox=100n Uo=600 Phi=.6 Rs=5.002m Kp=20.43u W=.35 L=2u Vto=3.625 + Rd=1.851 Rds=2.667MEG Cbd=790.1p Pb=.8 Mj=.5 Fc=.5 Cgso=1.64n + Cgdo=123.9p Rg=1.052 Is=720.2p N=1 Tt=685) ∗ Int’l Rectifier pid=IRFCC30 case=TO220
4.4.5 MOSFET Largesignal Model The equivalent circuit of Fig. 4.28 includes ﬁve device parasitic capacitances. The capacitors CGB , CGS , CGD , represent the chargestorage effect between the gate terminal and the bulk, source, and drain terminals, respectively. These are nonlinear twoterminal capacitors expressed as function of W, L, Cox , VGS , VT 0 , VDS , and CGBO , CGSO , CGDO , where the capacitors CGBO , CGSO , CGDO are outside the channel region, known as overlap capacitances, that exist between the gate electrode and the other three terminals, respectively. Table 4.1 shows the list of PSPICE MOSFET capacitance parameters and their default values. Notice that the PSPICE overlap capacitors keywords (CGBO , CGSO , CGDO ) are proportional either to the MOSFET width or length of the channel as follows:
∗ $Revision: 1.24 $ ∗ $Author: Rperez $
CGBO =
CGBO L
∗ $Date: 19 October 1998 10:22:26 $ ∗
CGSO =
CGSO W
CGDO =
CGDO W
. Model IRFBC30 NMOS NMOS
(4.46)
66
I. Batarseh d iD
Drain iD
Cgd
Cgd
iBD
+ VGD Gate iG
iB
+gmbVbs'
iG
+ +
VGS

VGS' 
S' RS
CBS
rS
go
ib  VBS' +
Cgs
 VBS + iBS

Cgs
gmVgs' Bulk(Substrate)
VDS
iDS
gBD
d'
VBD +
+
CBD
RD
CBD
rD
gBS CBS
Cgb
Cgb iS iS
FIGURE 4.29 Smallsignal equivalent circuit model for MOSFET.
Source
FIGURE 4.28 Largesignal model for the nchannel MOSFET.
In the triode region, vGS > vDS −VTh , the terminal capacitors are given by, 2
vGS − vDS − VTh + CGSO CGS = LW COX 1 − 2(vGS − VTh ) − VDS
2 vGS − VTh + CGDO CGD = LW COX 1 − 2(vGS − VTh ) − vDS CGB = CGBO L
(4.47)
2 CGS = LW COX + CGSO 3
4.4.6 Current MOSFET Performance (4.48)
CGD = CGD0 where COX is the perunitarea oxide capacitance given by, COX =
EXAMPLE 4.4 Figure 4.30a shows an example of a softswitching power factor connection circuit that has two MOSFETs. Its PSPICE simulation waveforms are shown in Fig. 4.30b. Table 4.2 shows the PSPICE code for Fig. 4.30a.
In the saturation (linear) region, we have
CGB = CGB0 L
by CBD and CBS across the two diodes. Because for almost all power MOSFETs, the bulk and source terminals are connected together and at zero potential, diodes DBD and DBS don’t have forward bias, resulting in very small conductance values, i.e. small diffusion capacitances. The smallsignal model for MOSFET devices is given in Fig. 4.29.
KOX E0 TOX
KOX = Oxide’s relative dielectric constant. E0 = Free space dielectric constant equals 8.854×10−12 F/m. TOX = Oxide’s thickness layer given as TOX in Table 4.1. Finally, the diffusion and junction region capacitances between the bulktochannel (drain and source) are modeled
The current focus of MOSFET technology development is much more broad than power handling capacity and switching speed; the size, packaging, and cooling of modern MOSFET technology is a major focus. Of course, the development of higher power and efﬁciency is still paramount, but as modern electronics have become increasingly smaller, the packaging and cooling of power circuits has become more important. It has been indicated by manufacturers that many of their modern MOSFETs are not limited by their semiconductor, but by the packaging. If the MOSFET cannot properly disperse heat, the device will become overheated, which will lead to failure. An example of modern MOSFET technology is the DirectFET surface mounted MOSFET manufactured by International Rectiﬁer. Part number IRF6662, for example, can handle 47 A at 100 V, while consuming a board space of
4
67
The Power MOSFET
Dao
Di out Do Lap
Li
Cp2
Lp1
{n1}
Co
{n1}
17.6u
Ro
Ls
60uF {n*16}
47u
25
Las
M2 N00105
N00245
Lak
{0.4*n1}
Dp
0 PARAMETERS:
5u
Vs IRF840
TS = 2us D = 0.3 DELTA = 0.1
0
M1 N00109
110
10p
N000911
Lp2 Cp1
Va
Vin
IRFBC30
0
{n}
47u
K K1 k_linear COUPLING = 0.995
PARAMETERS:
Lp1 Lp2
N = 1mH N1 = 400u
Ls
K K2 k_linear COUPLING = 1.0 0
Lap Las
(a) 10U
0U U(Ua;+)
U(Us;+)
1.0A
U(Ua;+) SEL>> 1.0A I(Lak) 10U
10U U(Cs : 1)/50 4.0A
4.0A 27.7us I(Li)
29.0us
30.0us
31.0us
32.0us
33.0us
33.8us
Time
(b) FIGURE 4.30 (a) Example of power electronic circuit and (b) PSPICE simulation waveforms.
5 × 6 mm, and being only 0.6 mm thick. This switch is efﬁcient at frequencies greater than 1 MHz, and the packaging can dissipate over 50% more heat than traditional surface mounted MOSFETs of similar power ratings. The power density of this switch is many times the power density of similarly rated devices made by International Rectiﬁer in the past. One major factor in the performance gain of this product line is dualsided cooling. By designing the package to mount to the
board through a large contact patch, and by using materials with high heat conductivity, the switch has a very high surface area vs volume ratio, which allows for the heat to be dissipated through the top heat sink as well as through the circuit board. Another example of manufacturers that are focusing on packaging and cooling to increase the performance of their products is Vishay’s PolarPAK and PowerPAK. These devices have a 65% smaller board surface area than traditional SO8 packages. Also, the thermal conductivity of the package is 88%
68 TABLE 4.2
I. Batarseh PSPICE MOSFET capacitance parameters and their default values for Fig. 4.30a
* source ZVTZCS D_Do V_Vs L_Ls Kn_K1 C_Co V_Vin L_Li V_Va {Ts} D_Dp C_C7 R_Ro C_C8 D_Dao D_Di L_Lp2 C_C9 L_Las Kn_K2 L_Lp1 L_Lap C_Cp2 C_Cp1 L_Lak M_M1 M_M2 .PARAM D=0.3 DELTA=0.1
N00111 OUT Dbreak N00105 0 DC 0 AC 0 PULSE 0 N00111 {n*.16} L_Lp1 L_Lp2 L_Ls 0.995 OUT 0 60uF IC=50 N00103 0 110 N00103 N00099 17.6u IC=0 N00109 0 DC 0 AC 0 PULSE
N1=400u
0
9
0
0
0
{D*Ts}
0
9
{Delta*Ts/1.1}
{Ts}
0
0
{2.0*Delta*Ts}
N00121 N00169 Dbreak N00111 OUT 30p OUT 0 25 N00143 OUT 10p N00143 OUT Dbreak N00099 N00245 Dbreak N00121 0 {n} IC=0 N00169 N00121 10p N00143 0 {0.4*n1} L_Lap L_Las 1.0 N00245 N00169 {n} IC=0 N00245 N000791 {n1} N00245 N00121 47u IC=170 N00169 0 47u IC=170 N000791 N000911 5u IC=0 N000911 N00109 0 0 IRFBC30 N00245 N00105 0 0 IRF840 N=1mH TS=2us
**** MOSFET MODEL PARAMETERS **************************************************** IRFBC30 IRF840 NMOS NMOS LEVEL 3 3 L 2.000000E06 2.000000E06 W .35 .68 VTO 3.625 3.879 KP 20.430000E06 20.850000E06 GAMMA 0 0 PHI .6 .6 LAMBDA 0 0 RD 1.851 .6703 RS 5.002000E03 6.382000E03 RG 1.052 .6038 RDS 2.667000E+06 2.222000E+06 IS 720.200000E12 56.030000E12 JS 0 0 PB .8 .8 PBSW .8 .8 CBD 790.100000E12 1.415000E09 CJ 0 0 CJSW 0 0 TT 685.000000E09 710.000000E09 CGSO 1.640000E09 1.625000E09 CGDO 123.900000E12 133.400000E12 CGBO 0 0 TOX 100.000000E09 100.000000E09 XJ 0 0 UCRIT 10.000000E+03 10.000000E+03 DELTA 0 0 ETA 0 0 DIOMOD 1 1 VFB 0 0 LETA 0 0 WETA 0 0 U0 0 0 TEMP 0 0 VDD 0 0 XPART 0 0
greater than traditional devices. The PolarPAK device increases the performance by cooling the part from the top and the bottom of the package. These advances in packaging and cooling have allowed the devices to have power densities greater than 250 W/mm3 as well, while maintaining high efﬁciencies into the megahertz. Another important characteristic of any solidstate device is the expected service life. For MOSFETs, manufacturers have indicated that the mean time before failure (MTBF) approximately decreases by 50% for every 10◦ C that the operational temperature increases. For this reason, the current Examples of modern MOSFETs Device type
Rated voltage
Rated current
Frequency limit
Rated power
Footprint mm2
High voltage High voltage High power High current High efﬁciency High efﬁciency High efﬁciency High freq. – low power
1000 V 600 V 100 V 40 V 30 V 30 V 100 V
6.1 A 40 A 180 A 280 A 40 A 60 A 47 A
1 MHz 1 MHz 500 kHz 1 MHz 2 MHz 2 MHz 2 MHz
6 kW 24 kW 18 kW 11 kW 1.2 kW 1.8 kW 4.7 kW
310 320 310 310 31.5 36 30.9
10 V
0.7 A
200 MHz
7W
21
advancement in cooling and packaging has a direct effect on the longevity of the components. While there are deﬁnite increases in device longevity every year, the easiest way to have a large impact on the life of the device is to keep the temperature down.
4
69
The Power MOSFET
As development continues, MOSFETs will become smaller, more efﬁcient, higher power density, and higher frequency of operation. As such, MOSFETs will continue to expand into applications that typically use other forms of power switches.
4.5 Future Trends in Power Devices As stated earlier, depending on the applications, the power range processed in power electronic range is very wide, from hundreds of milliwatts to hundreds of megawatts, therefore, it is very difﬁcult to ﬁnd a single switching device type to cover all power electronic applications. Today’s available power devices have tremendous power and frequency rating range as well as diversity. Their forward current ratings range from a few amperes to a few kiloamperes, blocking voltage rating ranges from a few volts to a few of kilovolts, and switching frequency ranges from a few hundred of hertz to a few megahertz as illustrated in Table 4.3. This table illustrates the relative comparison between available power semiconductor devices. We only give relative comparison because there is no straightforward technique that gives ranking of these devices. As we accumulate this table, devices are still being developed very rapidly with higher current, voltage ratings, and switching frequency. TABLE 4.3
Comparison of power semiconductor devices
Device type
Year made available
Rated Rated Rated voltage current frequency
Rated power
Forward voltage
Thyristor (SCR) Triac GTO BJT (Darlington) MOSFET IGBT SIT SITH MCT
1957 1958 1962 1960s
6 kV 1 kV 4.5 kV 1.2 kV
3.5 kA 100 A 3 kA 800 A
500 Hz 500 Hz 2 kHz 10 kHz
100’s MW 100’s kW 10’s MW 1 MW
1.5–2.5 V 1.5–2 V 3–4 V 1.5–3 V
1976 1983
500 V 1.2 kV 1.2 kV 1.5 kV 3 kV
50 A 400 A 300 A 300 A 2 kV
1 MHz 20 kHz 100 kHz 10 kHz 20– 100 kHz
100 kW 100’skW 10’s kW 10’s kW 10’s MW
3–4 V 3–4 V 10–20 V 2–4 V 1–2 V
1988
It is expected that improvement in power handling capabilities and increasing frequency of operation of power devices will continue to drive the research and development in semiconductor technology. From power MOSFET to power MOSIGBT and to power MOScontrolled thyristors, power rating has consistently increased by a factor of 5 from one type to another. Major research activities will focus on obtaining new device structure based on MOSBJT technology integration to rapidly increase power ratings. It is expected that the power MOSBJT technology will capture more than 90% of the total power transistor market. The continuing development of power semiconductor technology has resulted in power systems with driver circuit, logic and control, device protection, and switching devices being designed and fabricated on a singlechip. Such power IC modules are called “smart power” devices. For example, some of today’s power supplies are available as IC’s for use in lowpower applications. No doubt the development of smart power devices will continue in the near future, addressing more power electronic applications.
References 1. B. Jayant Baliga , Power Semiconductor Devices, 1996. 2. L. Lorenz, M. Marz, and H. Amann, “Rugged Power MOSFET A milestone on the road to a simpliﬁed circuit engineering,” SIEMENS application notes on SFET application, 1998. 3. M. Rashid, Microelectronics, ThomsonEngineering, 1998. 4. Sedra and Smith, Microelectronic Circuits, 4th Edition, Oxford Series, 1996. 5. Ned Mohan, Underland, and Robbins, Power Electronics: Converters, Applications and Design, 2nd Edition. John Wiley. 1995. 6. R. Cobbold, Theory and Applications of Field Effect Transistor, John Wiley, 1970. 7. R.M. Warner and B.L. Grung, MOSFET: Theory and Design, Oxford, 1999. 8. Power FET’s and Their Application, PrenticeHall, 1982. 9. J. G. Gottling, Hands on pspice, Houghton Mifﬂin Company, 1995. 10. G. Massobrio and P. Antognetti, Semiconductor Device Modeling with PSPICE, McGrawHill, 1993.
5 Insulated Gate Bipolar Transistor S. Abedinpour, Ph.D. and K. Shenai, Ph.D. Department of Electrical Engineering and Computer Science, University of Illinois at Chicago, 851, South Morgan Street (M/C 154), Chicago, Illinois, USA
5.1 5.2 5.3 5.4
Introduction .......................................................................................... Basic Structure and Operation................................................................... Static Characteristics ............................................................................... Dynamic Switching Characteristics.............................................................
71 72 74 76
5.4.1 Turnon Characteristics • 5.4.2 Turnoff Characteristics • 5.4.3 Latchup of Parasitic Thyristor
5.5 IGBT Performance Parameters .................................................................. 78 5.6 Gate Drive Requirements ......................................................................... 80 5.6.1 Conventional Gate Drives • 5.6.2 New Gate Drive Circuits • 5.6.3 Protection
5.7 Circuit Models ....................................................................................... 82 5.7.1 Input and Output Characteristics • 5.7.2 Implementing the IGBT Model into a Circuit Simulator
5.8 Applications........................................................................................... 85 Further Reading ..................................................................................... 87
5.1 Introduction The insulated gate bipolar transistor (IGBT), which was introduced in early 1980s, is becoming a successful device because of its superior characteristics. IGBT is a threeterminal power semiconductor switch used to control the electrical energy. Many new applications would not be economically feasible without IGBTs. Prior to the advent of IGBT, power bipolar junction transistors (BJT) and power metal oxide ﬁeld effect transistors (MOSFET) were widely used in low to medium power and highfrequency applications, where the speed of gate turnoff thyristors was not adequate. Power BJTs have good onstate characteristics but have long switching times especially at turnoff. They are currentcontrolled devices with small current gain because of highlevel injection effects and wide base width required to prevent reachthrough breakdown for high blocking voltage capability. Therefore, they require complex base drive circuits to provide the base current during onstate, which increases the power loss in the control electrode. On the other hand power MOSFETs are voltagecontrolled devices, which require very small current during switching period and hence have simple gate drive requirements. Power MOSFETs are majority carrier devices, which exhibit very high switching speeds. But the unipolar nature of the power
MOSFETs causes inferior conduction characteristics as the voltage rating is increased above 200 V. Therefore their onstate resistance increases with increasing breakdown voltage. Furthermore, as the voltage rating increases the inherent body diode shows inferior reverse recovery characteristics, which leads to higher switching losses. In order to improve the power device performance, it is advantageous to have the low onstate resistance of power BJTs with an insulated gate input like that of a power MOSFET. The Darlington conﬁguration of the two devices shown in Fig. 5.1 has superior characteristics as compared to the two discrete devices. This hybrid device could be gated like a power MOSFET with low onstate resistance because the majority of the output current is handled by the BJT. Because of the low current gain of BJT, a MOSFET of equal size is required as a driver. A more powerful approach to obtain the maximum beneﬁts of the MOS gate control and bipolar current conduction is to integrate the physics of MOSFET and BJT within the same semiconductor region. This concept gave rise to the commercially available IGBTs with superior onstate characteristics, good switching speed and excellent safe operating area. Compared to power MOSFETs the absence of the integral body diode can be considered as an advantage or disadvantage depending on the switching speed and current requirements. An external fast recovery diode or a diode in the same package 71 Copyright © 2001 by Academic Press
72
S. Abedinpour and K. Shenai E
G
MOSFET
time can be signiﬁcantly reduced if all issues of device performance and reliability are taken into consideration at the design stage. As high stress conditions are quite frequent in circuit applications, it is extremely cost efﬁcient and pertinent to model the IGBT performance under these conditions. However, development of the model can follow only after the physics of device operation under stress conditions imposed by the circuit is properly understood. Physically based process and device simulations are a quick and cheap way of optimizing the IGBT. The emergence of mixed mode circuit simulators in which semiconductor carrier dynamics is optimized within the constraints of circuit level switching is a key design tool for this task.
BJT
5.2 Basic Structure and Operation
C
FIGURE 5.1 Hybrid Darlington conﬁguration of MOSFET and BJT.
can be used for speciﬁc applications. The IGBTs are replacing MOSFETs in highvoltage applications with lower conduction losses. They have onstate voltage and current density comparable to a power BJT with higher switching frequency. Although they exhibit fast turnon, their turnoff is slower than a MOSFET because of current fall time. The IGBTs have considerably less silicon area than similar rated power MOSFETs. Therefore by replacing power MOSFETs with IGBTs, the efﬁciency is improved and cost is reduced. IGBT is also known as conductivity modulated FET (COMFET), insulated gate transistor (IGT), and bipolarmode MOSFET. As soft switching topologies offer numerous advantages over the hard switching topologies, their use is increasing in the industry. By the use of softswitching techniques, IGBTs can operate at frequencies up to hundreds of kilohertz. The IGBTs behave differently under soft switching condition as opposed to hard switching conditions. Therefore, the device tradeoffs involved in soft switching circuits are different than those in hard switching case. Application of IGBTs in high power converters subjects them to hightransient electrical stress such as short circuit and turnoff under clamped inductive load and therefore robustness of IGBTs under stress conditions is an important requirement. Traditionally, there has been limited interaction between device manufacturers and power electronic circuit designers. Therefore, shortcomings of device reliability are observed only after the devices are used in actual circuits. This signiﬁcantly slows down the process of power electronic system optimization. The development
The vertical cross section of a half cell of one of the parallel cells of an nchannel IGBT shown in Fig. 5.2 is similar to that of a double diffused power MOSFET (DMOS) except for a p+ layer at the bottom. This layer forms the IGBT collector and a pn junction with n− drift region, where conductivity modulation occurs by injecting minority carriers into the drain drift region of the vertical MOSFET. Therefore, the current density is much greater than a power MOSFET and the forward voltage drop is reduced. The p+ substrate, n− drift layer, and p+ emitter constitute a BJT with a wide base region and hence small current gain. The device operation can be explained by a BJT with its base current controlled by the voltage applied to the MOS gate. For simplicity, it is assumed that the emitter terminal is connected to the ground potential. By applying a negative voltage to the collector, the pn junction between the p+ substrate
Gate
Emitter
E
n+ pbase p+
NPN
G
NMOSFET n−
drift PNP
p + substrate Collector
(a)
C
(b)
FIGURE 5.2 IGBT: (a) halfcell vertical cross section and (b) equivalent circuit model.
5
73
Insulated Gate Bipolar Transistor
and the n− drift region is reverse biased which prevents any current ﬂow and the device is in its reverse blocking state. If the gate terminal is kept at ground potential but a positive potential is applied to the collector, the pn junction between the pbase and n− drift region is reverse biased. This prevents any current ﬂow and the device is in its forward blocking state until the open base breakdown of the pnp transistor is reached. When a positive potential is applied to the gate and exceeds the threshold voltage required to invert the MOS region under the gate an n channel is formed, which provides a path for electrons to ﬂow into the n− drift region. The pn junction between the p+ substrate and n− drift region is forward biased and holes are injected into the drift region. The electrons in the drift region recombine with these holes to maintain space charge neutrality and the remaining holes are collected at the emitter, causing a vertical current ﬂow between the emitter and collector. For small values of collector potential and a gate voltage larger than the threshold voltage the onstate characteristics can be deﬁned by a wide base power BJT. As the current density increases, the injected carrier density exceeds the low doping of the base region and becomes much larger than the background doping. This conductivity modulation decreases the resistance of the drift region, and therefore IGBT has a much greater current density than a power MOSFET with reduced forward voltage drop. The base–collector junction of the pnp BJT cannot be forward biased, and therefore this transistor will not operate in saturation. But when the potential drop across the inversion layer becomes comparable to the difference between the gate voltage and threshold voltage, channel pinchoff occurs. The pinchoff limits the electron current and as a result the holes injected from the p+ layer. Therefore, base current saturation causes the collector current to saturate.
Typical forward characteristics of an IGBT as a function of gate potential and IGBT transfer characteristics are shown in Fig. 5.3. The transfer characteristics of IGBT and MOSFET are similar. The IGBT is in the offstate if the gate–emitter potential is below the threshold voltage. For gate voltages greater than the threshold voltage, the transfer curve is linear over most of the drain current range. Gateoxide breakdown and the maximum IGBT drain current limit the maximum gate–emitter voltage. To turnoff the IGBT, gate is shorted to the emitter to remove the MOS channel and the base current of the pnp transistor. The collector current is suddenly reduced because the electron current from channel is removed. Then the excess carriers in the n− drift region decay by electron–hole recombination, which causes a gradual collector current decay. In order to keep the onstate voltage drop low, the excess carrier lifetime must be kept large. Therefore, similar to the other minority carrier devices there is a tradeoff between onstate losses and faster turnoff switching times. In the punchthrough (PT) IGBT structure of Fig. 5.4 the switching time is reduced by use of a heavily doped n buffer layer in the drift region near the collector. Because of much higher doping density in the buffer layer, the injection efﬁciency of the collector junction and the minority carrier lifetime in the base region is reduced. The smaller excess carrier lifetime in the buffer layer sinks the excess holes. This speeds up the removal of holes from the drift region and therefore decreases the turnoff time. Nonpunchthrough (NPT) IGBTs have higher carrier lifetimes and low doped shallow collector region, which affect their electrical characteristics. In order to prevent punch through, NPT IGBTs have a thicker drift region, which results in a higher base transit time. Therefore in NPT structure carrier lifetime is kept more than that of a PT structure, which causes conductivity modulation of the drift region and reduces the onstate voltage drop.
3
7
COLLECTOR CURRENT (A)
COLLECTOR CURRENT (A)
VGE = 10 V
6 5
9V 4 3
8V
2 7V 1
2
1
6V
0
0 0
2
4
6
8
COLLECTOR VOLTAGE (V)
10
12
0
2
4
GATE VOLTAGE (V)
FIGURE 5.3 IGBT: (a) forward characteristics and (b) transfer characteristics.
6
74
S. Abedinpour and K. Shenai Emitter
Gate
n+ pbase
p+
n− drift n buffer p+ substrate
Collector
FIGURE 5.4 Punchthrough (PT) IGBT structure.
5.3 Static Characteristics In the IGBT structure of Fig. 5.2, if a negative voltage is applied to the collector, the junction between the p+ substrate and n− drift region becomes reverse biased. The drift region is lightly doped and the depletion layer extends principally into the drift region. An open base transistor exists between the p+ substrate, n− drift region, and the pbase region. The doping concentration (ND ) and thickness of the n− drift region (WD ) are designed to avoid the breakdown of this structure. The width of the drift region affects the forward voltage drop and therefore, should be optimized for a desired breakdown voltage. The thickness of the drift region (WD ) is chosen equal to the sum of one diffusion length (Lp ) and the width of the depletion layer at maximum applied voltage (Vmax ). WD =
2εs Vmax + LP qND
(5.1)
When the gate is shorted to the emitter, no channel exists under the gate. Therefore, if a positive voltage is applied to the collector the junction between the pbase and n− drift region is reverse biased and only a small leakage current ﬂows through IGBT. Similar to a MOSFET the depletion layer extends into the pbase and n− drift region. The pbase doping concentration, which also controls the threshold voltage is chosen to
avoid punch through of the pbase to n+ emitter. In ac circuit applications, which require identical forward and reverse blocking capability the drift region thickness of the symmetrical IGBT shown in Fig. 5.2 is designed by use of Eq. (5.1) to avoid reach through of the depletion layer to the junction between the p+ collector and the n− drift region. When IGBT is used in dc circuits, which do not require reverse blocking capability a highly doped n buffer layer is added to the drift region near the collector junction to form a PT IGBT. In this structure, the depletion layer occupies the entire drift region and the n buffer layer prevents reach through of the depletion layer to the p+ collector layer. Therefore the required thickness of the drift region is reduced, which reduces the onstate losses. But the highly doped n buffer layer and p+ collector layer degrade the reverse blocking capability to a very low value. Therefore onstate characteristics of a PT IGBT can be optimized for a required forward blocking capability while the reverse blocking capability is neglected. When a positive voltage is applied to the gate of an IGBT, an MOS channel is formed between the n+ emitter and the n− drift region. Therefore a base current is provided for the parasitic pnp BJT. By applying a positive voltage between the collector and emitter electrodes of an n type IGBT, minority carriers (holes) are injected into the drift region. The injected minority carriers reduce the resistivity of the drift region and reduce the onstate voltage drop resulting in a much higher current density compared to a power MOSFET. If the shorting resistance between the base and emitter of the npn transistor is small, the n+ emitter pbase junction does not become forward biased and therefore the parasitic npn transistor is not active and can be deleted from the equivalent IGBT circuit. The analysis of the forward conduction characteristics of an IGBT is possible by the use of two equivalent circuit approaches. The model based on a PiN rectiﬁer in series with a MOSFET, shown in Fig. 5.5b is easy to analyze and gives a reasonable understanding of the IGBT operation. But this model does not account for the hole current component ﬂowing into the pbase region. The junction between the pbase and the n− drift region is reverse biased. This requires that the free carrier density be zero at this junction, and therefore results in a different boundary condition for IGBT compared to those for PiN rectiﬁer. The IGBT conductivity modulation in the drift region is identical to the PiN rectiﬁer near the collector junction, but it is less than a PiN rectiﬁer near the pbase junction. Therefore, the model based on a bipolar pnp transistor driven by a MOSFET in Fig. 5.5a gives a more complete description of the conduction characteristics. Analyzing the IGBT operation by the use of these models shows that IGBT has one diode drop due to the parasitic diode. Below the diode knee voltage, there is negligible current ﬂow due to the lack of minority carrier injection from the collector. Also by increasing the applied voltage between the gate and emitter, the base of the internal bipolar transistor is supplied by more base current, which results in an increase in the collector
5
75
Insulated Gate Bipolar Transistor E
E
Emitter
Gate
NMOSFET
G
n+
− Vch
G
NMOSFET
pbase
+
− Vacc
PNP
−
p+
PiN DIODE
+
VJFET +
C C
(a)
parasitic thyristor
(b)
− Vdrift
FIGURE 5.5 IGBT equivalent circuits: (a) BJT/MOSFET and (b) PiN/ MOSFET.
+
n − drift
−
current. The IGBT current shows saturation due to the pinchoff of the MOS channel. This limits the input base current of the bipolar transistor. The MOS channel of the IGBT reverse biases the collector–base junction and forces the bipolar pnp transistor to operate in its active region. The drift region is in highlevel injection at the required current densities and wider n− drift region results in higher breakdown voltage. Because of the very low gain of the pnp BJT, the driver MOSFET in the equivalent circuit of the IGBT carries a major portion of the total collector current. Therefore, the IGBT onstate voltage drop as is shown in Fig. 5.6 consists of voltage drop across the collector junction, drift region, and MOSFET portion. The low value of the drift region conductivity modulation near the pbase junction causes a substantial drop across the junction ﬁeld effect transistor (JFET) resistance of the MOSFET (VJFET ) in addition to the voltage drop across the channel resistance (Vch ) and the accumulation layer resistance (Vacc ).
Vp+n +
p + substrate
Collector
FIGURE 5.6 Components of onstate voltage drop within the IGBT structure.
Emitter
Gate
n+
p+ pbase
VCE(on) = Vp + n + Vdrift + VMOSFET VMOSFET = Vch + VJFET + Vacc
(5.2) (5.3)
When the lifetime in the n− drift region is large, the gain of the pnp bipolar transistor is high and its collector current is much larger than the MOSFET current and therefore, the voltage drop across the MOSFET component of IGBT is a small fraction of the total voltage drop. When lifetime control techniques are used to increase the switching speed, the current gain of the bipolar transistor is reduced and a greater portion of the current ﬂows through the MOSFET channel and therefore the voltage drop across the MOSFET increases. In order to decrease the resistance of the MOSFET current path, trench IGBTs can be used as shown in Fig. 5.7. Extending the trench gate below the pbase and n− drift region junction forms a channel between the n+ emitter and the n− drift region. This eliminates the JFET and accumulation layer resistance
n − drift n buffer p + substrate
Collector
FIGURE 5.7 Trench IGBT structure.
76
S. Abedinpour and K. Shenai
and therefore reduces the voltage drop across the MOSFET component of IGBT, which results in a superior conduction characteristics. By the use of trench structure, the IGBT cell density and latching current density are also improved.
5.4 Dynamic Switching Characteristics 5.4.1 Turnon Characteristics The switching waveforms of an IGBT in a clamped inductive circuit are shown in Fig. 5.8. The L/R time constant of the inductive load is assumed to be large compared to the switching frequency and therefore, can be considered as a constant current source Ion . The IGBT turnon switching performance is dominated by its MOS structure. During td(on) , the gate current charges the constant input capacitance with a constant slope until the gate–emitter voltage reaches the threshold voltage VGE(th) of the device. During tri , load current is transferred from the diode into the device and increases to its steadystate value. The gate voltage rise time and IGBT transconductance determine the current slope and results as tri . When the gate–emitter voltage reaches VGE(Ion) , which will support the steadystate collector current, collector–emitter voltage starts to decrease. After this there are two distinct intervals, during
VGG+ VGE(Ion) VGE(th)
vGE(t)
t
td(on)
Ion iC(t)
5.4.2 Turnoff Characteristics Turnoff begins by removing the gate–emitter voltage. Voltage and current remain constant until the gate voltage reaches VGE(Ion) , required to maintain the collector steadystate current as shown in Fig. 5.9. After this delay time (td(off ) ) the collector voltage rises, while the current is held constant. The gate resistance determines the rate of collector voltage rise. As the MOS channel turns off, collector current decreases sharply during tﬁ1 . The MOSFET portion of IGBT determines the turnoff delay time td(off ) and the voltage rise time trv . When the collector voltage reaches the bus voltage, the freewheeling diode starts to conduct. However the excess stored charge in the n− drift region during onstate conduction, must be removed for the device to turnoff. The high minority carrier concentration stored in the n− drift region supports the collector current after the MOS channel is turned off. Recombination of the minority carriers in the wide base region gradually decreases the collector current and results in a current tail. Since there is no access to the base of the pnp transistor, the excess minority carriers cannot be removed by reverse biasing the gate. The tﬁ2 interval is long because the excess carrier lifetime in this region is normally kept high to reduce the onstate voltage drop. Since the collector–emitter voltage has reached the bus voltage in this interval, a signiﬁcant power loss occurs which increases with frequency. Therefore, the current tail limits the IGBT operating frequency and there is a tradeoff between the onstate losses and faster switching times. For an onstate current of Ion , the magnitude of the current tail, and the time required for the collector current to decrease to 10% of its onstate value, turnoff (toff ) time, are approximated as:
t
tri Vcc vCE(t)
IGBT turnon. In the ﬁrst interval, the collector to emitter voltage drops rapidly as the gate–drain capacitance Cgd of the MOSFET portion of IGBT discharges. At low collector–emitter voltage Cgd increases. A ﬁnite time is required for highlevel injection conditions to set in the drift region. The pnp transistor portion of IGBT has a slower transition to its onstate than the MOSFET. The gate voltage starts rising again only after the transistor comes out of its saturation region into the linear region, when complete conductivity modulation occurs and the collector–emitter voltage reaches its ﬁnal onstate value.
tfv2 tfv1
Ic (t ) = αpnp Ion e−t /τHL
(5.4)
toff = τHL ln(10αpnp )
(5.5)
where
VCE(on)
t
FIGURE 5.8 IGBT turnon waveforms in a clamped inductive load circuit.
αpnp = sec h
l La
(5.6)
is the gain of the bipolar pnp transistor, l is the undepleted base width, and La is the ambipolar diffusion length and it
5
77
Insulated Gate Bipolar Transistor
VGG+ VGE(Ion) vGE(t)
t
VGG−
VGE(th) td(off)
tfi1
tfi2 Ion
iC(t)
t
Vcc VCE(on) vCE(t)
trv t
FIGURE 5.9 Switching waveforms during IGBT clamped inductive load turnoff.
is assumed that the high level lifetime (τHL ) is independent of the minority carrier injection during the collector current decay. Lifetimecontrol techniques are used to reduce the lifetime (τHL ) and the gain of the bipolar transistor (αpnp ). As a result, the magnitude of the current tail and toff decrease. But the conductivity modulation decreases, which increases the onstate voltage drop in the drift region. Therefore, higher speed IGBTs have a lower current rating. Thermal diffusion of impurities such as gold and platinum introduces recombination centers, which reduce the lifetime. The device can also be irradiated with highenergy electrons to generate recombination centers. Electron irradiation introduces a uniform distribution of defects, which results in reduction of lifetime in the entire wafer and affects the conduction properties of the device. Another method of lifetime control is proton implantation, which can place defects at a speciﬁc depth. Therefore, it is possible to have a localized control of lifetime to improve the tradeoff between the onstate voltage and switching speed of the device. The turnoff loss can be minimized by curtailing the current tail as a result of speeding up the recombination
process in the portion of the drift region, which is not swept by the reverse bias.
5.4.3 Latchup of Parasitic Thyristor A portion of minority carriers injected into the drift region from the collector of an IGBT ﬂows directly to the emitter terminal. The negative charge of electrons in the inversion layer attracts the majority of holes and generates the lateral component of hole current through the ptype body layer as shown in Fig. 5.10. This lateral current ﬂow develops a voltage drop across the spreading resistance of the pbase region, which forward biases the base–emitter junction of the npn parasitic BJT. By designing a small spreading resistance, the voltage drop is lower than the builtin potential and therefore the parasitic thyristor between the p+ collector region, n− drift region, pbase region, and n+ emitter does not latchup. Larger values of onstate current density produce a larger voltage drop, which causes injection of electrons from the emitter region into the pbase region and hence turns on the npn transistor. When this occurs the pnp transistor will turnon,
78
S. Abedinpour and K. Shenai Emitter
Gate
n+
of deep p+ diffusion improve the latchup immunity of IGBT. But inadequate extent of the p+ region may fail to prevent the device from latchup. Also care should be taken that the p+ diffusion does not extend into the MOS channel because this causes an increase in the MOS threshold voltage.
pbase
5.5 IGBT Performance Parameters p+
The IGBTs are characterized by certain performance parameters. The manufacturers specify these parameters, which are described below, in the IGBT data sheet. The important ratings of IGBTs are values, which establish either a minimum or maximum limiting capability or limiting condition. The IGBTs cannot be operated beyond the maximum or minimum rating’s value, which are determined for a speciﬁed operating point and environment condition.
parasitic thyristor n − drift
p + substrate
Collector
FIGURE 5.10 Onstate current ﬂow paths in an IGBT structure.
therefore the parasitic thyristor will latchup and the gate loses control over the collector current. Under dynamic turnoff conditions the magnitude of the lateral hole current ﬂow increases and latchup can occur at lower onstate currents compared to the static condition. The parasitic thyristor latches up when the sum of the current gains of the npn and pnp transistors exceeds one. When the gate voltage is removed from IGBT with a clamped inductive load, its MOSFET component turns off and reduces the MOSFET current to zero very rapidly. As a result the drain–source voltage rises rapidly and is supported by the junction between the n− drift region and the pbase region. The drift region has a lower doping and therefore the depletion layer extends more in the drift region. As a result the current gain of the pnp transistor portion, αpnp increases and a greater portion of the injected holes into the drift region will be collected at the junction of pbase and n− drift regions. Therefore, the magnitude of the lateral hole current increases, which increases the lateral voltage drop. As a result the parasitic thyristor will latchup even if the onstate current is less than the static latchup value. Reducing the gain of the npn or pnp transistors can prevent the parasitic thyristor latchup. A reduction in the gain of the pnp transistor increases the IGBT onstate voltage drop. Therefore in order to prevent the parasitic thyristor latchup, it is better to reduce the gain of the npn transistor component of IGBT. Reduction of carrier lifetime, use of buffer layer, and use
Collector–Emitter blocking voltage (BVCES ): This parameter speciﬁes the maximum offstate collector–emitter voltage when the gate and emitter are shorted. Breakdown is speciﬁed at a speciﬁc leakage current and varies with temperature by a positive temperature coefﬁcient. Emitter–Collector blocking voltage (BVECS ): This parameter speciﬁes the reverse breakdown of the collector–base junction of the pnp transistor component of IGBT. Gate–Emitter voltage (VGES ): This parameter determines the maximum allowable gate–emitter voltage, when collector is shorted to emitter. The thickness and characteristics of the gateoxide layer determine this voltage. The gate voltage should be limited to a much lower value to limit the collector current under fault conditions. Continuous collector current (IC ): This parameter represents the value of the dc current required to raise the junction to its maximum temperature, from a speciﬁed case temperature. This rating is speciﬁed at a case temperature of 25◦ C and maximum junction temperature of 150◦ C. Since normal operating condition cause higher case temperatures, a plot is given to show the variation of this rating with case temperature. Peak collector repetitive current (ICM ): Under transient conditions, the IGBT can withstand higher peak currents compared to its maximum continuous current, which is described by this parameter. Maximum power dissipation (PD ): This parameter represents the power dissipation required to raise the junction temperature to its maximum value of 150◦ C, at a case temperature of 25◦ C. Normally a plot is provided to show the variation of this rating with temperature. Junction temperature (Tj ): Speciﬁes the allowable range of the IGBT junction temperature during its operation. Clamped inductive load current (ILM ): This parameter speciﬁes the maximum repetitive current that IGBT can turnoff under a clamped inductive load. During IGBT turnon, the reverse recovery current of the freewheeling diode in parallel with the inductive load increases the IGBT turnon switching loss.
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Collector–Emitter leakage current (ICES ): This parameter determines the leakage current at the rated voltage and speciﬁc temperature when the gate is shorted to emitter. Gate–Emitter threshold voltage (VGE(th) ): This parameter speciﬁes the gate–emitter voltage range, where the IGBT is turned on to conduct the collector current. The threshold voltage has a negative temperature coefﬁcient. Threshold voltage increases linearly with gateoxide thickness and as the square root of the pbase doping concentration. Fixed surface charge at the oxide–silicon interface and mobile ions in the oxide shift the threshold voltage. Collector–Emitter saturation voltage (VCE(SAT) ): This parameter speciﬁes the collector–emitter forward voltage drop and is a function of collector current, gate voltage, and temperature. Reducing the resistance of the MOSFET channel and JFET region, and increasing the gain of the pnp bipolar transistor can minimize the onstate voltage drop. The voltage drop across the MOSFET component of IGBT, which provides the base current of the pnp transistor is reduced by a larger channel width, shorter channel length, lower threshold voltage, and wider gate length. Higher minority carrier lifetime and a thin nepi region cause high carrier injection and reduce the voltage drop in the drift region. Forward transconductance (gFE ): Forward transconductance is measured with a small variation on the gate voltage, which linearly increases the IGBT collector current to its rated current at 100◦ C. The transconductance of an IGBT is reduced at currents much higher than its thermal handling capability. Therefore, unlike the bipolar transistors, the current handling capability of IGBTs is limited by thermal consideration and not by its gain. At higher temperatures, the transconductance starts to decrease at lower collector currents. Therefore, these features of transconductance protects the IGBT under short circuit operation. Total gate charge (QG ): This parameter helps to design a suitable size gate drive circuit and approximately calculate its losses. Because of the minority carrier behavior of device, the switching times cannot be approximately calculated by the use of gate charge value. This parameter varies as a function of the gate–emitter voltage. Turnon delay time (td ): It is deﬁned as the time between 10% of gate voltage and 10% of the ﬁnal collector current. Rise time (tr ): It is the time required for the collector current to increase to 90% of its ﬁnal value from 10% of its ﬁnal value. Turnoff delay time (td(off ) ): It is the time between 90% of gate voltage and 10% of ﬁnal collector voltage. Fall time (tf ): It is the time required for the collector current to drop from 90% of its initial value to 10% of its initial value. Input capacitance (Cies ): It is the measured gate–emitter capacitance when collector is shorted to emitter. The input capacitance is the sum of the gate–emitter and the miller capacitance. The gate–emitter capacitance is much larger than the miller capacitance. Output capacitance (Coes ): It is the capacitance between collector and emitter when gate is shorted to the emitter, which has the typical pn junction voltage dependency.
Reverse transfer capacitance (Cres ): It is the miller capacitance between gate and collector, which has a complex voltage dependency. Safe operating area (SOA): The safe operating area determines the current and voltage boundary within which the IGBT can be operated without destructive failure. At low currents the maximum IGBT voltage is limited by the open base transistor breakdown. The parasitic thyristor latchup limits the maximum collector current at low voltages. The IGBTs immune to static latchup may be vulnerable to dynamic latchup. Operation in short circuit and inductive load switching are conditions that would subject an IGBT to a combined voltage and current stress. Forward biased safe operating area (FBSOA) is deﬁned during the turnon transient of the inductive load switching when both electron and hole current ﬂow in the IGBT in the presence of high voltage across the device. The reverse biased safe operating area (RBSOA) is deﬁned during the turnoff transient, where only hole current ﬂows in the IGBT with high voltage across it.
If the time duration of simultaneous high voltage and high current is long enough, the IGBT failure will occur because of thermal breakdown. But if this time duration is short, the temperature rise due to power dissipation will not be enough to cause thermal breakdown. Under this condition the avalanche breakdown occurs at voltage levels lower than the breakdown voltage of the device. Compared to the steadystate forward blocking condition the much larger charge in the drift region causes a higher electric ﬁeld and narrower depletion region at the pbase and n− drift junction. Under RBSOA conditions there is no electron in the space charge region, and therefore there is a larger increase in electric ﬁeld than the FBSOA condition. The IGBT SOA is indicated in Fig. 5.11. Under shortswitching times the rectangular SOA shrinks by increase in
SOA
iT
10−5 sec
Io
10−4 sec
Switchmode
Zerovoltage/ zero current switching
DC
VBUS
VBD
FIGURE 5.11 IGBT safe operating area (SOA).
vT
80
the duration of ontime. Thermal limitation is the reason for smaller SOA and the lower limit is set by dc operating conditions. The device switching loci under hard switching (dashed lines) and zero voltage or zero current switching (solid lines) is also indicated in Fig. 5.11. The excursion is much wider for switchmode hardswitching applications than for the softswitching case, and therefore a much wider SOA is required for hardswitching applications. Presently IGBTs are optimized for hardswitching applications. In softswitching applications the conduction losses of IGBT can be optimized at the cost of smaller SOA. In this case the pbase doping can be adjusted to result in a much lower threshold voltage and hence forward voltage drop. But in hardswitching applications, the SOA requirements dominate over forward voltage drop and switching time. Therefore, the pbase resistance should be reduced, which causes a higher threshold voltage. As a result, the channel resistance and forward voltage drop will increase.
5.6 Gate Drive Requirements The gate drive circuit acts as an interface between the logic signals of the controller and the gate signals of the IGBT, which reproduces the commanded switching function at a higher power level. Nonidealities of the IGBT such as ﬁnite voltage and current rise and fall times, turnon delay, voltage and current overshoots, and parasitic components of the circuit cause differences between the commanded and real waveforms. Gate drive characteristics affect the IGBT nonidealities. The MOSFET portion of the IGBT drives the base of the pnp transistor and therefore the turnon transient and losses is greatly affected by the gate drive. Due to lower switching losses, softswitched power converters require gate drives with higher power ratings. The IGBT gate drive must have sufﬁcient peak current capability to provide the required gate charge for zero current switching and zero voltage switching. The delay of the input signal to the gate drive should be small compared to the IGBT switching period and therefore, the gate drive speed should be designed properly to be able to use the advantages of faster switching speeds of the new generation IGBTs.
S. Abedinpour and K. Shenai Vgg+ C
Rgon
G Rgoff
E
Vgg−
FIGURE 5.12 Gate drive circuit with independent turnon and turnoff resistors.
Vgg+ C
Rg
G
5.6.1 Conventional Gate Drives The ﬁrst IGBT gate drives used ﬁxed passive components and were similar to MOSFET gate drives. Conventional gate drive circuits use a ﬁxed gate resistance for turnon and turnoff as shown in Fig. 5.12. The turnon gate resistor Rgon limits the maximum collector current during turnon, and the turnoff gate resistor Rgoff limits the maximum collector–emitter voltage. In order to decouple the dvce /dt and dic /dt control, an external capacitance Cg can be used at the gate, which increases the time constant of the gate circuit and reduces the dic /dt as shown in Fig. 5.13. But Cg does not affect the dvce /dt
Cg
Vgg−
E
FIGURE 5.13 External gate capacitor for decoupling dvce /dt and dic /dt during switching transient.
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transient, which occurs during the miller plateau region of the gate voltage.
5.6.2 New Gate Drive Circuits In order to reduce the delay time required for the gate voltage to increase from Vgg − to Vge (th), the external gate capacitor can be introduced in the circuit only after Vge reaches Vge (th) as is shown in Fig. 5.14, where the collector current rise occurs. The voltage tail during turnon transient is not affected by this method. In order to prevent shoot through caused by accidental turnon of IGBT due to noise, a negative gate voltage is required during offstate. Low gate impedance reduces the effect of noise on gate. During the ﬁrst slope of the gate voltage turnon transient, the rate of charge supply to the gate determines the collector current slope. During the miller effect zone of the turnon transient the rate of charge supply to the gate determines the collector voltage slope. Therefore, the slope of the collector current, which is controlled by the gate resistance, strongly affects the turnon power loss. Reduction in switching power loss requires low gate resistance. But the collector current slope also determines the amplitude of the conducted electromagnetic interference (EMI) during turnon switching transient. Lower EMI generation requires higher values of gate resistance. Therefore, in conventional gate drive circuits by Vgg+
selecting an optimum value for Rg , there is a tradeoff between lower switching losses and lower EMI generation. But the turnoff switching of IGBT depends on the bipolar characteristics. Carrier lifetime determines the rate at which the minority carriers stored in the drift region recombine. The charge removed from the gate during turnoff has small inﬂuence on minority carrier recombination. The tail current and di/dt during turnoff, which determine the turnoff losses, depend mostly on the amount of stored charge and the minority carriers lifetime. Therefore, the gate drive circuit has a minor inﬂuence on turnoff losses of the IGBT, while it affects the turnon switching losses. The turnon transient is improved by use of the circuit shown in Fig. 5.15. The additional current source increases the gate current during the tail voltage time, and therefore reduces the turnon loss. The initial gate current is determined by Vgg + and Rgon , which are chosen to satisfy device electrical speciﬁcations and EMI requirements. After the collector current reaches its maximum value, the miller effect occurs and the controlled current source is enabled to increase the gate current to increase the rate of collector voltage fall. This reduces the turnon switching loss. Turnoff losses can only be reduced during the miller effect and MOS turnoff portion of the turnoff transient, by reducing the gate resistance. But this increases the rate of change of collector voltage, which strongly affects the IGBT latching current and RBSOA. During the turnoff
Vgg+ C C
Rg Rgon G G
Rgoff
Cg
T1
Vgg−
Vgg−
E
FIGURE 5.14 A circuit for reducing the turnon delay.
E
FIGURE 5.15 Schematic circuit of an IGBT gate drive circuit.
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period, the turnoff gate resistor Rgoff determines the maximum rate of collector voltage change. After the device turns off, turning on transistor T1 prevents the spurious turnon of IGBT by preventing the gate voltage to reach the threshold voltage.
5.6.3 Protection Gate drive circuits can also provide fault protection of IGBT in the circuit. The fault protection methods used in IGBT converters are different from their gate turnoff thyristor (GTO) counterparts. In a GTO converter, a crowbar is used for protection and as a result there is no current limiting. When the short circuit is detected the control circuit turns on all the GTO switches in the converter, which results in the opening of a fuse or circuit breaker on the dc input. Therefore, series di/dt snubbers are required to prevent rapid increase of the fault current and the snubber inductor has to be rated for large currents in the fault condition. But IGBT has an important ability to intrinsically limit the current under overcurrent and short circuit fault conditions. However, the value of the fault current can be much larger than the nominal IGBT current. Therefore, IGBT has to be turned off rapidly after the fault occurs. The magnitude of the fault current depends on the positive gate bias voltage Vgg + . A higher Vgg + is required to reduce conduction loss in the device, but this leads to larger fault currents. In order to decouple the tradeoff limitation between conduction loss and fault current level, a protection circuit can reduce the gate voltage when a fault occurs. But this does not limit the peak value of the fault current, and therefore, a fast fault detection circuit is required to limit the peak value of the fault current. Fast integrated sensors in the gate drive circuit are essential for proper IGBT protection. Various methods have been studied to protect IGBTs under fault conditions. One of the techniques uses a capacitor to reduce the gate voltage when the fault occurs. But depending on the initial condition of the capacitor and its value the IGBT current may reduce to zero and then turned on again. Another method is to softly turnoff the IGBT after the fault and to reduce the overvoltage due to dic /dt. Therefore the overvoltage on IGBT caused by the parasitic inductance is limited while turning off large currents. The most common method of IGBT protection is the collector voltage monitoring or desat detection. The monitored parameter is the collector– emitter voltage, which makes fault detection easier compared to measuring the device current. But voltage detection can be activated only after the complete turnon of IGBT. If the fault current increases slowly due to large fault inductance, the fault detection is difﬁcult because the collector–emitter voltage will not change signiﬁcantly. In order to determine whether the current that is being turned off is overcurrent or nominal current, the miller voltage plateau level can be used. This method can be used to initiate soft turnoff and reduce the overvoltage during overcurrents.
S. Abedinpour and K. Shenai
Special sense IGBTs have been introduced at low power levels with a sense terminal to provide a current signal proportional to the IGBT collector current. A few active device cells are used to mirror the current carried by the other cells. But unfortunately, sense IGBTs are not available at high power levels and there are problems related to the higher conduction losses in the sense device. The most reliable method to detect an overcurrent fault condition is to introduce a current sensor in series with the IGBT. The additional current sensor makes the power circuit more complex and may lead to parasitic bus inductance, which results in higher overvoltages during turnoff. After the fault occurs, the IGBT has to be safely turned off. Due to large dic /dt during turnoff, the overvoltage can be very large. Therefore, many techniques have been investigated to obtain soft turnoff. The most common method is to use large turnoff gate resistor when the fault occurs. Another method to reduce the turnoff overvoltage is to lower the fault current level by reducing the gate voltage before initiating the turnoff. A resistive voltage divider can be used to reduce the gate voltage during fault turnoff. For example, the gate voltage reduction can be obtained by turning on simultaneously Rgoff and Rgon in the circuit of Fig. 5.12. Another method is to switch a capacitor into the gate and rapidly discharge the gate during the occurrence of a fault. To prevent the capacitor from charging back up to the nominal onstate gate voltage, a large capacitor should be used, which may cause a rapid gate discharge. Also a zener can be used in the gate to reduce the gate voltage after a fault occurs. But the slow transient behavior of the zener leads to large initial peak fault current. The power dissipation during a fault determines the time duration that the fault current can ﬂow in the IGBT without damaging it. Therefore, the IGBT fault endurance capability is improved by the use of fault current limiting circuits to reduce the power dissipation in the IGBT under fault conditions.
5.7 Circuit Models Highquality IGBT model for circuit simulation is essential for improving the efﬁciency and reliability in the design of power electronic circuits. Conventional models for power semiconductor devices simply described an abrupt or linear switching behavior and a ﬁxed resistance during the conduction state. Low switching frequencies of power circuits made it possible to use these approximate models. But moving to higher switching frequencies to reduce the size of a power electronic system requires highquality power semiconductor device models for circuit simulation. The nchannel IGBT consists of a pnp bipolar transistor whose base current is provided by an nchannel MOSFET, as is shown in Fig. 5.1. Therefore, the IGBT behavior is determined by the physics of the bipolar and MOSFET devices.
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Several effects dominate the static and dynamic device characteristics. The inﬂuence of these effects on lowpower semiconductor device is negligible and therefore they cannot be described by standard device models. The conventional circuit models were developed to describe the behavior of low power devices, and therefore were not adequate to be modiﬁed for IGBT. The reason is that the bipolar transistor and MOSFET in the IGBT have a different behavior compared to their lowpower counterparts and have different structures. The present available models have different levels of accuracy at the expense of speed. Circuit issues such as switching losses and reliability are strongly dependent on the device and require accurate device models. But simpler models are only adequate for system oriented issues such as the behavior of an electric motor driven by a pulse width modulation (PWM) converter. Finite element models have high accuracy, but are slow and require internal device structure details. Macro models are fast but have low accuracy, which depends on the operating point. Recently commercial circuit simulators have introduced onedimensional physicsbased models, which offer a compromise between the ﬁnite element models and macro models. The Hefner model and the Kraus model are such examples that have been implemented in Saber and there has been some effort to implement them in PSPICE. The Hefner model depends on the redistribution of charge in the drift region during transients. The Kraus model depends on the extraction of charge from the drift region by the electric ﬁeld and emitter back injection. The internal BJT of the IGBT has a wide base, which is lightly doped to support the depletion region to have high blocking voltages. The excess carrier lifetime in the base region is low to have fast turnoff. But low power bipolar transistors have high excess carrier lifetime in the base, narrow base, and high current gain. A ﬁnite base transit time is required for a change in the injected base charge to change the collector current. Therefore, quasistatic approximation cannot be used at high speeds and the transport of carriers in the base should be described by ambipolar transport theory.
5.7.1 Input and Output Characteristics The bipolar and MOSFET components of a symmetric IGBT are shown in Fig. 5.16. The components between the emitter (e), base (b), and collector (c) terminals correspond to the bipolar transistor and those between gate (g), source (s), and drain (d) are associated with MOSFET. The combination of the drain–source and gate–drain depletion capacitances is identical to the base–collector depletion capacitance, and therefore they are shown for the MOSFET components. The gateoxide capacitance of the source overlap (Coxs ) and source metallization capacitance (Cm ) form the gate–source capacitance (Cgs ). When the MOSFET is in its linear region the gateoxide capacitance of the drain overlap (Coxd ) forms the gate–drain capacitance (Cgd ). In the saturation region of
Cathode
Gate Cm
Coxd
Coxs
n+ s
pbase
p+
Cgdj
Cdsj
c b
d Rb Ccer
Cebj +Cebd
e
n − drift p + substrate
Anode
FIGURE 5.16 Symmetric IGBT half cell.
MOSFET the equivalent series connection of gate–drain overlap oxide capacitance and the depletion capacitance of the gate–drain overlap (Cgdj ) forms the gate–drain miller capacitance. The gate–drain depletion width and the drain–source depletion width are voltage dependent, which has the same effect on the corresponding capacitances. The most important capacitance in IGBT is the capacitance between the input terminal (g) and output terminal (a), because the switching characteristics is affected by this feedback. Cga
dQg dvox = Cox dvga dvga
(5.7)
Cox is determined by the oxide thickness and device area. The accumulation, depletion, and inversion states below the gate cause different states of charge and therefore different capacitance values. The stored charge in the lightly doped wide base of the bipolar component of IGBT causes switching delays and switching losses. The standard quasistatic charge description
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is not adequate for IGBT because it assumes that the charge distribution is a function of the IGBT terminal voltage. But the stored charge density (P(x,t)) changes with time and position and therefore the ambipolar diffusion equation must be used to describe the charge variation. dP(x,t ) P(x,t ) d 2 P(x,t ) =− + Da dt τa dx 2
GATE CATHODE g
Cgs
(5.8)
The slope of the charge carrier distribution determines the sum of electron and hole currents. The nonquasistatic behavior of the stored charge in the base of the bipolar component of IGBT results in the collector–emitter redistribution capacitance (Ccer ). This capacitance dominates the output capacitance of IGBT during turnoff and describes the rate of change of base–collector depletion layer with the rate of change of base–collector voltage. But the base–collector displacement current is determined by the gate–drain (Cgdj ) and drain–source (Cdsj ) capacitance of the MOSFET component.
5.7.2 Implementing the IGBT Model into a Circuit Simulator Usually a netlist is used in a circuit simulator such as Saber to describe an electrical circuit. Each component of the circuit is deﬁned by a model template with the component terminal connection and the model parameters values. While Saber libraries provide some standard component models, the models can be generated by implementing the model equations in a deﬁned saber template. Electrical component models of IGBT are deﬁned by the current through each component element as a function of component variables, such as terminal and internal node voltages and explicitly deﬁned variables. The circuit simulator uses the Kirchhoff’s current law to solve for electrical component variables such that the total current into each node is equal to zero, while satisfying the explicitly deﬁned component variables needed to describe the state of the device. The IGBT circuit model is generated by deﬁning the currents between terminal nodes as a nonlinear function of component variables and their rate of change. An IGBT circuit model is shown in Fig. 5.17. Compared to Fig. 5.16, the bipolar transistor is replaced by the two base and collector current sources. There is a distributed voltage drop due to diffusion and drift in the base regions. The drift terms in the ambipolar diffusion equation depends on base and collector currents. Therefore, both of these currents generate the resistive voltage drop Vae and Rb is placed at the emitterterminal in the IGBT circuit model. The capacitance of the emitter–base junction (Ceb ) is implicitly deﬁned by the emitter–base voltage as a function of base charge. Iceb is the emitter–base capacitor current which deﬁnes the rate of change of the base charge. The current through the collector–emitter redistribution capacitance (Iccer ) is part of the collector current, which in contrast
s
c
Cdsj
Ic
Cgd
Imos
Imult b
Iccer Icss
d
Ibss
Ccer
Iceb Ceb
e Rb a ANODE
FIGURE 5.17 IGBT circuit model.
to Icss depends on the rate of change of the base–emitter voltage. Ibss is part of the base current that does not ﬂow through Ceb and does not depend on rate of change of base–collector voltage. Impact ionization causes carrier multiplication in the high electric ﬁeld of the base–collector depletion region. This carrier multiplication generates an additional base–collector current component (Imult ), which is proportional to Ic , Imos , and the multiplication factor. The resulting Saber IGBT model should be able to describe accurately the experimental results for the range of static and dynamic conditions where IGBT operates. Therefore, the model can be used to describe the steadystate and dynamic characteristics under various circuit conditions. The present available models have different levels of accuracy at the expense of speed. Circuit issues such as switching losses and reliability are strongly dependent on the device and require accurate device models. But simpler models are adequate for system oriented issues such as the behavior of an electric motor driven by a PWM converter. Finite element models have high accuracy, but are slow and require internal device structure details. Macro models are fast but have low accuracy, which depends on the operating point. Recently commercial circuit simulators have introduced onedimensional
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physicsbased models, which offer a compromise between the ﬁnite element models and macro models.
5.8 Applications Power electronics evolution is a result of the evolution of power semiconductor devices. Applications of power electronics are still expanding in industrial and utility systems. A major challenge in designing power electronic systems is a simultaneous operation at high power and highswitching frequency. The advent of IGBTs has revolutionized power electronics by extending the power and frequency boundary. During the last decade, the conduction and switching losses of IGBTs has been reduced in the process of transition from the ﬁrst to the third generation IGBTs. The improved charcteristics of the IGBTs have resulted in higher switching speed and lower energy losses. High voltage IGBTs are expected to take the place of high voltage GTO thyristor converters in the near future. To advance the performance beyond the third generation IGBTs, the fourth generation devices will require exploiting ﬁneline lithographic technology and employing the trench technology used to produce power MOSFETs with very low onstate resistance. Intelligent IGBT or intelligent power module (IPM) is an attractive power device integrated with circuits to protect against overcurrent, overvoltage, and overheat. The main
application of IGBT is for use as a switching component in inverter circuits, which are used in both power supply and motordrive applications. The advantages of using IGBT in these converters are simplicity and modularity of the converter, simple gate drive, elimination of snubber circuits due to the square SOA, lower switching loss, improved protection characteristics in case of overcurrent and short circuit fault, galvanic isolation of the modules, and simpler mechanical construction of the power converter. These advantages have made the IGBT the preferred switching device in the power range below 1 MW. Power supply applications of IGBTs include uninterruptible power supplies (UPS) as is shown in Fig. 5.18, constant voltage, constant frequency power supplies, induction heating systems, switch mode power supplies, welders (Fig. 5.19), cutters, traction power supplies, and medical equipment (CT, Xray). Low noise operation, small size, low cost, and high accuracy are chracteristics of the IGBT converters in these applications. Examples of motordrive applications include variable voltage, variable frequency inverter as is shown in Fig. 5.20. The IGBTS have been recently introduced at high voltage and current levels, which has enabled their use in high power converters utilized for medium voltage motor drives. The improved characteristics of the IGBTs have introduced power converters in megawatt power applications such as traction drives. One of the critical issues in realizing high power
FIGURE 5.18 Constant voltage, constant frequency inverter (UPS).
FIGURE 5.19 IGBT welder.
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FIGURE 5.20 Variable voltage, variable frequency inverter (PWM).
converters is the reliability of the power switches. The devices used in these applications must be robust and capable of withstanding faults long enough for a protection scheme to be activated. The hard switching voltage source power converter is the most commonly used topology. In this switchmode operation, the switches are subjected to high switching stresses and high switching power loss that increases linearly with the switching frequency of the PWM. The resulting switching loci in the vt –it plane is shown by the dotted lines in Fig. 5.11. Because of simultaneous large switch voltage and large switch current, the switch must be capable of withstanding high switching stresses with a large SOA. The requirement of being able to withstand large stresses results in design compromises in other characteristics of the power semiconductor device. Often forward voltage drop and switching speed are sacriﬁced for enhanced short circuit capability. Process parameters of the IGBT such as threshold voltage, carrier lifetime, and the device thickness can be varied to obtain various combinations of SOA, onstate voltage, and switching time. However, there is very little overlap in the optimum combination for more than one performance parameter. Therefore, improved performance in one parameter is achieved at the cost of other parameters. In order to reduce the size, the weight, and the cost of circuit components used in a power electronics converter very highswitching frequencies of the order of few megahertz are being contemplated. In order to be able to increase the switching frequency, the problems of switch stresses, switching losses, and the EMI associated with switchmode applications need to be overcome. Use of softswitching converters reduces the problems of high dv/dt and high di/dt by the use of external inductive and capacitive components to shape the switching trajectory of device. The device switching loci resulting from soft switching is shown in Fig. 5.11, where signiﬁcant reduction in switching stress can be noticed. The traditional snubber circuits achieves this goal without the added control complexity, but the power dissipation in these snubber circuits can be large and limit the switching frequency of the converter. Also passive components signiﬁcantly add to the size, weight, and cost of the converter at high power levels. Soft switching uses lossless resonant circuits, which overcomes the problem
of power loss in the snubber circuit, but increases the conduction loss. Resonant transition circuits eliminate the problem of high peak device stress in the softswitched converters. The main drawback of these circuits is the increased control complexity required to obtain the resonant switching transition. The large number of circuit variables that have to be sensed in such power converters can affect their reliability. Short circuit capability no longer being the primary concern, designers can push the performance envelope for their circuits until the device becomes the limiting factor once again. The transient response of the conventional volts/hertz induction motor drive is sluggish, because both torque and ﬂux are functions of stator voltage and frequency. Use of vector or ﬁeld oriented control methods makes the performance of the induction motor drive almost identical to that of a separately excited dc motor. Therefore, the transient response is like a dc machine, where torque and ﬂux can be controlled in a decoupled manner. Vector controlled induction motors with shaft encoders or speed sensors have been widely applied in combination with voltage source PWM inverters using IGBT modules. According to the speciﬁcation of the new products, vector controlled induction motor drive systems ranging from kilowatts to megawatts provide a broad range of speed control, constant torque operation, and high starting torque. Because of their simple gate drives and modular packaging, IGBTs lead to simpler construction of power electronic circuits. This feature has lead to a trend to standardize and modularize power electronic circuits. Simpliﬁcation of the overall system design and construction and signiﬁcant cost reduction are the main implications of this approach. With these goals the power electronics building block (PEBB) program has been introduced, where the entire power electronic converter system is reduced to a single block. Similar modular power electronic blocks are commercially available at low power levels in the form of power integrated circuits. At higher power levels, these blocks have been realized in the form of intelligent power modules and power blocks. But these high power modules do not encompass the entire power electronic systems like motor drives and UPS. The aim of the PEBB program is to realize the whole power handling system within standardized blocks. A PEBB is a universal power processor
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that changes any electrical power input to any desired form of voltage, current, and frequency output. A PEBB is a single package with a multifunction controller that replaces the complex power electronic circuits with a single device and therefore reduces the development and design costs of the complex power circuits and simpliﬁes the development and design of large electric power systems. The applications of power electronics are varied and various applications have their own speciﬁc design requirement. There is a wide choice of available power devices. Because of physical, material, and design limitations, none of the presently available devices behave as an ideal switch, which should block arbitrarily large forward and reverse voltages with zero current in the offstate, conduct arbitrarily large currents with zero voltage drop in the onstate, and have negligible switching time and power loss. Therefore, power electronic circuits should be designed by considering the capabilities and limitations of available devices. Traditionally there has been limited interaction between device manufacturers and circuit designers. Therefore, manufacturers have been fabricating generic power semiconductor devices with inadequate consideration of the speciﬁc applications where the devices are used. The diverse nature of power electronics does not allow the use of generic power semiconductor devices in all applications as it leads to nonoptimal systems. Therefore, the devices and circuits need to be optimized at the application level. Softswitching topologies offer numerous advantages over conventional hardswitching applications such as reduced switching stress and EMI, and higher switching speed at reduced power loss. The IGBTs behave dissimilarly in the two circuit conditions. As a result, devices optimized for hard switching conditions do not necessarily give the best possible performance when used in soft switching circuits. In order to extract maximum system performance, it is necessary to develop IGBTs suited for speciﬁc applications. These optimized devices need to be manufacturable and cost effective in order to be commercially viable.
Further Reading 1. Adler, M. S., Owyang, K. W., Baliga, B. J., and Kokosa, R. A., “The evolution of power device technology,” IEEE Trans. Electron. Devices ED31: 1570–1591 (1984). 2. Akagi, H., “The stateoftheart of power electronics in Japan,” IEEE Trans. Power Electron. 13: 345–356 (1998). 3. Baliga, B. J., Adler, M. S., Love, R. P., Gray, P. V., and Zommer, N., “The insulated gate transistor: a new threeterminal MOS controlled bipolar power device,” IEEE Trans. Electron. Devices ED31: 821–828 (1984). 4. Baliga B. J., Power Semiconductor Devices, PWS Publishing, Boston, MA, 1996. 5. Blaabjerg, F. and Pedersen, J. K., “An optimum drive and clamp circuit design with controlled switching for a snubberless PWMVSIIGBT inverterleg,” in IEEE Power Electronics Specialists Conference Records, pp. 289–297, 1992.
87 6. Chokhawala, R. and Castino, G., “IGBT fault current limiting circuits,” in IEEE Industry Applications Society Annual Meeting Records, pp. 1339–1345, 1993. 7. Clemente, S. et al., IGBT Characteristics, IR Applications note AN983A. 8. Divan, D. M. and Skibinski, G., “Zeroswitchingloss inverters for high power applications,” IEEE Trans. Industry Applications 25: 634–643 (1989). 9. Elasser, A., Parthasarathy, V., and Torrey, D., “A study of the internal device dynamics of punchthrough and non punchthrough IGBTs under zerocurrent switching,” IEEE Trans. Power Electron. 12: 21–35 (1997). 10. Ghandi, S. K., Semiconductor Power Devices, John Wiley & Sons, NY, 1977. 11. Hefner, A. R., “An improved understanding for the transient operation of the insulated gate bipolar transistor (IGBT),” IEEE Trans. Power Electron. 5: 459–468 (1990). 12. Hefner, A. R. and Blackburn, D. L., “An analytical model for the steadystate and transient characteristics of the power insulated gate bipolar transistor,” SolidState Electron. 31: 1513–1532 (1988). 13. Hefner, A. R., “An investigation of the drive circuit requirements for the power insulated gate bipolar transistor (IGBT),” IEEE Trans. Power Electron. 6: 208–219 (1991). 14. Jahns, T.M. “Designing intelligent muscle into industrial motion control,” in Industrial Electronics Conference Records, pp. 1–14, 1989. 15. John, V., Suh, B. S., and Lipo, T. A., “Fast clamped short circuit protection of IGBTs,” in IEEE Applied Power Electronics Conference Records, pp. 724–730, 1998. 16. Kassakian, J. G., Schlecht, M. F., and Verghese, G. C., Principles of Power Electronics, Addison Wesley, Reading, MA, 1991. 17. Kraus, R. and Hoffman, K., “An analytical model of IGBTs with low emitter efﬁciency,” in ISPSD’93, pp. 30–34. 18. Lee, H. G., Lee, Y. H., Suh, B. S., and Lee, J. W., “A new intelligent gate control scheme to drive and protect high power IGBTs,” in European Power Electronics Conference Records, pp. 1.400–1.405, 1997. 19. Licitra, C., Musumeci, S., Raciti, A., Galluzzo, A. U., and Letor, R., “A new driving circuit for IGBT devices,” IEEE Trans. Power Electron. 10: 373–378 (1995). 20. McMurray, W., “Resonant snubbers with auxiliary switches,” IEEE Trans. Industry Applications 29: 355–362 (1993). 21. Mohan, N., Undeland, T., and Robbins, W., Power Electronics – Design, Converters and Applications, John Wiley & Sons, NY, 1996. 22. Penharkar, S. and Shenai, K., “Zero voltage switching behavior of punchthrough and nonpunchthrough insulated gate bipolar transistors (IGBTs),” IEEE Trans. Electron. Devices 45: 1826–1835 (1998). 23. Powerex IGBTMOD and intellimod – Intelligent Power Modules Applications and Technical Data Book, 1994. 24. Sze, S. M., Physics of Semiconductor Devices, John Wiley & Sons, NY, 1981. 25. Sze, S. M., Modern Semiconductor Device Physics, John Wiley & Sons, NY, 1998. 26. Trivedi, M., Pendharkar, S., and Shenai, K., “Switching charcteristics of IGBTs and MCTs in power converters,” IEEE Trans. Electron. Devices 43: 1994–2003 (1996). 27. Trivedi, M. and Shenai, K., “Modeling the turnoff of IGBTs in hardand softswitching applications,” IEEE Trans. Electron. Devices 44: 887–893 (1997).
88 28. Trivedi, M. and Shenai, K., “Internal dynamics of IGBT under zerovoltage and zerocurrent switching conditions,” IEEE Trans. Electron. Devices 46: 1274–1282 (1999). 29. Trivedi, M. and Shenai, K., “Failure mechanisms of IGBTs under shortcircuit and clamped inductive switching stress,” IEEE Trans. Power Electron. 14: 108–116 (1999). 30. Undeland, T., Jenset, F., Steinbakk, A., Ronge, T., and Hernes, M., “A snubber conﬁguration for both power transistor and GTO PWM inverters,” in IEEE Power Electronics Specialists Conference Records, pp. 42–53, 1984.
S. Abedinpour and K. Shenai 31. Venkatesan, V., Eshaghi, M., Borras, R., and Deuty, S., “IGBT turnoff characteristics explained through measurements and device simulation,” in IEEE Applied Power Electronics Conference Records, pp. 175–178, 1997. 32. Widjaja, I., Kurnia, A., Shenai, K., and Divan, D., “Switching dynamics of IGBTs in softswitching converters,” IEEE Trans. Electron. Devices 42: 445–454 (1995).
6 Thyristors Angus Bryant, Ph.D. Department of Engineering, University of Warwick, Coventry CV4 7AL, UK
Enrico Santi, Ph.D. Department of Electrical Engineering, University of South Carolina, Columbia, South Carolina, USA
Jerry Hudgins, Ph.D. Department of Electrical Engineering, University of Nebraska, Lincoln, Nebraska, USA
Patrick Palmer, Ph.D. Department of Engineering, University of Cambridge, Trumpington Street, Cambridge CB2 1PZ, UK
6.1 Introduction .......................................................................................... 89 6.2 Basic Structure and Operation................................................................... 90 6.3 Static Characteristics ............................................................................... 92 6.3.1 Current–Voltage Curves for Thyristors • 6.3.2 Edge and Surface Terminations • 6.3.3 Packaging
6.4 Dynamic Switching Characteristics............................................................. 95 6.4.1 Cathode Shorts • 6.4.2 Anode Shorts • 6.4.3 Amplifying Gate • 6.4.4 Temperature Dependencies
6.5 Thyristor Parameters ............................................................................... 99 6.6 Types of Thyristors ................................................................................. 101 6.6.1 SCRs and GTOs • 6.6.2 MOScontrolled Thyristors • 6.6.3 Static Induction Thyristors • 6.6.4 Optically Triggered Thyristors • 6.6.5 Bidirectional Thyristors
6.7 Gate Drive Requirements ......................................................................... 106 6.7.1 Snubber Circuits • 6.7.2 Gate Circuits
6.8 PSpice Model ......................................................................................... 109 6.9 Applications........................................................................................... 110 6.9.1 DC–AC Utility Inverters • 6.9.2 Motor Control • 6.9.3 VAR Compensators and Static Switching Systems • 6.9.4 Lighting Control Circuits
Further Reading ..................................................................................... 114
6.1 Introduction Thyristors are usually threeterminal devices that have four layers of alternating ptype and ntype material (i.e. three p–n junctions) comprising its main power handling section. In contrast to the linear relation which exists between load and control currents in a transistor, the thyristor is bistable. The control terminal of the thyristor, called the gate (G) electrode, may be connected to an integrated and complex structure as a part of the device. The other two terminals, called the anode (A) and cathode (K), handle the large applied potentials (often of both polarities) and conduct the major current through the thyristor. The anode and cathode terminals are connected in series with the load to which power is to be controlled. Thyristors are used to approximate ideal closed (no voltage drop between anode and cathode) or open (no anode current ﬂow) switches for control of power ﬂow in a circuit. This differs from lowlevel digital switching circuits that are designed to deliver two distinct small voltage levels while conducting small currents (ideally zero). Thyristor circuits must have the capability of delivering large currents and be able Copyright © 2007, 2001, Elsevier Inc. All rights reserved.
to withstand large externally applied voltages. All thyristor types are controllable in switching from a forwardblocking state (positive potential applied to the anode with respect to the cathode, with correspondingly little anode current ﬂow) into a forwardconduction state (large forward anode current ﬂowing, with a small anode–cathode potential drop). Most thyristors have the characteristic that after switching from a forwardblocking state into the forwardconduction state, the gate signal can be removed and the thyristor will remain in its forwardconduction mode. This property is termed “latching” and is an important distinction between thyristors and other types of power electronic devices. Some thyristors are also controllable in switching from forwardconduction back to a forwardblocking state. The particular design of a thyristor will determine its controllability and often its application. Thyristors are typically used at the highest energy levels in power conditioning circuits because they are designed to handle the largest currents and voltages of any device technology (systems approximately with voltages above 1 kV or currents above 100 A). Many mediumpower circuits (systems operating at less than 1 kV or 100 A) and particularly 89
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lowpower circuits (systems operating below 100 V or several amperes) generally make use of power bipolar transistors, power metal oxide semiconductor ﬁeld effect transistors (MOSFETs) or insulated gate bipolar transistors (IGBTs) as the main switching elements because of the relative ease in controlling them. IGBT technology, however, continues to improve and multiple silicon die are commonly packaged together in a module. These modules are replacing thyristors in applications operating up to 3 kV that require controllable turnoff because of easier gatedrive requirements. Power diodes are used throughout all levels of power conditioning circuits and systems for component protection and wave shaping. A thyristor used in some ac power circuits (50 or 60 Hz in commercial utilities or 400 Hz in aircraft) to control ac power ﬂow can be made to optimize internal power loss at the expense of switching speed. These thyristors are called phasecontrol devices, because they are generally turned from a forwardblocking into a forwardconducting state at some speciﬁed phase angle of the applied sinusoidal anode–cathode voltage waveform. A second class of thyristors is used in association with dc sources or in converting ac power at one amplitude and frequency into ac power at another amplitude and frequency, and must generally switch on and off relatively quickly. A typical application for the second class of thyristors is in converting a dc voltage or current into an ac voltage or current. A circuit that performs this operation is often called an inverter, and the associated thyristors used are referred to as inverter thyristors. There are four major types of thyristors: (i) the siliconcontrolled rectiﬁer (SCR); (ii) the gate turnoff thyristor (GTO) and its close relative the integrated gate commutated thyristor (IGCT); (iii) the MOScontrolled thyristor (MCT) and its various forms; and (iv) the static induction thyristor (SITh). MCTs are sonamed because many parallel enhancement mode, MOSFET structures of one charge type are integrated into the thyristor for turnon and many more MOSFETs of the other charge type are integrated into the thyristor for turnoff. A SITh or ﬁeldcontrolled thyristor (FCTh), has essentially the same construction as a power diode with a gate structure that can pinchoff anode current ﬂow. Although MCTs, derivative forms of the MCT and SIThs have the advantage of being essentially voltagecontrolled devices (i.e. little control current is required for turnon or turnoff, and therefore require simpliﬁed control circuits attached to the gate electrode), they are currently only found in niche applications such as pulse power. Detailed discussion of variations of MCTs and SIThs, as well as additional references on these devices are discussed by Hudgins in [1]. Other types of thyristors include the Triac (a pair of antiparallel SCRs integrated together to form a bidirectional current switch) and the programmable unijunction transistor (PUT). The SCRs and GTOs are designed to operate at all power levels. These devices are primarily controlled using electrical
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signals (current), though some types are made to be controlled using optical energy (photons) for turnon. Subclasses of SCRs and GTOs are reverse conducting types and symmetric structures that block applied potentials in the reverse and forward polarities. Other variations of GTOs are the gatecommutated turnoff thyristor (GCT), commonly available as the IGCT, and the bidirectional controlled thyristor (BCT). Most power converter circuits incorporating thyristors make use of SCRs, GTOs, or IGCTs, and hence the chapter will focus on these devices, though the basics of operation are applicable to all thyristor types. All power electronic devices must be derated (e.g. power dissipation levels, current conduction, voltage blocking, and switching frequency must be reduced), when operating above room temperature (deﬁned as approximately 25◦ C). Bipolartype devices have thermal runaway problems, in that if allowed to conduct unlimited current, these devices will heat up internally causing more current to ﬂow, thus generating more heat, and so forth until destruction. Devices that exhibit this behavior are pin diodes, bipolar transistors, and thyristors. Almost all power semiconductor devices are made from silicon (Si). Research and development continues in developing other types of devices in silicon carbide (SiC), gallium nitride (GaN), and related material systems. However, the physical description and general behavior of thyristors is unimportant to the semiconductor material system used, though the discussion and any numbers cited in the chapter will be associated with Si devices.
6.2 Basic Structure and Operation Figure 6.1 shows a conceptual view of a typical thyristor with the three p–n junctions and the external electrodes labeled. Also shown in the ﬁgure is the thyristor circuit symbol used in electrical schematics.
Anode(A) A pemitter
p J1
n−
nbase pbase nemitter
G
J2 J3
p K n+
Cathode (K)
Gate (G)
FIGURE 6.1 Simple cross section of a typical thyristor and the associated electrical schematic symbols.
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A highresistivity region, nbase, is present in all thyristors. It is this region, the nbase and associated junction, J2 of Fig. 6.1, which must support the large applied forward voltages that occur when the switch is in its off or forwardblocking state (nonconducting). The nbase is typically doped with impurity phosphorous atoms at a concentration of 1013 to 1014 cm−3 . The nbase can be tens to hundreds of micrometer thick to support large voltages. Highvoltage thyristors are generally made by diffusing aluminum or gallium into both surfaces to create pdoped regions forming deep junctions with the nbase. The doping proﬁle of the pregions ranges from about 1015 to 1017 cm−3 . These pregions can be up to tens of micrometer thick. The cathode region (typically only a few micrometer thick) is formed by using phosphorous atoms at a doping density of 1017 to 1018 cm−3 . The higher the forwardblocking voltage rating of the thyristor, the thicker the nbase region must be. However, increasing the thickness of this highresistivity region results in slower turnon and turnoff (i.e. longer switching times and/or lower frequency of switching cycles because of more stored charge during conduction). For example, a device rated for a forwardblocking voltage of 1 kV will, by its physical construction, switch much more slowly than one rated for 100 V. In addition, the thicker highresistivity region of the 1 kV device will cause a larger forward voltage drop during conduction than the 100 V device carrying the same current. Impurity atoms, such as platinum or gold, or electron irradiation are used to create chargecarrier recombination sites in the thyristor. The large number of recombination sites reduces the mean carrier lifetime (average time that an electron or hole moves through the Si before recombining with its opposite chargecarrier type). A reduced carrier lifetime shortens the switching times (in particular the turnoff or recovery time) at the expense of increasing the forwardconduction drop. There are other effects associated with the relative thickness and layout of the various regions that make up modern thyristors, but the major tradeoff between forwardblocking voltage rating and switching times, and between forwardblocking voltage rating and forwardvoltage drop during conduction should be kept in mind. (In signallevel electronics an analogous tradeoff appears as a lowering of ampliﬁcation (gain) to achieve higher operating frequencies, and is often referred to as the gainbandwidth product.) Operation of thyristors is as follows. When a positive voltage is applied to the anode (with respect to cathode), the thyristor is in its forwardblocking state. The center junction, J2 (see Fig. 6.1) is reverse biased. In this operating mode the gate current is held to zero (open circuit). In practice, the gate electrode is biased to a small negative voltage (with respect to the cathode) to reverse bias the GKjunction J3 and prevent chargecarriers from being injected into the pbase. In this condition only thermally generated leakage current ﬂows through the device and can often be approximated as zero in value (the actual value of the leakage current is typically many orders of
magnitude lower than the conducted current in the onstate). As long as the forward applied voltage does not exceed the value necessary to cause excessive carrier multiplication in the depletion region around J2 (avalanche breakdown), the thyristor remains in an offstate (forwardblocking). If the applied voltage exceeds the maximum forwardblocking voltage of the thyristor, it will switch to its onstate. However, this mode of turnon causes nonuniformity in the current ﬂow, is generally destructive, and should be avoided. When a positive gate current is injected into the device, J3 becomes forward biased and electrons are injected from the nemitter into the pbase. Some of these electrons diffuse across the pbase and get collected in the nbase. This collected charge causes a change in the bias condition of J1 . The change in bias of J1 causes holes to be injected from the pemitter into the nbase. These holes diffuse across the nbase and are collected in the pbase. The addition of these collected holes in the pbase acts the same as gate current. The entire process is regenerative and will cause the increase in charge carriers until J2 also becomes forward biased and the thyristor is latched in its onstate (forwardconduction). The regenerative action will take place as long as the gate current is applied in sufﬁcient amount and for a sufﬁcient length of time. This mode of turnon is considered to be the desired one as it is controlled by the gate signal. This switching behavior can also be explained in terms of the twotransistor analog shown in Fig. 6.2. The two transistors are regeneratively coupled so that if the sum of their forward current gains (α’s) exceeds unity, each drives the other into saturation. Equation 6.1 describes the condition necessary for the thyristor to move from a forwardblocking state into the forwardconduction state. The forward current gain (expressed as the ratio of collector current to emitter current) of the pnp transistor is denoted by αp , and that of the npn as αn . The α’s are current dependent and increase slightly as the current increases. The center junction J2 is reverse biased under forward applied voltage (positive, vAK ). The associated electric ﬁeld in the depletion region around the junction can result
iA
A A iA
p n
n
p
p
n
G
G
iG
iG K
K
FIGURE 6.2 Twotransistor behavioral model of a thyristor.
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in signiﬁcant carrier multiplication, denoted as a multiplying factor M on the current components, Ico and iG . iA =
MIco + M αn iG 1 − M (αn + αp )
openbase, causing thyristor turnoff. This is similar in principle to use negative base current to quickly turnoff a traditional bipolar transistor.
(6.1)
In the forwardblocking state, the leakage current Ico is small, both α’s are small, and their sum is less than unity. Gate current increases the current in both transistors, increasing their α’s. Collector current in the npn transistor acts as base current for the pnp, and analogously, the collector current of the pnp acts as base current driving the npn transistor. When the sum of the two α’s equals unity, the thyristor switches to its onstate (latches). This condition can also be reached, without any gate current, by increasing the forward applied voltage so that carrier multiplication (M >> 1) at J2 increases the internal leakage current, thus increasing the two α’s. A third way to increase the α’s exists by increasing the device (junction) temperature. Increasing the temperature causes a corresponding increase in the leakage current Ico to the point where latching can occur. The typical manifestation of this temperature dependence is to cause an effective lowering of the maximum blocking voltage that can be sustained by the thyristor. Another way to cause a thyristor to switch from forwardblocking to forwardconduction exists. Under a forward applied voltage, J2 is reverse biased while the other two junctions are forwardbiased in the blocking mode. The reversebiased junction of J2 is the dominant capacitance of the three and determines the displacement current that ﬂows. If the rate of increase in the applied vAK (dvAK /dt) is sufﬁcient, it will cause a signiﬁcant displacement current through the J2 capacitance. This displacement current can initiate switching similar to an externally applied gate current. This dynamic phenomenon is inherent in all thyristors and causes there to be a limit (dv/dt) to the time rate of applied vAK that can be placed on the device to avoid uncontrolled switching. Alterations to the basic thyristor structure can be produced that increase the dv/dt limit and will be discussed in Section 6.4. Once the thyristor has moved into forwardconduction, any applied gate current is superﬂuous. The thyristor is latched and, for SCRs, cannot be returned to a blocking mode by using the gate terminal. Anode current must be commutated away from the SCR for a sufﬁcient time to allow stored charge in the device to recombine. Only after this recovery time has occurred, can a forward voltage be reapplied (below the dv/dt limit of course) and the SCR again be operated in a forwardblocking mode. If the forward voltage is reapplied before sufﬁcient recovery time has elapsed, the SCR will move back into forwardconduction. For GTOs and IGCTs, a large applied reverse gate current (typically in the range of 10–50% of the anode current for GTOs, and 100% of the anode current for IGCTs) applied for a sufﬁcient time can remove enough charge near the GK junction to cause it to turnoff. This interrupts the base current to the pnp transistor, leaving the pnp
6.3 Static Characteristics 6.3.1 Current–Voltage Curves for Thyristors A plot of the anode current (iA ) as a function of anode–cathode voltage (vAK ) is shown in Fig. 6.3. The forwardblocking mode is shown as the lowcurrent portion of the graph (solid curve around operating point “1”). With zero gate current and positive vAK , the forward characteristic in the off or blockingstate is determined by the center junction J2 , which is reverse biased. At operating point “1” very little current ﬂows (Ico only) through the device. However, if the applied voltage exceeds the forwardblocking voltage, the thyristor switches to its onor conductingstate (shown as operating point “2”) because of carrier multiplication (M in Eq. (6.1)). The effect of gate current is to lower the blocking voltage at which switching takes place. The thyristor moves rapidly along the negativelysloped portion of the curve until it reaches a stable operating point determined by the external circuit (point “2”). The portion of the graph indicating forwardconduction shows the large values of iA that may be conducted at relatively low values of vAK , similar to a power diode. As the thyristor moves from forwardblocking to forwardconduction, the external circuit must allow sufﬁcient anode current to ﬂow to keep the device latched. The minimum anode current that will cause the device to remain in forwardconduction as it switches from forwardblocking is called the
iA
2
IL VRBD
3
IH
IG2 > IG1 IG2
IG1
IG=0
1 VFBD
VAK
FIGURE 6.3 Static characteristic i–v curve typical of thyristors.
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latching current IL . If the thyristor is already in forwardconduction and the anode current is reduced, the device can move its operating mode from forwardconduction back to forwardblocking. The minimum value of anode current necessary to keep the device in forwardconduction after it has been operating at a high anode current value is called the holding current IH . The holding current value is lower than the latching current value as indicated in Fig. 6.3. The reverse thyristor characteristic, quadrant III of Fig. 6.3, is determined by the outer two junctions (J1 and J3 ), which are reverse biased in this operating mode (applied vAK is negative). Symmetric thyristors are designed so that J1 will reach reverse breakdown due to carrier multiplication at an applied reverse potential near the forward breakdown value (operating point “3” in Fig. 6.3). The forward and reverseblocking junctions are usually fabricated at the same time with a very long diffusion process (10–50 h) at high temperatures (>1200◦ C). This process produces symmetric blocking properties. Wafer edge termination processing causes the forwardblocking capability to be reduced to about 90% of the reverseblocking capability. Edge termination is discussed below. Asymmetric devices are made to optimize forwardconduction and turnoff properties, and as such reach reverse breakdown at a lower voltage than that applied in the forward direction. This is accomplished by designing the asymmetric thyristor with a much thinner nbase than is used in symmetric structures. The thin nbase leads to improved properties such as lower forward drop and shorter switching times. Asymmetric devices are generally used in applications when only forward voltages (positive, vAK ) are to be applied (including many inverter designs). The form of the gatetocathode i–v characteristic of SCRs, GTOs and IGCTs is similar to that of a diode. With positive gate bias, the gate–cathode junction is forward biased and permits the ﬂow of a large current in the presence of a low voltage drop. When negative gate voltage is applied to an SCR, the gate–cathode junction is reverse biased and prevents the ﬂow of current until the avalanche breakdown voltage is reached. In a GTO or IGCT, a negative gate voltage is applied to provide a low impedance path for anode current to ﬂow out of the device instead of out the cathode. In this way the cathode region (base–emitter junction of the equivalent npn transistor) turns off, thus pulling the equivalent npn transistor out of conduction. This causes the entire thyristor to return to its blocking state. The problem with the GTO and IGCT is that the gatedrive circuitry is typically required to sink 10–50% (for the GTO) or 100% (for the IGCT) of the anode current to achieve turnoff.
6.3.2 Edge and Surface Terminations Thyristors are often made with planar diffusion technology to create the cathode region. Formation of these regions creates cylindrical curvature of the metallurgical
gate–cathode junction. Under reverse bias, the curvature of the associated depletion region results in electric ﬁeld crowding along the curved section of the p+ diffused region. The ﬁeld crowding seriously reduces the breakdown potential below that expected for the bulk semiconductor. A ﬂoating ﬁeld ring, an extra p diffused region with no electrical connection at the surface, is often added to modify the electric ﬁeld proﬁle and thus reduce it to a value below or at the ﬁeld strength in the bulk. An illustration of a single ﬂoating ﬁeld ring is shown in Fig. 6.4. The spacing, W, between the main anode region and the ﬁeld ring is critical. Multiple rings can also be employed to further modify the electric ﬁeld in highvoltage rated thyristors. Another common method for altering the electric ﬁeld at the surface is by using a ﬁeld plate as shown in cross section in Fig. 6.5. By forcing the potential over the oxide to be the same as at the surface of the p+ region, the depletion region can be extended so that the electric ﬁeld intensity is reduced near the curved portion of the diffused p+ region. A common practice is to use ﬁeld plates with ﬂoating ﬁeld rings to obtain optimum breakdown performance. Highvoltage thyristors are made from single wafers of Si and must have edge terminations other than ﬂoating ﬁeld rings or ﬁeld plates to promote bulk breakdown and limit leakage
Si 2 SiO
p+
Si 2 SiO
p
W
n−
FIGURE 6.4 Cross section showing a ﬂoating ﬁeld ring to decrease the electric ﬁeld intensity near the curved portion of the main anode region (leftmost p+ region).
A SiO2 +
p
depletion boundary n−
FIGURE 6.5 Cross section showing a ﬁeld plate used to reduce the electric ﬁeld intensity near the curved portion of the p+ region (anode).
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p
FIGURE 6.6 Cross section of a thyristor showing the negative bevel (upper p–n− and p–n+ junctions) and positive bevel (lower p–n− junction) used for edge termination of largearea devices.
current at the surface. Controlled bevel angles can be created using lapping and polishing techniques during production of largearea thyristors. Two types of bevel junctions can be created: (i) a positive bevel deﬁned as one in which the junction area decreases when moving from the highlydoped to the lightlydoped side of the depletion region and (ii) a negative bevel deﬁned as one in which the junction area increases when moving from the highlydoped to the lightlydoped side of the depletion region. In practice, the negative bevel must be lapped at an extremely shallow angle to reduce the surface ﬁeld below the ﬁeld intensity in the bulk. All positive bevel angles between 0 and 90◦ result in a lower surface ﬁeld than in the bulk. Figure 6.6 shows the use of a positive bevel for the J1 junction and a shallow negative bevel for the J2 and J3 junctions on a thyristor cross section to make maximum use of the Si area for conduction and still reduce the surface electric ﬁeld. Further details of the use of beveling, ﬁeld plates, and ﬁeld rings can be found in Ghandi [2] and Baliga [3].
6.3.3 Packaging Thyristors are available in a wide variety of packages, from small plastic ones for lowpower (i.e. TO247), to studmount
packages for mediumpower, to presspack (also called ﬂatpack) for the highest power devices. The presspacks must be mounted under pressure to obtain proper electrical and thermal contact between the device and the external metal electrodes. Special forcecalibrated clamps are made for this purpose. Largearea thyristors cannot be directly attached to the large copper pole piece of the presspack because of the difference in the coefﬁcient of thermal expansion (CTE), hence the use of a pressure contact for both anode and cathode. Figure 6.7 shows typical thyristor studmount and presspack packages. Many medium power thyristors are appearing in modules where a half or fullbridge (and associated antiparallel diodes) is put together in one package. A power module package should have ﬁve characteristics: i) electrical isolation of the baseplate from the semiconductor; ii) good thermal performance; iii) good electrical performance; iv) long life/high reliability; and v) low cost. Electrical isolation of the baseplate from the semiconductor is necessary in order to contain both halves of a phase leg in one package as well as for convenience (modules switching different phases can be mounted on one heatsink) and safety (heatsinks can be held at ground potential). Thermal performance is measured by the maximum temperature rise in the Si die at a given power dissipation level with a ﬁxed heat sink temperature. The lower the die temperature, the better the package. A package with a low thermal resistance from junctiontosink can operate at higher power densities for the same temperature rise or lower temperatures for the same power dissipation than a more thermally resistive package. While maintaining low device temperature is generally preferable, temperature variation affects majority carrier and bipolar devices differently. Roughly speaking, in a bipolar device such as a thyristor, switching losses increase and
FIGURE 6.7 Examples of thyristor packaging: studmount (left) and presspack/capsule (right).
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TABLE 6.1
Thermal conductivity of thyristor package materials
Material
Thermal conductivity (W/m·K) at 300 K
Silicon Copper (baseplate and pole pieces) AlN substrate Al2 O3 (Alumina) Aluminum (Al) Tungsten (W) Molybdenum (Mo) Metal matrix composites (MMC) Thermal grease (heatsink compound) 60/40 solder (Pb/Sn eutectic) 95/5 solder (Pb/Sn high temperature)
150 390–400 170 28 220 167 138 170 0.75 50 35
conduction losses decrease with increasing temperature. In a majority carrier device, such as a MOSFET, conduction losses increase with increasing temperature. The thermal conductivity of typical materials used in thyristor packages is shown in Table 6.1. Electrical performance refers primarily to the stray inductance in series with the die, as well as the capability of mounting a lowinductance bus to the terminals. Another problem is the minimization of capacitive crosstalk from one switch to another, which can cause an abnormal onstate condition by charging the gate of an offstate switch, or from a switch to any circuitry in the package (as would be found in a hybrid power module). Capacitive coupling is a major cause of electromagnetic interference (EMI). As the stray inductance of the module and the bus sets a minimum switching loss for the device – because the switch must absorb the stored inductive energy – it is very important to minimize inductance within the module. Reducing the parasitic inductance reduces the highfrequency ringing during transients that is another cause of radiated electromagnetic interference. Since stray inductance can cause large peak voltages during switching transients, minimizing it helps to maintain the device within its safe area of operation. Long life and high reliability are primarily attained through minimization of thermal cycling, minimization of ambient temperature, and proper design of the transistor stack. Thermal cycling fatigues material interfaces because of coefﬁcient of thermal expansion (CTE) mismatch between dissimilar materials. As the materials undergo temperature variation, they expand and contract at different rates which stresses the interface between the layers and can cause interface deterioration (e.g. cracking of solder layers or wire debonding). Chemical degradation processes such as dendrite growth and impurity migration are accelerated with increasing temperature, so keeping the absolute temperature of the device low, as well as minimizing the temperature changes to which it is subjected is important. Typical CTE values for common package materials are given in Table 6.2.
TABLE 6.2 CTE for thyristor package materials Material
CTE (mm/m·K) at 300 K
Silicon Copper (baseplate and pole pieces) AlN substrate Al2 O3 (Alumina) Tungsten (W) Molybdenum (Mo) Aluminum (Al) Metal matrix composites (MMC) 60/40 solder (Pb/Sn eutectic)
4.1 17 4.5 6.5 4.6 4.9 23 5–20 25
Low cost is achieved in a variety of ways. Both manufacturing and material costs must be taken into account when designing a power module. Materials that are difﬁcult to machine or process, even if they are relatively cheap in raw form (molybdenum, for example), should be avoided. Manufacturing processes that lower yield also drive up costs. In addition, a part that is very reliable can reduce future costs by reducing the need for repair and replacement. The basic halfbridge module has three power terminals: plus, minus and phase. Advanced modules differ from traditional high power commercial modules in several ways. The baseplate is metallized aluminum nitride (AlN) ceramic rather than the typical 0.125” thick nickelplated copper baseplate with a soldered metallized ceramic substrate for electrical isolation. This AlN baseplate stack provides a low thermal resistance from die to heatsink. The copper terminal power busses are attached by solder to the devices in a wirebondfree, lowinductance, lowresistance, device interconnect conﬁguration. The balance of the assembly is typical for module manufacturing with attachment of shells, use of dielectric gels, and hard epoxies and adhesive to seal the ﬁnished module. Details of the thermal performance of modules and advanced modules can be found in Beker et al. [4] and Godbold et al. [5].
6.4 Dynamic Switching Characteristics The time rate of rise of anode current (di/dt) during turnon and the time rate of rise of anode–cathode voltage (dv/dt) during turnoff are important parameters to control for ensuring proper and reliable operation. All thyristors have maximum limits for di/dt and dv/dt that must not be exceeded. Devices capable of conducting large currents in the onstate, are necessarily made with large surface areas through which the current ﬂows. During turnon, localized areas of a device (near the gate region) begin to conduct current. The initial turnon of an SCR is shown in Fig. 6.8. The cross section illustrates how injected gate current ﬂows to the nearest cathode region, causing this portion of the npn transistor to begin conducting. The pnp transistor then follows the npn into conduction such that anode current begins ﬂowing only in a small portion of the
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Top view
Gate metallization
Cathode metallization
G
K Cathode metallization
Gate metallization
n+ p
Crosssectional view Anode metallization
n− p+
A
FIGURE 6.8 Top view and associated cross section of gate–cathode periphery showing initial turnon region in a centerﬁred thyristor.
cathode region. If the local current density becomes too large (in excess of several thousand amperes per square centimeter), then selfheating will damage the device. Sufﬁcient time (referred to as plasma spreading time) must be allowed for the entire cathode area to begin conducting before the localized currents become too high. This phenomenon results in a maximum allowable rate of rise of anode current in a thyristor and is referred to as a di/dt limit. In many highfrequency
applications, the entire cathode region is never fully in conduction. Prevention of di/dt failure can be accomplished if the rate of increase of conduction area exceeds the di/dt rate such that the internal junction temperature does not exceed a speciﬁed critical temperature (typically approximately 350◦ C). This critical temperature decreases as the blocking voltage increases. Adding series inductance to the thyristor to limit di/dt below its maximum usually causes circuit design problems. Another way to increase the di/dt rating of a device is to increase the amount of gate–cathode periphery. Inverter SCRs (sonamed because of their use in highfrequency power converter circuits that convert dc to ac, i.e. invert) are designed so that there is a large amount of gate edge adjacent to a signiﬁcant amount of cathode edge. A top surface view of two typical gate–cathode patterns, found in large thyristors, is shown in Fig. 6.9. An inverter SCR often has a stated maximum di/dt limit of approximately 2000 A/ms. This value has been shown to be conservative [6], and by using excessive gate current under certain operating conditions, an inverter SCR can be operated reliably at 10,000 A/ms–20,000 A/ms. A GTO takes the interdigitation of the gate and cathode to the extreme (Fig. 6.9, left). In Fig. 6.10 a cross section of a GTO shows the amount of interdigitation. A GTO often has cathode islands that are formed by etching the Si. A metal plate can be placed on the top to connect the individual cathodes into a large arrangement of electrically parallel cathodes. The gate metallization is placed so that the gate surrounding each cathode is electrically in parallel as well. This construction not only allows high di/dt values to be reached, as in an inverter SCR, but also provides the capability to turnoff the anode current by shunting it away from the individual cathodes and out of the gate electrode upon reverse biasing of the gate. During turnoff, current is decreasing while voltage across the device is increasing. If the forward voltage becomes too high while sufﬁcient current is still ﬂowing, then the device will drop back into its conduction mode instead of completing its turnoff cycle. Also, during turnoff, the power dissipation can
FIGURE 6.9 Top view of typical interdigitated gate–cathode patterns used for thyristors.
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Thyristors n+
n+
A
n+
p
αp n− αn
p+
G
Rs
FIGURE 6.10 Cross section of a GTO showing the cathode islands and interdigitation with the gate (pbase).
become excessive if the current and voltage are simultaneously too large. Both of these turnoff problems can damage the device as well as other portions of the circuit. Another switching problem that occurs is associated primarily with thyristors, though other power electronic devices suffer some degradation of performance from the same problem. This problem is that thyristors can selftrigger into a forwardconduction mode from a forwardblocking mode if the rate of rise of forward anode–cathode voltage is too large. This triggering method is due to displacement current through the associated junction capacitances (the capacitance at J2 dominates because it is reverse biased under forward applied voltage). The displacement current contributes to the leakage current Ico , shown in Eq. (6.1). The SCRs, GTOs and IGCTs, therefore, have a maximum dv/dt rating that should not be exceeded (typical values are 100–1000 V/ms). Switching into a reverseconducting from a reverseblocking state, due to an applied reverse dv/dt, is not possible because the values of the reverse α’s of the equivalent transistors can never be made large enough to cause the necessary feedback (latching) effect. An external capacitor is often placed between the anode and cathode of the thyristor to help control the dv/dt experienced. Capacitors and other components that are used to form such protection circuits, known as snubbers, may be found in all power semiconductor devices.
6.4.1 Cathode Shorts As the temperature in the thyristor increases above 25◦ C, the minority carrier lifetime and the corresponding diffusion lengths in the n and pbases increase. This leads to an increase in the α’s of the equivalent transistors. Discussion of the details of the minority carrier diffusion length and its role in determining the current gain factor α can be found in Sze [7]. Referring to Eq. (6.1), it is seen that a lower applied bias will give a carrier multiplication factor M sufﬁcient to switch the device from forwardblocking into conduction, because of this increase of the α’s with increasing temperature. Placing a shunt resistor in parallel with the base–emitter junction of the equivalent npn transistor (shown in Fig. 6.11) will result in an effective current gain, αneff , that is lower than αn , as given by
K
FIGURE 6.11 Twotransistor equivalent circuit showing the addition of a resistive shunt path for anode current.
K
G
n+
n+
n+
p
n− p+
A
FIGURE 6.12 Cross section showing cathode shorts and the resulting resistive shunt path for anode current.
Eq. (6.2), where vGK is the applied gate–cathode voltage, Rs is the equivalent lumped value for the distributed current shunting structure, and the remaining factors form the appropriate current factor based on the applied bias and characteristics of the gate–cathode junction. The shunt current path is implemented by providing intermittent shorts, called cathode shorts, between the pbase (gate) region and the n+ emitter (cathode) region in the thyristor as illustrated in Fig. 6.12. The lumped shunt resistance value is in the range of 1–15 as measured from gate to cathode. αneff = αn
1 1 + (vGK αn )/(Rs i0 exp(qvGK /kT ))
(6.2)
Low values of anode current (e.g. those associated with an increase in temperature under forwardblocking conditions) will ﬂow through the shunt path to the cathode contact, bypassing the n+ emitter and keeping the device out of its forwardconduction mode. As the anode current becomes
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large, the potential drop across the shunt resistance will be sufﬁcient to forward bias the gate–cathode junction, J3 , and bring the thyristor into forwardconduction. The cathode shorts also provide a path for displacement current to ﬂow without forward biasing J3 . The dv/dt rating of the thyristor is thus improved as well as the forwardblocking characteristics by using cathode shorts. However, the shorts do cause a lowering of cathode current handling capability because of the loss of some of the cathode area (n+ region) to the shorting pattern, an increase in the necessary gate current to obtain switching from forwardblocking to forwardconduction, and an increase in complexity of manufacturing of the thyristor. The loss of cathode area due to the shortingstructure is from 5 to 20%, depending on the type of thyristor. By careful design of the cathode short windows to the pbase, the holding current can be made lower than the latching current. This is important so that the thyristor will remain in forwardconduction when used with varying load impedances.
6.4.2 Anode Shorts A further increase in forwardblocking capability can be obtained by introducing anode shorts in addition to the cathode shorts. This reduces αp in a similar manner that cathode shorts reduce αn . An illustration of this is provided in Fig. 6.13. In this structure both J1 and J3 are shorted (anode and cathode shorts), so that the forwardblocking capability of the thyristor is completely determined by the avalanche breakdown characteristics of J2 . Anode shorts will result in the complete loss of reverseblocking capability and is only suitable for thyristors used in asymmetric circuit applications. Shorted cathode
p
n+
n+
n+
Gate
n+
n− n+ region p+
p+
p+
p+
Shorted anode
FIGURE 6.13 Cross section showing integrated cathode and anode shorts.
6.4.3 Amplifying Gate The cathodeshorting structure will reduce the gate sensitivity dramatically. To increase this sensitivity and yet retain the
Amplifying Pilotgate gate contact
Cathode contact n+
n+
n+
Main cathode areas Main IA
n+
3
1 p
2 Pilot IA
n− p+
Metal anode contact
FIGURE 6.14 Cross section showing the amplifying gate structure in a thyristor.
beneﬁts of the cathodeshorts, a structure called an amplifying gate (or regenerative gate) is used, as shown in Fig. 6.14 (and Fig. 6.9, right). When the gate current (1) is injected into the pbase through the pilotgate contact, electrons are injected into the pbase by the n+ emitter with a given emitter injection efﬁciency. These electrons traverse through the pbase (the time taken for this process is called the transit time) and accumulate near the depletion region. This negative charge accumulation leads to injection of holes from the anode. The device then turns on after a certain delay, dictated by the pbase transit time, and the pilot anode current (2) begins to ﬂow through a small region near the pilotgate contact as shown in Fig. 6.14. This ﬂow of pilot anode current corresponds to the initial sharp rise in the anode current waveform (phase I), as shown in Fig. 6.15. The device switching then goes into phase II, during which the anode current remains fairly constant, suggesting that the resistance of the region has reached its lower limit. This is due to the fact that the pilot anode current (2) takes a ﬁnite time to traverse through the pbase laterally and become the gate current for the main cathode area. The n+ emitters start to inject electrons which traverse the pbase vertically and after a certain ﬁnite time (transit time of the pbase) reach the depletion region. The total time taken by the lateral traversal of pilot anode current and the electron transit time across the pbase is the reason for observing this characteristic phase II interval. The width of the phase II interval is comparable to the switching delay, suggesting that the pbase transit time is of primary importance. Once the main cathode region turns on, the resistance of the device decreases and the anode current begins to rise again (transition from phase II to III). From this time onward in the switching cycle, the plasma spreading velocity will dictate the rate at which the conduction area will increase. The current density during phase I and II can be quite large, leading to a considerable increase in the local temperature and device failure. The detailed effect of the amplifying gate on the anode current rise will only be noticed
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Phase III IA1.93 kA/division Phase II 2 A/division
125°C (398K)
0
–125°C (148K) decreasing temperature (25°C steps)
VAK 500 V/division PhaseI 100 ns/division
FIGURE 6.15 Turnon waveforms showing the effect of the amplifying gate in the anode current rise.
at high levels of di/dt (in the range of 1000 A/ms), shown in Fig. 6.15. It can be concluded that the amplifying gate will increase gate sensitivity at the expense of some di/dt capability, as demonstrated by Sankaran [8]. This lowering of di/dt capability can be somewhat offset by an increase in gate–cathode interdigitation as previously discussed.
6.4.4 Temperature Dependencies The forwardblocking voltage of an SCR has been shown to be reduced from 1350 V at 25◦ C to 950 V at −175◦ C in a near linear fashion [8]. Above 25◦ C, the forwardblocking capability is again reduced, due to changes in the minority carrier lifetime which cause the leakage current to increase and the associated breakover voltage to decrease. Several dominant physical parameters associated with semiconductor devices are sensitive to temperature variations, causing their dependent device characteristics to change dramatically. The most important of these parameters are: (i) the minority carrier lifetimes (which control the highlevel injection lifetimes); (ii) the hole and electron mobilities; (iii) the impact ionization collision cross sections; and (iv) the freecarrier concentrations (primarily the ionized impurityatom concentration). Almost all of the impurity atoms are ionized at temperatures above 0◦ C, and so further discussion of the temperature effects on ionization is not relevant for normal operation. As the temperature increases above 25◦ C, the following trends are observed: the carrier lifetimes increase, giving longer recovery times and greater switching losses; the carrier mobilities are reduced, increasing the onstate voltage drop; and at very high temperatures, the intrinsic carrier concentration becomes sufﬁciently high that the depletion layer will not form and the device cannot switch off. A more detailed discussion of these physical parameters is beyond the scope of this article, but references are listed for those persons interested in pursuing relevant information about temperature effects.
GROUND 4 µs/division
FIGURE 6.16 Temperature effect on the anode current tail during turnoff.
It is well known that charge carrier recombination events are more efﬁcient at lower temperatures. This shows up as a larger potential drop during forwardconduction and a shorter recovery time during turnoff. A plot of the anode current during turnoff, at various temperatures, for a typical GTO is shown in Fig. 6.16. An approximate relation between the temperature and the forward drop across the nbase of a thyristor is discussed in detail by Herlet [10] and Hudgins et al. [11]. Temperature dependent equations relating the anode current density, JA and the applied anode–cathode voltage VAK are also given in Reference [11]; these include the junction potential drops in the device, the temperature dependence of the bandgap energy, and the nbase potential drop. Data from measurements at forward current densities of approximately 100 A/cm2 on a GTO rated for 1 kV symmetric blocking gives forward voltage drops of 1.7 V at –50◦ C and 1.8 V at 150◦ C.
6.5 Thyristor Parameters Understanding of a thyristor’s maximum ratings and electrical characteristics is required for proper application. Use of a manufacturer’s data sheet is essential for good design practice. Ratings are maximum or minimum values that set limits on device capability. A measure of device performance under speciﬁed operating conditions is a characteristic of the device. A summary of some of the maximum ratings which must be considered when choosing a thyristor for a given application is provided in Table 6.3. Thyristor types shown in parentheses indicate a maximum rating unique to that device. Both forward and reverse repetitive and nonrepetitive voltage ratings must be considered, and a properly rated device must be chosen so that the maximum voltage ratings are never exceeded. In most cases, either forward or reverse voltage
100 TABLE 6.3
A. Bryant et al. Thyristor maximum ratings speciﬁed by manufacturers
Symbol
Description
VRRM
Peak repetitive reverse voltage
VRSM
Peak nonrepetitive reverse voltage (transient)
VR(DC)
DC reverse blocking voltage
VDRM
Peak repetitive forward offstate voltage
VDSM
Peak nonrepetitive forward offstate voltage (transient)
VD(DC)
DC forwardblocking voltage
IT (RMS) , IF (RMS)
RMS forward onstate current
IT (AV ), IF (AV )
Average forward onstate current at speciﬁed case or junction temperature
ITSM , IF (TSM )
Peak onecycle surge onstate current (values speciﬁed at 60 and 50 Hz)
ITGQ (GTO)
Peak controllable current
I 2t
Nonrepetitive pulse overcurrent capability (t = 8.3 ms for a 60 Hz half cycle)
PT
Maximum power dissipation
di/dt
Critical rate of rise of onstate current at speciﬁed junction temperature, gate current and forwardblocking voltage
PGM (PFGM for GTO)
Peak gate power dissipation (forward)
PRGM (GTO)
Peak gate power dissipation (reverse)
PG(AV )
Average gate power dissipation
VFGM
Peak forward gate voltage
VRGM
Peak reverse gate voltage
IFGM
Peak forward gate current
IRGM (GTO)
Peak reverse gate current
TSTG
Storage temperature
Tj
Junction operating temperature
VRMS
Voltage isolation (modules)
transients in excess of the nonrepetitive maximum ratings result in destruction of the device. The maximum root mean square (RMS) or average current ratings given are usually those which cause the junction to reach its maximum rated temperature. Because the maximum current will depend upon the current waveform and upon thermal conditions external to the device, the rating is usually shown as a function of case temperature and conduction angle. The peak single halfcycle surgecurrent rating must be considered, and in applications where the thyristor must be protected from damage by overloads, a fuse with an I2 t rating smaller than the maximum rated value for the device must be used. Maximum ratings for both forward and reverse gate voltage, current and power also must not be exceeded. The maximum rated operating junction temperature TJ must not be exceeded, since device performance, in particular voltageblocking capability, will be degraded. Junction temperature cannot be measured directly but must be calculated
from a knowledge of steadystate thermal resistance R(J −C) , and the average power dissipation. For transients or surges, the transient thermal impedance (Z(J −C) ) curve must be used (provided in manufacturer’s data sheets). The maximum average power dissipation PT is related to the maximum rated operating junction temperature and the case temperature by the steadystate thermal resistance. In general, both the maximum dissipation and its derating with increasing case temperature are provided. The number and type of thyristor characteristics speciﬁed varies widely from one manufacturer to another. Some characteristics are given only as typical values of minima or maxima, while many characteristics are displayed graphically. Table 6.4 summarizes some of the typical characteristics provided as maximum values. The maximum value means that the manufacturer guarantees that the device will not exceed the value given under the speciﬁed operating or switching conditions. A minimum value means that the manufacturer guarantees that the device will perform at least, as well as the characteristic given under the speciﬁed operating or switching conditions. Thyristor types shown in parenthesis indicate a characteristic unique to that device. Gate conditions of both voltage and current to ensure either nontriggered or triggered device operation are included. The turnon and turnoff transients of the thyristor are characterized by switching times like the
TABLE 6.4 Typical thyristor characteristic maximum and minimum values speciﬁed by manufacturers Symbol
Description
VTM , VFM
Maximum onstate voltage drop(at speciﬁed junction temperature and forward current)
IDRM
Maximum forward offstate current (at speciﬁed junction temperature and forward voltage)
IRRM
Maximum reverse offstate current (at speciﬁed junction temperature and reverse voltage)
dv/dt
Minimum critical rate of rise of offstate voltage at speciﬁed junction temperature and forwardblocking voltage level
VGT
Maximum gate trigger voltage (at speciﬁed temperature and forward applied voltage)
VGD , VGDM
Maximum gate nontrigger voltage (at speciﬁed temperature and forward applied voltage)
IGT
Maximum gate trigger current (at speciﬁed temperature and forward applied voltage)
Tgt (GTO)
Maximum turnon time (under speciﬁed switching conditions)
Tq
Maximum turnoff time (under speciﬁed switching conditions)
tD
Maximum turnon delay time (for speciﬁed test)
R(J −C)
Maximum junctiontocase thermal resistance
R(C−S)
Maximum casetosink thermal resistance (interface lubricated)
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turnoff time listed in Table 6.4. The turnon transient can be divided into three intervals: (i) gatedelay interval; (ii) turnon of initial area; and (iii) spreading interval. The gatedelay interval is simply the time between application of a turnon pulse at the gate and the time the initial cathode area turns on. This delay decreases with increasing gate drive current and is of the order of a few microseconds. The second interval, the time required for turnon of the initial area, is quite short, typically less than 1 ms. In general, the initial area turned on is a small percentage of the total useful device area. After the initial area turns on, conduction spreads (spreading interval or plasma spreading time) throughout the device in tens of microseconds for highspeed or thyristors. The plasma spreading time may take up to hundreds of microseconds in largearea phasecontrol devices. Table 6.5 lists many of the thyristor parameters that appear as listed values or as information on graphs. The deﬁnition of each parameter and the test conditions under which they are measured are given in the table as well.
6.6 Types of Thyristors In recent years, most development effort has gone into continued integration of the gating and control electronics into thyristor modules, and the use of MOStechnology to create gate structures integrated into the thyristor itself. Many variations of this theme are being developed and some technologies should rise above the others in the years to come. Further details concerning most of the following discussion of thyristor types can be found in [1].
6.6.1 SCRs and GTOs The highest power handling devices continue to be bipolar thyristors. High powered thyristors are large diameter devices, some well in excess of 100 mm, and as such have a limitation on the rate of rise of anode current, a di/dt rating. The depletion capacitances around the p–n junctions, in particular the center junction J2 , limit the rate of rise in forward voltage that can be applied even after all the stored charge, introduced during conduction, is removed. The associated displacement current under application of forward voltage during the thyristor blocking state sets a dv/dt limit. Some effort in improving the voltage holdoff capability and overvoltage protection of conventional SCRs is underway by incorporating a lateral high resistivity region to help dissipate the energy during breakover. Most effort, though, is being placed in the further development of high performance GTOs and IGCTs because of their controllability and to a lesser extent in optically triggered structures that feature gate circuit isolation. High voltage GTOs with symmetric blocking capability require thick nbase regions to support the high electric ﬁeld.
The addition of an n+ buffer layer next to the p+anode allows high voltage forwardblocking and a low forward voltage drop during conduction because of the thinner nbase required. Cylindrical anode shorts have been incorporated to facilitate excess carrier removal from the nbase during turnoff and still retain the high blocking capability. This device structure can control 200 A, operating at 900 Hz, with a 6 kV holdoff. Some of the design tradeoff between the nbase width and turnoff energy losses in these structures have been determined. A similar GTO incorporating an n+ buffer layer and a pin structure has been fabricated that can control up to 1 kA (at a forward drop of 4 V) with a forward blocking capability of 8 kV. A reverse conducting GTO has been fabricated that can block 6 kV in the forward direction, interrupt a peak current of 3 kA and has a turnoff gain of about 5. The IGCT is a modiﬁed GTO structure. It is designed and manufactured so that it commutates all of the cathode current away from the cathode region and diverts it out of the gate contact. The IGCT is similar to a GTO in structure except that it always has a lowloss nbuffer region between the nbase and pemitter. The IGCT device package is designed to result in a very low parasitic inductance and is integrated with a specially designed gatedrive circuit. The gate drive contains all the necessary di/dt and dv/dt protection; the only connections required are a lowvoltage power supply for the gate drive and an optical signal for controlling the gate. The specially designed gate drive and ringgate package circuit allows the IGCT to be operated without a snubber circuit, and to switch with a higher anode di/dt than a similar GTO. At blocking voltages of 4.5 kV and higher the IGCT provides better performance than a conventional GTO. The speed at which the cathode current is diverted to the gate (diGQ /dt) is directly related to the peak snubberless turnoff capability of the IGCT. The gate drive circuit can sink current for turnoff at diGQ /dt values in excess of 7000 A/ms. This hard gate drive results in a low charge storage time of about 1 ms. The low storage time and the failshort mode makes the IGCT attractive for highpower, highvoltage series applications; examples include highpower converters in excess of 100 MVA, static volampere reactive (VAR) compensators and converters for distributed generation such as wind power.
6.6.2 MOScontrolled Thyristors The cross section of the ptype MCT unit cell is given in Fig. 6.17. When the MCT is in its forwardblocking state and a negative gate–anode voltage is applied, an inversion layer is formed in the ndoped material that allows holes to ﬂow laterally from the pemitter (pchannel FET source) through the channel to the pbase (pchannel FET drain). This hole ﬂow is the base current for the npn transistor. The nemitter then injects electrons which are collected in the nbase, causing the pemitter to inject holes into the nbase so that the pnp transistor is turned on and latches the MCT. The MCT is brought
102 TABLE 6.5
A. Bryant et al. Symbols and deﬁnitions of major thyristor parameters
Rθ
Thermal resistance
Speciﬁes the degree of temperature rise per unit of power, measuring junction temperature from a speciﬁed external point. Deﬁned when junction power dissipation results in steadystate thermal ﬂow.
Rθ(J −A) Rθ(J −C) Rθ(J −S)
Junctiontoambient thermal resistance Junctiontocase thermal resistance Junctiontosink thermal resistance
Rθ(C−S)
Contact thermal resistance
Zθ
Transient thermal impedance
Zθ(J −A) Zθ(J −C)
Junctiontoambient transient thermal impedance Junctiontocase transient thermal impedance
The steadystate thermal resistance between the junction and ambient. The steadystate thermal resistance between the junction and case surface. The steadystate thermal resistance between the junction and the heatsink mounting surface. The steadystate thermal resistance between the surface of the case and the heatsink mounting surface. The change of temperature difference between two speciﬁed points or regions at the end of a time interval divided by the step function change in power dissipation at the beginning of the same interval causing the change of temperature difference. The transient thermal impedance between the junction and ambient.
Zθ(J −S)
Junctiontosink transient thermal impedance
TA
Ambient temperature
TS TC TJ
Sink temperature Case temperature Junction temperature
TSTG
Storage temperature
VRRM
Peak reverse blocking voltage
VRSM
Transient peak reverseblocking voltage
VR(DC) SCR only
dc reverseblocking voltage
VDRM
Peak forwardblocking voltage
VDSM
Transient peak forwardblocking voltage
VD(DC)
dc forwardblocking voltage
dv/dt
Critical rate of rise of offstate voltage dv/dt = (0.632VD )/τVD is speciﬁed offstate voltage τ is time constant for exponential
VTM
Peak onstate voltage
The transient thermal impedance between the junction and the case surface. The transient thermal impedance between the junction and the heatsink mounting surface. It is the temperature of the surrounding atmosphere of a device when natural or forcedair cooling is used, and is not inﬂuenced by heat dissipation of the device. The temperature at a speciﬁed point on the device heatsink. The temperature at a speciﬁed point on the device case. The device junction temperature rating. Speciﬁes the maximum and minimum allowable operation temperatures. Speciﬁes the maximum and minimum allowable storage temperatures (with no electrical connections). Within the rated junction temperature range, and with the gate terminal open circuited, speciﬁes the repetitive peak reverse anode to cathode voltage applicable on each cycle. Within the rated junction temperature range, and with the gate terminal open circuited, speciﬁes the nonrepetitive peak reverse anode to cathode voltage applicable for a time width equivalent to less than 5 ms. Within the rated junction temperature range, and with the gate terminal opencircuited, speciﬁes the maximum value for dc anode to cathode voltage applicable in the reverse direction. Within the rated junction temperature range, and with the gate terminal open circuited (SCR), or with a speciﬁed reverse voltage between the gate and cathode (GTO), speciﬁes the repetitive peak offstate anode to cathode voltage applicable on each cycle. This does not apply for transient offstate voltage application. Within the rated junction temperature range, and with the gate terminal open circuited (SCR), or with a speciﬁed reverse voltage between the gate and cathode (GTO), speciﬁes the nonrepetitive offstate anode to cathode voltage applicable for a time width equivalent to less than 5 ms. This gives the maximum instantaneous value for nonrepetitive transient offstate voltage. Within the rated junction temperature range, and with the gate terminal open circuited (SCR), or with a speciﬁed reverse voltage between the gate and cathode (GTO), speciﬁes the maximum value for dc anode to cathode voltage applicable in the forward direction. At the maximum rated junction temperature range, and with the gate terminal open circuited (SCR), or with a speciﬁed reverse voltage between the gate and cathode (GTO), this speciﬁes the maximum rate of rise of offstate voltage that will not drive the device from an offstate to an onstate when an exponential offstate voltage of speciﬁed amplitude is applied to the device. At speciﬁed junction temperature, and when onstate current (50 or 60 Hz, half sine wave of speciﬁed peak amplitude) is applied to the device, indicates peak value for the resulting voltage drop.
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TABLE 6.5—Contd. IT (RMS)
RMS onstate current
IT (AV )
Average onstate current
ITSM
Peak onstate current
I 2t
Currentsquared time
di/dt
Critical rate of Rise of onstate current
IRRM
Peak reverse leakage current
IDRM
Peak forwardleakage current
PGM (SCR) PGFM (GTO)
Peak gate power dissipation peak gate forward power dissipation
PG(AV )
Average gate power dissipation
PGRM GTO only
Peak gate reverse power dissipation
PGR(AV ) GTO only
Average gate reverse power dissipation
IGFM
Peak forward gate current
IGRM GTO only
Peak reverse gate current
VGRM
Peak reverse gate voltage
VGFM
Peak forward gate voltage
IGT
Gate current to trigger
VGT
Gate voltage to trigger
VGDM SCR Only
Nontriggering gate voltage
ITGQ GTO only
Gate controlled turnoff current
At speciﬁed case temperature, indicates the RMS value for onstate current that can be continuously applied to the device. At speciﬁed case temperature, and with the device connected to a resistive or inductive load, indicates the average value for forwardcurrent (sine half wave, commercial frequency) that can be continuously applied to the device. Within the rated junction temperature range, indicates the peakvalue for nonrepetitive onstate current (sine half wave, 50 or 60 Hz). This value indicated for one cycle, or as a function of a number of cycles. The maximum, onstate, nonrepetitive shorttime thermal capacity of the device and is helpful in selecting a fuse or providing a coordinated protection scheme of the device in the equipment. This rating is intended speciﬁcally for operation less than one half cycle of a 180° (degree) conduction angle sinusoidal wave form. The offstate blocking capability cannot be guaranteed at values near the maximum I 2 t . At speciﬁed case temperature, speciﬁed offstate voltage, speciﬁed gate conditions, and at a frequency of less than 60 Hz, indicates the maximum rate of rise of onstate current which the thyristor will withstand when switching from an offstate to an onstate, when using recommended gate drive. At maximum rated junction temperature, indicates the peak value for reverse current ﬂow when a voltage (sine half wave, 50 or 60 Hz, and having a peak value as speciﬁed for repetitive peak reversevoltage rating) is applied in a reverse direction to the device. At maximum rated junction temperature, indicates the peak value for offstate current ﬂow when a voltage (sine half wave, 50 or 60 Hz, and having a peak value for repetitive offstate voltage rating) is applied in a forward direction to the device. For a GTO, a reverse voltage between the gate and cathode is speciﬁed. Within the rated junction temperature range, indicates the peak value for maximum allowable power dissipation over a speciﬁed time period, when the device is in forwardconduction between the gate and cathode. Within the rated junction temperature range, indicates the average value for maximum allowable power dissipation when the device is forwardconducting between the gate and cathode. Within the rated junction temperature range, indicates the peak value for maximum allowable power dissipation in the reverse direction between the gate and cathode, over a speciﬁed time period. Within the rated junction temperature range, indicates the average value for maximum allowable power dissipation in the reverse direction between the gate and cathode. Within the rated junction temperature range, indicates the peak value for forward current ﬂow between the gate and cathode. Within the rated junction temperature range, indicates peak value for reverse current that can be conducted between the gate and cathode. Within the rated junction temperature range, indicates the peak value for reverse voltage applied between the gate and cathode. Within the rated junction temperature range, indicates the peak value for forward voltage applied between the gate and cathode. At a junction temperature of 25°C, and with a speciﬁed offvoltage, and a speciﬁed load resistance, indicates the minimum gate dc current required to switch the thyristor from an offstate to an onstate. At a junction temperature of 25°C, and with a speciﬁed offstate voltage, and a speciﬁed load resistance, indicates the minimum dc gate voltage required to switch the thyristor from an offstate to an onstate. At maximum rated junction temperature, and with a speciﬁed offstate voltage applied to the device, indicates the maximum dc gate voltage which will not switch the device from an offstate to an onstate. Under speciﬁed conditions, indicates the instantaneous value for oncurrent usable in gate control, speciﬁed immediately prior to device turnoff. continued
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TABLE 6.5—Contd. Rθ
Thermal resistance
Speciﬁes the degree of temperature rise per unit of power, measuring junction temperature from a speciﬁed external point. Deﬁned when junction power dissipation results in steadystate thermal ﬂow.
ton SCR only
Turnon time
Tq SCR Only
Turnoff time
tgt GTO only
Turnon time
tqt GTO only
Turnoff time
At speciﬁed junction temperature, and with a peak repetitive offstate voltage of half rated value, followed by device turnon using speciﬁed gate current, and when speciﬁed onstate current of speciﬁed di/dt ﬂows, indicated as the time required for the applied offstate voltage to drop to 10% of its initial value after gate current application. Delay time is the term used to deﬁne the time required for applied voltage to drop to 90% of its initial value following gatecurrent application. The time required for the voltage level to drop from 90 to 10% of its initial value is referred to as rise time. The sum of both these deﬁnes turnon time. Speciﬁed at maximum rated junction temperature. Device set up to conduct onstate current, followed by application of speciﬁed reverse anodecathode voltage to quench onstate current, and then increasing the anodecathode voltage at a speciﬁed rate of rise as determined by circuit conditions controlling the point where the speciﬁed offstate voltage is reached. Turnoff time deﬁnes the minimum time which the device will hold its offstate, starting from the time onstate current reached zero until the time forward voltage is again applied (i.e. applied anode–cathode voltage becomes positive again). When applying forward current to the gate, indicates the time required to switch the device from an offstate to an onstate. When applying reverse current to the gate, indicates the time required to switch the device from an onstate to an offstate.
anode gate
oxide n+ p
p+
n+ p
n−
p−
p n+
cathode
FIGURE 6.17 Cross section of unit cell of a ptype MCT.
out of conduction by applying a positive gate–anode voltage. This signal creates an inversion layer that diverts electrons in the nbase away from the pemitter and into the heavily doped nregion at the anode. This nchannel FET current amounts to a diversion of the pnp transistor base current so that its
base–emitter junction turns off. Holes are then no longer available for collection by the pbase. The elimination of this hole current (npn transistor base current) causes the npn transistor to turnoff. The remaining stored charge recombines and returns the MCT to its blocking state. The seeming variability in fabrication of the turnoff FET structure continues to limit the performance of MCTs, particularly current interruption capability, though these devices can handle two to ﬁve times the conduction current density of IGBTs. Numerical modeling and its experimental veriﬁcation show that ensembles of cells are sensitive to current ﬁlamentation during turnoff. All MCT device designs suffer from the problem of current interruption capability. Turnon is relatively simple, by comparison; both the turnon and conduction properties of the MCT approach the onedimensional thyristor limit. Other variations on the MCT structure have been demonstrated, namely the emitter switched thyristor (EST) and the dualgate emitter switched thyristor (DGEST) [12]. These comprise integrated lateral MOSFET structures which connect a ﬂoating thyristor nemitter region to an n+ thyristor cathode region. The MOS channels are in series with the ﬂoating nemitter region, allowing triggering of the thyristor with electrons from the nbase and interruption of the current to initiate turnoff. The DGEST behaves as a dualmode device, with the two gates allowing an IGBT mode to operate during switching and a thyristor mode to operate in the onstate.
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105
Thyristors light
cathode
amplifying gate structures
n+ buried gate
n+
K
R (p+)
p−
p
n−
n−
p n+ p+
A
FIGURE 6.19 Cross section of a lighttriggered thyristors (LTT).
anode
FIGURE 6.18 Cross section of a SITh or FCT.
6.6.3 Static Induction Thyristors A SITh or FCTh has a cross section similar to that shown in Fig. 6.18. Other SITh conﬁgurations have surface gate structures. The device is essentially a pin diode with a gate structure that can pinchoff anode current ﬂow. High power SIThs have a subsurface gate (buriedgate) structure to allow larger cathode areas to be utilized, and hence larger current densities are possible. Planar gate devices have been fabricated with blocking capabilities of up to 1.2 kV and conduction currents of 200 A, while stepgate (trenchgate) structures have been produced that are able to block up to 4 kV and conduct 400 A. Similar devices with a “Verigrid” structure have been demonstrated that can block 2 kV and conduct 200 A, with claims of up to 3.5 kV blocking and 200 A conduction. Buriedgate devices that block 2.5 kV and conduct 300 A have also been fabricated. Recently there has been a resurgence of interest in these devices for fabrication in SiC.
6.6.4 Optically Triggered Thyristors Optically gated thyristors have traditionally been used in power utility applications where series stacks of devices are necessary to achieve the high voltages required. Isolation between gate drive circuits for circuits such as static VAR compensators and high voltage dc to ac inverters (for use in high voltage dc (HVDC) transmission) have driven the development of this class of devices, which are typically available in ratings from 5 to 8 kV. The cross section is similar to that shown in Fig. 6.19, showing the photosensitive region and the
amplifying gate structures. Lighttriggered thyristors (LTTs) may also integrate overvoltage protection. One of the most recent devices can block 6 kV forward and reverse, conduct 2.5 kA average current, maintain a di/dt capability of 300 A/ms and a dv/dt capability of 3000 V/ms, with a required trigger power of 10 mW. An integrated light triggered and light quenched SITh has been produced that can block 1.2 kV and conduct up to 20 A (at a forward drop of 2.5 V). This device is an integration of a normally off buriedgate static induction photothyristor and a normally off pchannel darlington surfacegate static induction phototransistor. The optical trigger and quenching power required is less than 5 and 0.2 mW, respectively.
6.6.5 Bidirectional Thyristors The BCT is an integrated assembly of two antiparallel thyristors on one Si wafer. The intended applications for this switch are VAR compensators, static switches, soft starters and motor drives. These devices are rated up to 6.5 kV blocking. Crosstalk between the two halves has been minimized. A cross section of the BCT is shown in Fig. 6.20. Note that each surface has a cathode and an anode (opposite devices). The small gate–cathode periphery necessarily restricts the BCT to lowfrequency applications because of its di/dt limit. Lowpower devices similar to the BCT, but in existence for many years, are the diac and triac. A simpliﬁed cross section of a diac is shown in Fig. 6.21. A positive voltage applied to the anode with respect to the cathode forward biases J1 , while reverse biasing J2 . J4 and J3 are shorted by the metal contacts. When J2 is biased to breakdown, a lateral current ﬂows in the p2 region. This lateral ﬂow forward biases the edge of J3 , causing carrier injection. The result is that the device switches into its thyristor mode and latches. Applying a reverse voltage causes the opposite behavior at each junction, but
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Separation region
reverse breakover voltages for a given gate voltage. The device is ﬁred by applying a gate pulse of the same polarity relative to MT1 as that of MT2.
Thyristor half A Gate A
Anode B Cathode A Shallow pbase Deep pbase
VB(t)
nbase
VA(t)
6.7 Gate Drive Requirements 6.7.1 Snubber Circuits
Deep pbase Shallow pbase Anode A
Cathode B
Gate B (not visible)
FIGURE 6.20 Cross section of a bidirectional control thyristor (BCT).
A i
A J4
n3 p1
J1 n1
v
J2 p2
J3
n2
K K
To protect a thyristor, from a large di/dt during turnon and a large dv/dt during turnoff, a snubber circuit is needed. A general snubber topology is shown in Fig. 6.23. The turnon snubber is made by inductance L1 (often L1 is stray inductance only). This protects the thyristor from a large di/dt during the turnon process. The auxiliary circuit made by R1 and D1 allows the discharging of L1 when the thyristor is turned off. The turnoff snubber is made by resistor R2 and capacitance C2 . This circuit protects a GTO from large dv/dt during the turnoff process. The auxiliary circuit made by D2 and R2 allows the discharging of C2 when the thyristor is turned on. The circuit of capacitance C2 and inductance L1 also limits the value of dv/dt across the thyristor during forwardblocking. In addition, L1 protects the thyristor from reverse overcurrents. R1 and diodes D1 , D2 are usually omitted in ac circuits with convertergrade thyristors. A similar second set of L, C and R may be used around this circuit in HVDC applications.
FIGURE 6.21 Cross section and i–v plot of a diac.
6.7.2 Gate Circuits MT1
MT1
G
n+
n
It is possible to turn on a thyristor by injecting a current pulse into its gate. This process is known as gating, triggering or ﬁring the thyristor. The most important restrictions are on the maximum peak and duration of the gate pulse current.
p G n− R1
L1
p
D1
n+
MT2
MT2
FIGURE 6.22 Cross section of a triac.
with the same result. Figure 6.21 also shows the i–v plot for a diac. The addition of a gate connection, to form a triac, allows the breakover to be controlled at a lower forward voltage. Figure 6.22 shows the structure for the triac. Unlike the diac, this is not symmetrical, resulting in differing forward and
Thyristor
C2
R2
D2
FIGURE 6.23 Turnon (top elements) and turnoff (bottom elements) snubber circuits for thyristors.
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107
Thyristors ig(t)
Backporch current
t
0
FIGURE 6.24 Gate current waveform showing large initial current followed by a suitable backporch value.
In order to allow a fast turnon, and a correspondingly large anode di/dt during the turnon process, a large gate current pulse is supplied during the initial turnon phase with a large diG /dt. The gate current is kept on, at lower value, for some times after the thyristor turned on in order to avoid unwanted turnoff of the device; this is known as the “backporch” current. A shaped gate current waveform of this type is shown in Fig. 6.24. Figure 6.25 shows typical gate i–v characteristics for the maximum and minimum operating temperatures. The dashed line represents the minimum gate current and corresponding gate voltage needed to ensure that the thyristor will be triggered at various operating temperatures. It is also known as the locus of minimum ﬁring points. On the data sheet it is possible ﬁnd a line representing the maximum operating power of the thyristor gating internal circuit. The straight line, between VGG and
VGG /RG , represents the current voltage characteristic of the equivalent trigger circuit. If the equivalent trigger circuit line intercepts the two gate i–v characteristics for the maximum and minimum operating temperatures between where they intercept the dashed lines (minimum gate current to trigger and maximum gate power dissipation), then the trigger circuit is able to turnon the thyristor at any operating temperature without destroying or damaging the device. In order to keep the power circuit and the control circuit electrically unconnected, the gate signal generator and the gate of the thyristor are often connected through a transformer. There is a transformer winding for each thyristor, and in this way unwanted short circuits between devices are avoided. A general block diagram of a thyristor gatetrigger circuit is shown in Fig. 6.26. This application is for a standard bridge conﬁguration often used in power converters. Another problem can arise if the load impedance is high, particularly if the load is inductive and the supply voltage is low. In this situation, the latching current may not be reached during the trigger pulse. A possible solution to this problem could be the use of a longer current pulse. However, such a solution is not attractive because of the presence of the isolation transformer. An alternative solution is the generation of a series of short pulses that last for the same duration as a single long pulse. A single short pulse, a single long pulse and a series of short pulses are shown in Fig. 6.27. Reliable gating of the thyristor is essential in many applications. There are many gate trigger circuits that use optical isolation between the logiclevel electronics and a drive stage (typically MOSFETs) conﬁgured in a push–pull output. The dc power supply voltage for the drive stage is provided
VGK
Tj = –40 °C
VG
Maximum gate power dissipation
Tj = 150 °C
0
VG/RG Minimum gate current to trigger
FIGURE 6.25 Gate i–v curve for a typical thyristor.
IG
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T1
T3
Power Converter
AC Line Voltage
T2
T4
Out to T3 DC Power Supply for Current Amplifier Circuit
Out to T4
Current Amplifier Input Control Signal
ZeroCrossing Detection and PhaseAngle Circuit
Out to T2
Out to T1 Isolation Transformers for Gate Trigger Signal
FIGURE 6.26 Block diagram of a transformerisolated gate drive circuit.
iG (a) GCT
0 iG
a
p
2p a + 2p
3p
wt
0 iG
a
p
2p a + 2p
3p
wt
0
a
p
2p a + 2p
3p
wt
Gate unit
(b)
(c)
FIGURE 6.27 Multiple gate pulses used as an alternative to one long current pulse.
FIGURE 6.28 Typical layout of an IGCT gate drive.
through transformer isolation. Many device manufacturers supply drive circuits available on printed circuit (PC) boards or diagrams of suggested circuits. IGCT gate drives consist of an integrated module to which the thyristor is connected via a lowinductance mounting; an example is given in Fig. 6.28. Multiple MOSFETs and
capacitors connected in parallel may be used to source or sink the necessary currents to turn the device on or off. Logic in the module controls the gate drive from a ﬁberoptic trigger input, and provides diagnostic feedback from a ﬁberoptic output. A simple power supply connection is also required.
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Thyristors
6.8 PSpice Model Circuit simulators such as Spice and PSpice are widely used as tools in the design of power systems. For this purpose equivalent circuit models of thyristors have been developed. A variety of models have been proposed with varying degrees of complexity and accuracy. Frequently the simple twotransistor model described in Section 6.2 is used in PSpice. This simple structure, however, cannot model the appropriate negativedifferentialresistance (NDR) behavior as the thyristor moves from forwardblocking to forwardconduction. Few other models for conventional thyristors have been reported. A PSpice model for a GTO has been developed by Tsay et al. [13], which captures much of thyristor behavior, such as the static i–v curve shown in Fig. 6.3, dynamic characteristics (turnon and turnoff times), device failure modes (e.g. current crowding due to excessive di/dt at turnon and spurious turnon due to excessive dv/dt at turnoff), and thermal effects. Specifically, three resistors are added to the twotransistor model to create the appropriate behavior. The proposed twotransistor, threeresistor model (2T3R) is shown in Fig. 6.29. This circuit exhibits the desired NDR behavior. Given the static i–v characteristics for an SCR or GTO, it is possible to obtain similar curves from the model by choosing appropriate values for the three resistors and for the forward current gains αp and αn of the two transistors. The process of curve ﬁtting can be simpliﬁed by keeping in mind that resistor R1 tends to affect the negative slope of the i–v characteristic, resistor R2 tends to affect the value of the holding current IH and resistor R3 tends to affect the value of the forward breakdown voltage VFBD . When modeling thyristors with cathode or anode shorts, as described in Section 6.4, the presence of these shorts determines the values of R1 and R2 ,
Ai IAi R2i
PNP Q1i R3i
Gi
IGi
NPN Q2i R1i
Ki
FIGURE 6.29 A twotransistor, threeresistor model for SCRs and GTOs.
respectively. In the case of a GTO or IGCT, an important device characteristic is the socalled turnoff gain Koff =IA /IG , i.e. the ratio of the anode current to the negative gate current required to turnoff the device. An approximate formula relating the turnoff gain to the α‘s of the two transistors is given by, Koff =
αn αn + α p − 1
(6.3)
The ability of this model to predict dynamic effects depends on the dynamics included in the transistor models. If transistor junction capacitances are included, it is possible to model the dv/dt limit of the thyristor. Too high a value of dvAK /dt will cause signiﬁcant current to ﬂow through the J2 junction capacitance. This current acts like gate current and can turn on the device. This model does not accurately represent spatial effects such as current crowding at turnon (the di/dt limit), when only part of the device is conducting, and, in the case of a GTO, current crowding at turnoff, when current is extracted from the gate to turnoff the device. Current crowding is caused by the location of the gate connection with respect to the conducting area of the thyristor and by the magnetic ﬁeld generated by the changing conduction current. To model these effects, Tsay et al. [13] propose a multicell circuit model, in which the device is discretized in a number of conducting cells, each having the structure of Fig. 6.29. This model, shown in Fig. 6.30, takes into account the mutual inductive coupling, the delay in the gate turnoff signal due to positions of the cells relative to the gate connection, and nonuniform gate and cathodecontact resistance. In particular, the RC delay circuits (series R with a shunt C tied to the cathode node) model the time delays between the gate triggering signals due to the position of the cell with respect to the gate connection; coupled inductors, M, model magnetic coupling between cells; resistors, RKC , model nonuniform contact resistance; and resistors, RGC , model gate contact resistances. The various circuit elements in the model can be estimated from device geometry and measured electrical characteristics. The choice of the number of cells is a tradeoff between accuracy and complexity. Example values of the RC delay network, RGC , RKC , and M are given in Table 6.6. Other GTO thyristor models have been developed which offer improved accuracy at the expense of increased complexity. The model by Tseng et al. [14] includes charge storage TABLE 6.6 Element values for each cell of a multicell GTO model Model component
Symbol
Value
Delay resistor Delay capacitor Mutual coupling inductance Gate contact resistance Cathode contact resistance
R C M RGC RKC
1 m 1 nF 10 nH 1 m 1 m
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Gate
Islands (Cathode)
Anode
RGC1 G1 RKC1
A1
A2
A3
A8
Cell Model 1
Cell Model 2
Cell Model 3
Cell Model 8
RGC2 G2 RKC2
K1
Delay Circuit
G3 RKC3
K2
M12 Gate
RGC3
Delay Circuit
RGC8 G8 RKC8
K3
K8
M23
Delay Circuit
Cathode
FIGURE 6.30 Thyristor multicell circuit model containing eight cells.
effects in the nbase, and its application to a multicell model, as in Fig. 6.30, has been demonstrated successfully. Models for the IGCT, based on the lumpedcharge approach [15] and the Fourierbased solution of the ambipolar diffusion equation (ADE) [16], have also been developed.
id +
Ld
Ls +
6.9 Applications
vd
vs
Load
−
The most important application of thyristors is for linefrequency phasecontrolled rectiﬁers. This family includes several topologies, of which one of the most important is used to construct HVDC transmission systems. A singlephase controlled rectiﬁer is shown in Fig. 6.31. The use of thyristors instead of diodes allows the average output voltage to be controlled by appropriate gating of the thyristors. If the gate signals to the thyristors were continuously applied, the thyristors in Fig. 6.31 would behave as diodes. If no gate currents are supplied they behave as open circuits. Gate current can be applied any time (phase delay) after the forward voltage becomes positive. Using this phasecontrol feature, it is possible to produce an average dc output voltage less than the average output voltage obtained from an uncontrolled diode rectiﬁer.
−
FIGURE 6.31 Singlephase controlled rectiﬁer circuit.
6.9.1 DC–AC Utility Inverters Threephase converters can be made in different ways, according to the system in which they are employed. The basic circuit used to construct these topologies – the threephase controlled rectiﬁer – is shown in Fig. 6.32.
6
111
Thyristors ir +
n
v − an + a
Ls
b
Ls
c
Ls
−v
+
−
+
bn
vcn
Lr
Load
vr
−
are required to reduce the current harmonics generated by the converter. When a large amount of current and relatively low voltage is required, it is possible to connect in parallel, using a specially designed inductor, two sixpulse linefrequency converters connected through Y and YY transformers. The special inductor is designed to absorb the voltage between the two converters, and to provide a pole to the load. This topology is shown in Fig. 6.34. This conﬁguration is often known as a twelvepulse converter. Higher pulse numbers may also be found.
6.9.2 Motor Control
FIGURE 6.32 A threephase controlled bridge circuit used as a basic topology for many converter systems.
Starting from this basic conﬁguration, it is possible to construct more complex circuits in order to obtain highvoltage or highcurrent outputs, or just to reduce the output ripple by constructing a multiphase converter. One of the most important systems using the topology shown in Fig. 6.32 as a basic circuit is the HVDC system represented in Fig. 6.33. This system is made by two converters, a transmission line, and two ac systems. Each converter terminal is made of two poles. Each pole is made by two sixpulse linefrequency converters connected through Y and YY transformers in order to obtain a twelvepulse converter and a reduced output ripple. The ﬁlters
Another important application of thyristors is in motor control circuits. Historically thyristors have been used heavily in traction, although most new designs are now based on IGBTs. Such motor control circuits broadly fall into four types: i) chopper control of a dc motor from a dc supply; ii) singleor threephase converter control of a dc motor from an ac supply; iii) inverter control of an ac synchronous or induction machine from a dc supply and iv) cycloconverter control of an ac machine from an ac supply. An example of a GTO chopper is given in Fig. 6.35. L1 , R1 , D1 , and C1 are the turnon snubber; R2 , D2 , and C2 are the turnoff snubber; ﬁnally R3 and D3 form the snubber for the freewheel diode D3 . A thyristor cycloconverter is shown in Fig. 6.36; the waveforms show the fundamental component of the output voltage for one phase. Three double converters are used to produce a threephase
Converter #1
Converter #2
12pulse Converter for Positive Line Y Y
Filter Y
AC Power Grid #1
AC Power Grid #2 Y Y
Y
Filter
12pulse Converter for Negative Line
FIGURE 6.33 A HVDC transmission system.
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AC Grid Load AC Motor
FIGURE 6.34 Parallel connection of two sixpulse converters for high current applications.
3φ Line
+ R1
C1
L1
D1
D4
C2
D2
T1
FIGURE 6.36 Cycloconverter for control of large ac machines.
R2
C3 Motor R3
D3
−
FIGURE 6.35 GTO chopper for dc motor control.
variablefrequency, variable voltage sinusoidal output for driving ac motors. However, the limited frequency range (less than a third of the line frequency) restricts the application to large, lowspeed machines at high powers. A single or threephase thyristor converter (controlled rectiﬁer) may be used to provide a variable dc supply for controlling a dc motor. Such a converter may also be used as the front end of a threephase induction motor drive. The variable voltage, variable frequency motor drive requires a dc supply, which is supplied by the thyristor converter. The drive may use a squarewave or PWM voltage source inverter (VSI), or a current source inverter (CSI). Figure 6.37 shows a squarewave or PWM VSI with a controlled rectiﬁer on the input side. The switch block inverter may be made of thyristors (usually GTOs or IGCTs) for high power, although most new designs
now use IGBTs. Lowpower motor controllers generally use IGBT inverters. In motor control, thyristors are also used in CSI topologies. When the motor is controlled by a CSI, a controlled rectiﬁer is also needed on the input side. Figure 6.38 shows a typical CSI inverter. The capacitors are needed to force the current in the thyristors to zero at each switching event. This is not needed when using GTOs. This inverter topology does not need any additional circuitry to provide the regenerative braking (energy recovery when slowing the motor). Historically, two backtoback connected linefrequency thyristor converters have been employed to allow bidirectional power ﬂow, and thus regenerative braking. Use of antiparallel GTOs with symmetric blocking capability, or the use of diodes in series with each asymmetric GTO, reduces the number of power devices needed, but greatly increases the control complexity.
6.9.3 VAR Compensators and Static Switching Systems Thyristors are also used to switch capacitors or inductors in order to control the reactive power in the system. Such arrangements may also be used in phasebalancing circuits for
6
113
Thyristors
+
AC 1φ or 3φ, 50 or 60 Hz
AC Output, Variable Voltage and Variable Frequency
DC Voltage
Filter Controlled Rectifier
Induction Motor Threephase Inverter
−
FIGURE 6.37 PWM or squarewave inverter with a controlled rectiﬁer input.
Lr
ir
Induction motor
ia
FIGURE 6.38 CSI on the output section of a motor drive system using capacitors for power factor correction.
balancing the load fed from a threephase supply. Examples of these circuits are shown in Fig. 6.39. These circuits act as static VAR controllers. The topology represented on the left of Fig. 6.39 is called a thyristorcontrolled inductor (TCI) and it acts as a variable inductor where the inductive VAR supplied can be varied quickly. Because the system may require either inductive or capacitive VAR compensation, it is possible to connect a bank of capacitors in parallel with a TCI. The topology shown on the right of Fig. 6.39 is called a thyristorswitched capacitor (TSC). Capacitors can be switched out by
blocking the gate pulse of all thyristors in the circuit. The problem of this topology is the voltage across the capacitors at the thyristor turnoff. At turnon the thyristor must be gated at the instant of the maximum ac voltage to avoid large overcurrents. Many recent SVCs have used GTOs. A similar application of thyristors is in solidstate fault current limiters and circuit breakers. In normal operation, the thyristors are continuously gated. However, under fault conditions they are switched rapidly to increase the series impedance in the load and to limit the fault current. Key advantages are the ﬂexibility of the current limiting, which is independent of the location of the fault and the change in load impedance, the reduction in fault level of the supply, and a smaller voltage sag during a shortcircuit fault. A less important application of thyristors is as a static transfer switch, used to improve the reliability of uninterruptible power supplies (UPS) as shown in Fig. 6.40. There are two modes of using the thyristors. The ﬁrst leaves the load permanently connected to the UPS system and in case of emergency disconnects the load from the UPS and connects it directly to the power line. The second mode is opposite to the ﬁrst one. Under normal conditions the load is permanently connected to the power line, and in event of a line outage, the load is disconnected from the power line and connected to the UPS system.
AC System VAC
L
C1
FIGURE 6.39 Per phase TCI and TSC system.
C2
114
A. Bryant et al.
AC Line In Load
Batteries
Rectifier
Inverter
Static Transfer Switch Pairs
FIGURE 6.40 Static transfer switch used in an UPS system.
Lamp
Filter AC Supply
MT2 MT1
Triac
R
G Diac
C
FIGURE 6.41 Basic dimmer circuit used in lighting control.
6.9.4 Lighting Control Circuits An important circuit used in lighting control is the dimmer, based on a triac and shown in Fig. 6.41. The R–C network applies a phase shift to the gate voltage, delaying the triggering of the triac. Varying the resistance, controls the ﬁring angle of the triac and therefore the voltage across the load. The diac is used to provide symmetrical triggering for the positive and negative halfcycles, due to the nonsymmetrical nature of the triac. This ensures symmetrical waveforms and elimination of even harmonics. An L–C ﬁlter is often used to reduce any remaining harmonics.
Further Reading 1. J.L. Hudgins, “A review of modern power semiconductor electronic devices,” Microelectronics Journal, vol. 24, pp. 41–54, Jan. 1993. 2. S.K. Ghandi, Semiconductor Power Devices – Physics of Operation and Fabrication Technology, New York, John Wiley and Sons, 1977, pp. 63–84. 3. B.J. Baliga, Power Semiconductor Devices, Boston, PWS Publishing, 1996, pp. 91–110.
4. B. Beker, J.L. Hudgins, J. Coronati, B. Gillett, and S. Shekhawat, “Parasitic parameter extraction of PEBB module using VTB technology,” IEEE IAS Ann. Mtg. Rec., pp. 467–471, Oct. 1997. 5. C.V. Godbold, V.A. Sankaran, and J.L. Hudgins, “Thermal analysis of high power modules,” IEEE Trans. PEL, vol. 12, no. 1, pp. 3–11, Jan. 1997. 6. J.L. Hudgins and W.M. Portnoy, “High di/dt pulse switching of thyristors,” IEEE Tran. PEL, vol. 2, pp. 143–148, April 1987. 7. S.M. Sze, Physics of Semiconductor Devices, 2nd ed., New York, John Wiley and Sons, 1984, pp. 140–147. 8. V.A. Sankaran, J.L. Hudgins, and W.M. Portnoy, “Role of the amplifying gate in the turnon process of involute structure thyristors,” IEEE Tran. PEL, vol. 5, no. 2, pp. 125–132, April 1990. 9. S. Menhart, J.L. Hudgins, and W.M. Portnoy, “The low temperature behavior of thyristors,” IEEE Tran. ED, vol. 39, pp. 1011–1013, April 1992. 10. A. Herlet, “The forward characteristic of silicon power rectiﬁers at high current densities,” SolidState Electron., vol. 11, no. 8, pp. 717–742, 1968. 11. J.L. Hudgins, C.V. Godbold, W.M. Portnoy, and O.M. Mueller, “Temperature effects on GTO characteristics,” IEEE IAS Annual Mtg. Rec., pp. 1182–1186, Oct. 1994. 12. P.R. Palmer and B.H. Stark, “A PSPICE model of the DGEST based on the ambipolar diffusion equation,” IEEE PESC Rec., pp. 358–363, June 1999. 13. C.L. Tsay, R. Fischl, J. Schwartzenberg, H. Kan, and J. Barrow, “A high power circuit model for the gate turn off thyristor,” IEEE IAS Annual Mtg. Rec., pp. 390–397, Oct. 1990. 14. K.J. Tseng and P.R. Palmer, “Mathematical model of gateturnoff thyristor for use in circuit simulations,” IEE Proc.Electr. Power Appl., vol. 141, no. 6, pp. 284–292, Nov. 1994. 15. X. Wang, A. Caiafa, J. Hudgins, and E. Santi, “Temperature effects on IGCT performance,” IEEE IAS Annual Mtg. Rec., Oct. 2003. 16. X. Wang, A. Caiafa, J.L. Hudgins, E. Santi, and P.R. Palmer, “Implementation and validation of a physicsbased circuit model for IGCT with full temperature dependencies,” IEEE PESC Rec., pp. 597–603, June 2004.
7 Gate Turnoff Thyristors Muhammad H. Rashid, Ph.D. Electrical and Computer Engineering, University of West Florida, 11000 University Parkway, Pensacola, Florida 325145754, USA
7.1 7.2 7.3 7.4
Introduction .......................................................................................... 115 Basic Structure and Operation................................................................... 115 GTO Thyristor Models ............................................................................ 116 Static Characteristics ............................................................................... 117 7.4.1 Onstate Characteristics • 7.4.2 Offstate Characteristics • 7.4.3 Rate of Rise of Offstate Voltage (dvT /dt) • 7.4.4 Gate Triggering Characteristics
7.5 Switching Phases..................................................................................... 118 7.6 SPICE GTO Model.................................................................................. 120 7.7 Applications........................................................................................... 121 References ............................................................................................. 121
7.1 Introduction A gate turnoff thyristor (known as a GTO) is a three terminal power semiconductor device. GTOs belong to a thyristor family having a fourlayer structure. GTOs also belong to a group of power semiconductor devices that have the ability for full control of on and offstates via the control terminal (gate). To fully understand the design, development and operation of the GTO, it is easier to compare with the conventional thyristor. Like a conventional thyristor, applying a positive gate signal to its gate terminal can turnon to a GTO. Unlike a standard thyristor, a GTO is designed to turnoff by applying a negative gate signal. GTOs are of two types: asymmetrical and symmetrical. The asymmetrical GTOs are the most common type on the market. This type of GTOs is normally used with a antiparallel diode and hence high reverse blocking capability is not available. The reverse conducting is accomplished with an antiparallel diode integrated onto the same silicon wafer. The symmetrical type of GTOs has an equal forward and reverse blocking capability.
7.2 Basic Structure and Operation The symbol of a GTO is shown in Fig. 7.1a. A high degree of interdigitation is required in GTOs in order to achieve efﬁcient turnoff. The most common design employs the cathode area
separated into multiple segments (cathode ﬁngers) arranged in concentric rings around the device center. The internal structure is shown in Fig. 7.1b. A common contact disc pressed against the cathode ﬁngers connects the ﬁngers together. It is important that all the ﬁngers turns off simultaneously, otherwise the current may be concentrated into a fewer ﬁngers which are likely to be damaged due to over heating. The high level of gate interdigitation also results in a fast turnon speed and a high di/dt performance of the GTOs. The most remote part of a cathode region is not more than 0.16 mm from a gate edge and hence the whole GTO can conduct within about 5 µs with sufﬁcient gate drive and the turnon losses can be reduced. However, the interdigitation reduces the available emitter area so the low frequency average current rating is less than for a standard thyristor with an equivalent diameter. The basic structure of a GTO consists of a fourlayerPNPN semiconductor device, which is very similar in construction to a thyristor. It has several design features which allow it to be turned on and off by reversing the polarity of the gate signal. The most important differences are that the GTO has long narrow emitter ﬁngers surrounded by gate electrodes and no cathode shorts. The turnon mode is similar to a standard thyristor. The injection of the hole current from the gate forward biases the cathode pbase junction causing electron emission from the cathode. These electrons ﬂow to the anode and induce hole injection by the anode emitter. The injection of holes and electrons into the base regions continues until charge 115 Copyright © 2001 by Academic Press
116
M. H. Rashid
n+
A
through the most remote areas from the gate contacts, forming high current density ﬁlaments. This is the most crucial phase of the turnoff process in GTOs, because high density ﬁlaments leads to localized heating which can cause device failure unless these ﬁlaments are extinguished quickly. An application of higher negative gate voltage may aid in extinguishing the ﬁlaments rapidly. However, the breakdown voltage of the gatecathode junction limits this method. When the excess carrier concentration is low enough for carrier multiplication to cease, the device reverts to the forward blocking condition. At this point although the cathode current has stopped ﬂowing, anodetogate current continues to ﬂow supplied by the carriers from nbase region stored charge. This is observed as a tail current that decays exponentially as the remaining charge concentration is reduced by recombination process. The presence of this tail current with the combination of high GTO offstate voltage produces substantial power losses. During this transition period, the electric ﬁeld in the nbase region is grossly distorted due to the presence of the charge carriers and may result in premature avalanche breakdown. The resulting impact ionization can cause device failure. This phenomenon is known as “dynamic avalanche.” The device regains its steadystate blocking characteristics when the tail current diminishes to leakage current level.
Cathode emitter Gate
Cathode
p
pbase
n
nbase
p
pemitter Anode
G
C
(a) GTO symbol
(b) GTO structure FIGURE 7.1 GTO structure.
multiplication effects bring the GTO into conduction. This is shown in Fig. 7.2a. As with a conventional thyristor only the area of cathode adjacent to the gate electrode is turned on initially, and the remaining area is brought into conduction by plasma spreading. However, unlike the thyristor, the GTO consists of many narrow cathode elements, heavily interdigitated with the gate electrode, and therefore the initial turnedon area is very large and the time required for plasma spreading is small. The GTO, therefore, is brought into conduction very rapidly and can withstand a high turnon di/dt. In order to turnoff a GTO, the gate is reversed biased with respect to the cathode and holes from the anode are extracted from the pbase. This is shown in Fig. 7.2b. As a result a voltage drop is developed in the pbase region, which eventually reverse biases the gate cathode junction cutting off the injection of electrons. As the hole extraction continues, the pbase is further depleted, thereby squeezing the remaining conduction area. The anode current then ﬂows
7.3 GTO Thyristor Models Onedimensional twotransistor model of GTOs is shown in Fig. 7.3. The device is expected to yield the turnoff gain g given by Ag =
TURNON G
VFG
K
VFG
αnpn IA = IG αpnp + αnpn − 1
TURNOFF G
G
VFG
N+
K
VFG
G
N+
P
P Electrons P+
P+ P+
P+
Electrons Holes
(a) Turnon
(b) Turnoff FIGURE 7.2 Turnon and turnoff of GTOs.
Holes
(7.1)
7
117
Gate Turnoff Thyristors Anode
P
P
N Gate
The GTO remains in a transistor state if the load circuit limits the current through the shorts.
A
A
P
G
α pnp
N
N
P
P
N
G
α npn
N
C
Cathode
C
FIGURE 7.3 Twotransistor model representing the GTO thyristor.
where IA is the anode current and IG the gate current at turnoff, and α npn and α pnp are the commonbase current gains in the NPN and PNP transistors sections of the device. For a nonshorted device, the charge is drawn from the anode and regenerative action commences, but the device does not latch on (remain on when the gate current is removed) until αnpn + αpnp ≥ 1
(7.2)
This process takes a short period while the current and the current gains increase until they satisfy Eq. (7.2). For anodeshorted devices, the mechanism is similar but the anode short impairs the turnon process by providing a base–emitter short thus reducing the PNP transistor gain, which is shown in Fig. 7.4. The composite PNP gain of the emittershorted structure is given as follows 1 − Vbe αpnp (composite) = αpnp (7.3) RSanode where Vbe = emitter base voltage (generally 0.6 V for injection of carriers), and RS is the anode short resistance. The anode emitter injects when the voltage around it exceed 0.06 V, and therefore the collector current of the NPN transistor ﬂowing through the anode shorts inﬂuences turnon.
7.4 Static Characteristics 7.4.1 Onstate Characteristics In the onstate the GTO operates in a similar manner to the thyristor. If the anode current remains above the holding current level then positive gate drive may be reduced to zero and the GTO will remain in conduction. However, as a result of the turnoff ability of the GTO, it does posses a higher holding current level than the standard thyristor, and in addition, the cathode of the GTO thyristor is subdivided into small ﬁnger elements to assist turnoff. Thus, if the GTO thyristor anode current transiently dips below the holding current level, localized regions of the device may turnoff, thus forcing a high anode current back into the GTO at a high rate of rise of anode current after this partial turnoff. This situation could be potentially destructive. It is recommended, therefore, that the positive gate drive is not removed during conduction but is held at a value IG(ON ) , where IG(ON ) is greater than the maximum critical trigger current (IGT ) over the expected operating temperature range of the GTO thyristor. Figure 7.5 shows the typical onstate V–I characteristics for a 4000 A, 4500 V GTO from Dynex range of GTOs [1] at junction temperatures of 25◦ C and 125◦ C. The curves can be approximated to a straight line of the form VTM = V0 + IR 0
where V0 = voltage intercept, models the voltage across the cathode and anode forward biased junctions and R0 = on state resistance. When average and RMS values of onstate current (ITAV , ITRMS ) are known, then the onstate power dissipation PON can be determined using V0 and R0 . That is, 2 PON = V0 ITAV + R0 ITRMS
SYMMETRICAL GTO STRUCTURE
ASYMMETRICAL GTO STRUCTURE K
K K
G
K
G
G
G N+ Pbase
N+ Pbase
N
N
N+
P
N+
P
P A A
(7.4)
A
Anode shorted area
FIGURE 7.4 Twotransistor models of GTO structures.
N+
Rs A
(7.5)
118
M. H. Rashid
Instantaneous onstate current IT  (A)
4000
Measured under pulse conditions IGIONI = 10A Half sine wave 10ms
3000
TI = 25˚C
TI = 125˚C
2000
1000
0 1.0
1.5
2.0 2.5 3.0 Instantaneous onstate voltage VTM  (V)
3.5
4.0
FIGURE 7.5 V–I characteristics of GTO [see data sheet in Ref. 1].
7.4.2 Offstate Characteristics
7.4.4 Gate Triggering Characteristics
Unlike the standard thyristor, the GTO does not include cathode emitter shorts to prevent nongated turnon effects due to dv/dt induced forward biased leakage current. In the offstate of the GTO, steps should, therefore, be taken to prevent such potentially dangerous triggering. This can be accomplished by either connecting the recommended value of resistance between the gate and the cathode (RGK ) or by maintaining a small reverse bias on the gate contact (VRG = −2 V). This will prevent the cathode emitter becoming forward biased and therefore sustain the GTO thyristor in the off state. The peak offstate voltage is a function of resistance RGK . This is shown in Fig. 7.6. Under ordinary operating conditions, GTOs are biased with a negative gate voltage of around −15 V supplied from the gate drive unit during the offstate interval. Nevertheless, provision of RGK may be desirable design practice in the event of the gatedrive failure for any reason (RGK < 1.5 is recommended for a large GTO). RGK dissipates energy and hence adds to the system losses.
The gate trigger current (IGT ) and the gate trigger voltage (VGT ) are both dependent on junction temperature Tj as shown in Fig. 7.8. During the conduction state of the GTO a certain value of gate current must be supplied and this value should be larger than the IGT at the lowest junction temperature at which the GTO operates. In dynamic conditions the speciﬁed IGT is not sufﬁcient to trigger the GTO switching from higher voltage and high di/dt . In practice a much high peak gate current IGM (in order of ten times IGT ) at Tj min is recommended to obtain good turnon performance.
7.4.3 Rate of Rise of Offstate Voltage (dvT /dt) The rate of rise of offstate voltage (dvT /dt) depends on the resistance RGK connected between the gate and the cathode and the reverse bias applied between the gate and the cathode. This relationship is shown in Fig. 7.7.
7.5 Switching Phases The switching process of a GTO thyristor goes through four operating phases (a) turnon, (b) onstate, (c) turnoff, and (d) offstate. Turnon: A GTO has a highly interdigited gate structure with no regenerative gate. Thus it requires a large initial gate trigger pulse. A typical turnon gate pulse and its important parameters are shown in Fig. 7.9. A minimum and maximum values of IGM can be derived from the device data sheet. A value of dig /dt is given in device characteristics of the data sheet, against turnon time. The rate of rise of gate current, dig /dt will affect the device turnon losses. The duration of
7
119
Gate Turnoff Thyristors VD (V) 5000 VD (C)
4500
VD 4000 10 ms
t
10 ms
3500 VD 3000
RGK
T = 40˚C
125˚C
2500 2000 1500 1000 500 0 10
1
100
1000 RGK (Ω)
FIGURE 7.6 GTO blocking voltage vs. RGK [see data sheet in Ref. 1].
VD = 2250V
500
VD = 3000V 0 0.1
1.0 10 100 1000 Gate cathode resistance RGK  (Ohms)
Gate trigger voltage VGT  (V)
Ti = 125˚C
2.5
12.5
2.0
10.0
1.5
7.5
1.0
5.0 VGT
Gate trigger current IGT  (A)
Rate of rise of offstate voltage dv/dt (V/µs)
1000
2.5
0.5
FIGURE 7.7 dVD /dt vs. RGK [see data sheet in Ref. 1]. IGT
the IGM pulse should not be less than half the minimum on time given in data sheet ratings. A longer period will be required if the anode current di/dt is low such that IGM is maintained until a sufﬁcient level of anode current is established. Onstate: Once the GTO is turned on, forward gate current must be continued for the whole of the conduction period. Otherwise, the device will not remain in conduction during the onstate period. If large negative di/dt or anode current reversal occurs in the circuit during the onstate, then higher
0 50 25
0
25
50
75
0 100 125 150
Junction temperature TI  (˚C)
FIGURE 7.8 GTO trigger characteristics [see data sheet in Ref. 1].
values of IG may be required. Much lower values of IG are, however, required when the device has heated up. Turnoff: The turnoff performance of a GTO is greatly inﬂuenced by the characteristics of the gate turnoff circuit. Thus the characteristics of the turnoff circuit must match
120
M. H. Rashid
FIGURE 7.9 A typical turnon gate pulse [see data sheet in Ref. 2]. FIGURE 7.12 Gatecathode resistance, RGK [see data sheet in Ref. 2].
FIGURE 7.10 Anode and gate currents during turnoff [see data sheet in Ref. 2].
with the device requirements. Figure 7.10 shows the typical anode and gate currents during the turnoff. The gate turnoff process involves the extraction of the gate charge, the gate avalanche period and the anode current decay. The amount of the charge extraction is a device parameter and its value is not signiﬁcantly affected by the external circuit conditions. The initial peak turnoff current and turnoff time, which are important parameters of the turningoff process, depend on the external circuit components. The device data sheet gives typical values for IGQ . The turnoff circuit arrangement of a GTO is shown in Fig. 7.11. The turnoff current gain of a GTO is low, typically 6–15. Thus, for a GTO with a turnoff gain of 10, it will require a turnoff gate current of 10 A to turnoff an onstate of 100 A. A charged capacitor C is normally used to provide the required turnoff gate current. Inductor L limits the turnoff di/dt of the gate current through the circuit formed by R1 , R2 , SW1 , and L. The gate circuit supply voltage VGS should be selected to give the required value of VGQ . The values of R1 and R2 should also be minimized. Offstate period: During the offstate period, which begins after the fall of the tail current to zero, the gate should
ideally remain reverse biased. This reverse bias ensures maximum blocking capability and dv/dt rejection. The reverse bias can be obtained either by keeping SW1 closed during the whole offstate period or via a higher impedance circuit SW2 and R3 provided a minimum negative voltage exits. This higher impedance circuit SW2 and R3 must sink the gate leakage current. In case of a failure of the auxiliary supplies for the gate turnoff circuit, the gate may be in reverses biased condition and the GTO may not be able to block the voltage. To ensure blocking voltage of the device is maintained, then a minimum gatecathode resistance (RGK ) should be applied as shown in Fig. 7.12. The value of RGK for a given line voltage can be derived from the data sheet.
7.6 SPICE GTO Model A GTO may be modelled with two transistors shown in Fig. 7.3. However, a GTO model [3] consisting of two thyristors, which are connected in parallel, yield improved onstate, turnon, and turnoff characteristics. This is shown in Fig. 7.13 with four transistors. When the anode to cathode voltage, VAK is positive and there is no gate voltage, the GTO model will be in the offstate like a standard thyristor. If a positive voltage (VAK ) is applied to the anode with respect to the cathode and no gate
Anode
1
Q1
Q3 6 Gate 3
R3 10 ohms
R2 10 ohms
7
Q4 5
R1 10 ohms 2 Cathode
FIGURE 7.11 Turnoff circuit [see data sheet in Ref. 2].
4
FIGURE 7.13 Fourtransistor GTO model.
Q2
7
121
Gate Turnoff Thyristors
pulse applied, IB1 = IB2 = 0 and therefore IC1 = IC2 = 0. Thus no anode current will ﬂow, IA = IK = 0. When a small voltage is applied to the gate, then IB2 is nonzero and therefore both IC1 = IC2 = 0 are nonzero. Thus the internal circuit will conduct and there will a current ﬂow from the anode to the cathode. When a negative gate pulse is applied to the GTO model, the PNP junction near to the cathode will behave as a diode. The diode will be reverse biased since the gate voltage is negative with to the cathode. Therefore the GTO will stop conduction. When the anodetocathode voltage is negative, that is, the anode voltage is negative with respect to the cathode, the GTO model will act like a reverse biased diode. This is because the PNP transistor will see a negative voltage at the emitter and the NPN transistor will see a positive voltage at the emitter. Therefore both transistors will be in the offstate and hence the GTO will not conduct. The SPICE subcircuit description of the GTO model will be as follows .SUBCIRCUIT 1 *Terminal Q1 5 4
1
Q3 7 Q2 4
6 5
1 2
Q4 6 R1 7 R2 6 R3 3 .MODEL
7 2 5 10 ohms 4 10 ohms 7 10 ohms DMOD1
.MODEL DMOD2 .ENDS
2
3
; GTO Subcircuit deﬁnition
anode cathode gate DMOD1 PNP ; PNP transistor with model DMOD1 DMOD1 PNP DMOD2 NPN ; PNP transistor with model DMOD2 DMOD2 NPN
PNP ; Model statement for a PNP transistor NPN ; Model statement for an NPN transistor ; End of subcircuit deﬁnition
7.7 Applications GTO thyristors ﬁnd many applications such as in motor drives, induction heating [4], distribution lines [5], pulsed power [6], and Flexible AC transmission systems [7, 8].
References 1. Dynex semiconductor: Data GTO datasheets website: http://www. dynexsemi.com/products/power_search.cgi 2. Westcode semiconductor: Data GTO datasheets website: http:// www.westcode.com/wsgto.html 3. ElAmin, I.M.A. “GTO PSPICE Model and its applications,” The Fourth Saudi Engineering Conference, November 1995, vol. III, pp. 271–7. 4. Busatto, G., Iannuzzo, F., and Fratelli, L., “PSPICE model for GTOs,” Proceedings of Symposium on Power Electronics Electrical Drives. Advanced Machine Power Quality. SPEEDAM Conference. Sorrento, Italy, 3–5 June 1998, vol. 1, pp. 2/5–10. 5. Malesani, L. and Tenti, P. “Mediumfrequency GTO inverter for induction heating applications,” Second European Conference on Power Electronics and Applications. EPE. Proceedings, Grenoble, France, 22–24, September 1987, vol. 1, pp. 271–6. 6. Souza, L.F.W., Watanabe, E.H., and Aredes, M.A. “GTO controlled series capacitor for distribution lines,” International Conference on Large High Voltage Electric Systems. CIGRE’98, 1998. 7. Chamund, D.J. “Characterisation of 3.3 kV asymmetrical thyristor for pulsed power application,” IEE Symposium Pulsed Power 2000 (Digest No.00/053) pp. 35/1–4, London, UK, 3–4 May 2000. 8. Moore, P. and Ashmole, P. “Flexible AC transmission systems: 4. Advanced FACTS controllers,” Power Engineering Journal, vol. 12, no. 2, pp. 95–100, April 1998.
8 MOS Controlled Thyristors (MCTs) S. Yuvarajan, Ph.D. Department of Electrical Engineering, North Dakota State University, P.O. Box 5285, Fargo, North Dakota, USA
8.1 Introduction .......................................................................................... 123 8.2 Equivalent Circuit and Switching Characteristics .......................................... 124 8.2.1 Turnon and Turnoff
8.3 Comparison of MCT and other Power Devices ............................................ 125 8.4 Gate Drive for MCTs ............................................................................... 126 8.5 Protection of MCTs ................................................................................ 126 8.5.1 Paralleling of MCTs • 8.5.2 Overcurrent Protection
8.6 8.7 8.8 8.9 8.10 8.11
Simulation Model of an MCT ................................................................... 127 Generation1 and Generation2 MCTs........................................................ 127 Nchannel MCT ..................................................................................... 127 Base Resistancecontrolled Thyristor .......................................................... 127 MOS Turnoff Thyristor .......................................................................... 128 Applications of PMCT ............................................................................. 128 8.11.1 Softswitching • 8.11.2 Resonant Converters
8.12 Conclusions ........................................................................................... 130 8.13 Appendix .............................................................................................. 130 References ............................................................................................. 130
8.1 Introduction The efﬁciency, capacity, and ease of control of power converters depend mainly on the power devices employed. Power devices, in general, belong to either bipolarjunction type or ﬁeldeffect type and each one has its advantages and disadvantages. The silicon controlled rectiﬁer (SCR), also known as a thyristor, is a popular power device that has been used over the past several years. It has a high current density and a low forward voltage drop, both of which make it suitable for use in large power applications. The inability to turnoff through the gate and the low switching speed are the main limitations of an SCR. The gate turnoff (GTO) thyristor was proposed as an alternative to SCR. However, the need for a higher gate turnoff current limited its application. Copyright © 2007, 2001, Elsevier Inc. All rights reserved.
The power MOSFET has several advantages such as high input impedance, ease of control, and higher switching speeds. Lower current density and higher forward drop limited the device to lowvoltage and lowpower applications. An effort to combine the advantages of bipolar junction and ﬁeldeffect structures has resulted in hybrid devices such as the insulated gate bipolar transistor (IGBT) and the MOS controlled thyristor (MCT). While an IGBT is an improvement over a bipolar junction transistor (BJT) using a MOSFET to turnon and turnoff current, an MCT is an improvement over a thyristor with a pair of MOSFETs to turnon and turnoff current. The MCT overcomes several of the limitations of the existing power devices and promises to be a better switch for the future. While there are several devices in the MCT family with distinct combinations of channel and gate structures [1], 123
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S. Yuvarajan
one type, called the Pchannel MCT, has been widely reported and is discussed here. Because the gate of the device is referred to with respect to the anode rather than the cathode, it is sometimes referred to as a complementary MCT (CMCT) [2]. Harris Semiconductors (Intersil) originally made the MCTs, but the MCT division was sold to Silicon Power Corporation (SPCO), which has continued the development of MCTs.
Anode Metal
Metal Oxide
Oxide Gate
Gate
Gate n+ p
8.2 Equivalent Circuit and Switching Characteristics The SCR is a 4layer pnpn device with a control gate, and applying a positive gate pulse turns it on when it is forwardbiased. The regenerative action in the device helps to speed up the turnon process and to keep it in the “ON” state even after the gate pulse is removed. The MCT uses an auxiliary MOS device (PMOSFET) to turnon and this simpliﬁes the gate control. The turnon has all the characteristics of a power MOSFET. The turnoff is accomplished using
n+ p+
p
n(pnp base, OffFET drain)
p(npn base, OnFET drain)
p buffer, epitaxial layer
n+ substrate Metal
Cathode
K
Cathode
FIGURE 8.2 Cross section of an MCT unit cell.
Q1
Q2 Gate G Anode A
K
G
A
FIGURE 8.1 Equivalent circuit and symbol of an MCT.
another MOSFET (NMOSFET), which essentially diverts the base current of one of the BJTs and breaks the regeneration. The transistorlevel equivalent circuit of a Pchannel MCT and the circuit symbol are shown in Fig. 8.1. The cross section of a unit cell is shown in Fig. 8.2. The MCT is modeled as an SCR merged with a pair of MOSFETs. The SCR consists of the bipolar junction transistors (BJTs) Q1 and Q2 , which are interconnected to provide regenerative feedback such that the transistors drive each other into saturation. Of the two MOSFETs, the PMOS located between the collector and emitter of Q2 helps to turn the SCR on, and the NMOS located across the baseemitter junction of Q2 turns it off. In the actual fabrication, each MCT is made up of a large number (∼100,000) cells, each of which contains a widebase npn transistor and a narrowbase pnp transistor. While each pnp transistor in a cell is provided with an Nchannel MOSFET across its emitter and base, only a small percentage (∼4%) of pnp transistors are provided with Pchannel MOSFETs across their emitters and collectors. The small percentage of PMOS cells in an MCT provides just enough current for turnon and the large number of NMOS cells provide plenty of current for turnoff.
8
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MOS Controlled Thyristors (MCTs)
8.2.1 Turnon and Turnoff
8.3 Comparison of MCT and Other Power Devices An MCT can be compared to a power MOSFET, a power BJT, and an IGBT of similar voltage and current ratings. The operation of the devices is compared under onstate, offstate, and transient conditions. The comparison is simple and very comprehensive. The current density of an MCT is ≈70% higher than that of an IGBT having the same total current [2]. During its onstate, an MCT has a lower conduction drop compared to other devices. This is attributed to the reduced cell size and the absence of emitter shorts present in the SCR within the MCT. The MCT also has a modest negative temperature coefﬁcient at
Current density (A/sq.cm)
When the MCT is in the forward blocking state, it can be turned on by applying a negative pulse to its gate with respect to the anode. The negative pulse turns on the PMOSFET (OnFET) whose drain current ﬂows through the baseemitter junction of Q1 (npn) thereby turning it on. The regenerative action within Q1 – Q2 turns the MCT on into full conduction within a very short time and maintains it even after the gate pulse is removed. The MCT turns on without a plasmaspreading phase giving a high dI/dt capability and ease of overcurrent protection. The onstate resistance of an MCT is slightly higher than that of an equivalent thyristor because of the degradation of the injection efﬁciency of the N + emitter/pbase junction. Also, the peak current rating of an MCT is much higher than its average or rms current rating. An MCT will remain in the “ON” state until the device current is reversed or a turnoff pulse is applied to its gate. Applying a positive pulse to its gate turns off a conducting MCT. The positive pulse turns on the NMOSFET (OffFET), thereby diverting the base current of Q2 (pnp) away to the anode of the MCT and breaking the latching action of the SCR. This stops the regenerative feedback within the SCR and turns the MCT off. All the cells within the device are to be turned off at the same time to avoid a sudden increase in current density. When the OffFETs are turned on, the SCR section is heavily shorted and this results in a high dV/dt rating for the MCT. The highest current that can be turned off with the application of a gate bias is called the “maximum controllable current.” The MCT can be gate controlled if the device current is less than the maximum controllable current. For smaller device currents, the width of the turnoff pulse is not critical. However, for larger currents, the gate pulse has to be wider and more often has to occupy the entire offperiod of the switch.
1000
MCT
100
IGBT Power BJT
10 Power MOSFET
1.0 0.0
0.5
1.0 1.5 Conduction drop (Volts)
2.0
2.5
FIGURE 8.3 Comparison of forward drop for different devices.
lower currents with the temperature coefﬁcient turning positive at larger current [2]. Figure 8.3 shows the conduction drop as a function of current density. The forward drop of a 50A MCT at 25 ◦ C is around 1.1 V, while that for a comparable IGBT is over 2.5 V. The equivalent voltage drop calculated from the value of rDS (ON) for a power MOSFET will be much higher. However, the power MOSFET has a much lower delay time (30 ns) compared to that of an MCT (300 ns). The turnon of a power MOSFET can be so much faster than an MCT or an IGBT therefore, the switching losses would be negligible compared to the conduction losses. The turnon of an IGBT is intentionally slowed down to control the reverse recovery of the freewheeling diode used in inductive switching circuits [3]. The MCT can be manufactured for a wide range of blocking voltages. Turnoff speeds of MCTs are supposed to be higher as initially predicted. The turnon performance of Generation2 MCTs are reported to be better compared to Generation1 devices. Even though the Generation1 MCTs have higher turnoff times compared to IGBTs, the newer ones with higher radiation (hardening) dosage have comparable turnoff times. At present, extensive development activity in IGBTs has resulted in highspeed switched mode power supply (SMPS) IGBTs that can operate at switching speeds ≈150 kHz [4]. The turnoff delay time and the fall time for an MCT are much higher compared to a power MOSFET, and they are found to increase with temperature [2]. Power MOSFETs becomes attractive at switching frequencies above 200 kHz, and they have the lowest turnoff losses among the three devices. The turnoff safe operating area (SOA) is better in the case of an IGBT than an MCT. For an MCT, the full switching current is sustainable at ≈50 to 60% of the breakdown voltage rating, while for an IGBT it is about 80%. The use of capacitive snubbers becomes necessary to shape the turnoff locus
126
of an MCT. The addition of even a small capacitor improves the SOA considerably.
8.4 Gate Drive for MCTs The MCT has a MOS gate similar to a power MOSFET or an IGBT and hence it is easy to control. In a PMCT, the gate voltage must be applied with respect to its anode. A negative voltage below the threshold of the OnFET must be applied to turn on the MCT. The gate voltage should fall within the speciﬁed steadystate limits in order to give a reasonably low delay time and to avoid any gate damage due to overvoltage [3]. Similar to a GTO, the gate voltage risetime has to be limited to avoid hot spots (current crowding) in the MCT cells. A gate voltage less than −5 V for turnoff and greater than 10 V for turnon ensures proper operation of the MCT. The latching of the MCT requires that the gate voltage be held at a positive level in order to keep the MCT turned off. Because the peaktopeak voltage levels required for driving the MCT exceeds those of other gatecontrolled devices, the use of commercial drivers is limited. The MCT can be turned on and off using a push–pull pair with discrete NMOS– PMOS devices, which, in turn, are driven by commercial integrated circuits (ICs). However, some drivers developed by MCT manufacturers are not commercially available [3]. A Baker’s clamp push–pull can also be used to generate gate pulses of negative and positive polarity of adjustable width for driving the MCT [5–7]. The Baker’s clamp ensures that the push–pull transistors will be in the quasisaturated state prior to turnoff and this results in a fast switching action. Also, the negative feedback built into the circuit ensures satisfactory operation against variations in load and temperature. A similar circuit with a push–pull transistor pair in parallel with a pair of power BJTs is available [8]. An intermediate section, with a BJT that is either cut off or saturated, provides −10 and +15 V through potential division.
S. Yuvarajan
8.5.2 Overcurrent Protection The anodetocathode voltage in an MCT increases with its anode current and this property can be used to develop a protection scheme against overcurrent [5, 6]. The gate pulses to the MCT are blocked when the anode current and hence the anodetocathode voltage exceeds a preset value. A Schmitt trigger comparator is used to allow gate pulses to the MCT when it is in the process of turning on, during which time the anode voltage is relatively large and decreasing.
8.5.2.1 Snubbers As with any other power device, the MCT is to be protected against switchinginduced transient voltage and current spikes by using suitable snubbers. The snubbers modify the voltage and current transients during switching such that the switching trajectory is conﬁned within the safe operating area (SOA). When the MCT is operated at high frequencies, the snubber increases the switching loss due to the delayed voltage and current responses. The power circuit of an MCT chopper including an improved snubber circuit is shown in Fig. 8.4 [5, 7]. The turnon snubber consists of Ls and DLS and the turnoff snubber consists of Rs , Cs , and DCs . The seriesconnected turnon snubber reduces the rate of change of the anode current dIA /dt. The MCT does not support Vs until the current through the freewheeling diode reaches zero at turnon. The turnoff snubber helps to reduce the peak power and the total power dissipated by the MCT by reducing the voltage across the MCT when the anode current decays to zero. The analysis and design of the snubber and the effect of the snubber on switching loss and electromagnetic interference are given in References [5] and [7]. An alternative snubber conﬁguration for the two MCTs in an ac–ac converter has also been reported [8]. This snubber uses only one capacitor and one inductor for both the MCT switches (PMCT and NMCT) in a powerconverter leg.
DLs Ls
Df
R–L Load _
8.5 Protection of MCTs Rs
8.5.1 Paralleling of MCTs Similar to power MOSFETs, MCTs can be operated in parallel. Several MCTs can be paralleled to form larger modules with only slight derating of the individual devices provided the devices are matched for proper current sharing. In particular, the forward voltage drops of individual devices have to be matched closely.
Dcs Vs
Gate Cs +
FIGURE 8.4 An MCT chopper with turnon and turnoff snubbers.
8
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MOS Controlled Thyristors (MCTs)
8.6 Simulation Model of an MCT The operation of power converters can be analyzed using PSPICE and other simulation software. As it is a new device, models of MCTs are not provided as part of the simulation libraries. However, an appropriate model for the MCT would be helpful in predicting the performance of novel converter topologies and in designing the control and protection circuits. Such a model must be simple enough to keep the simulation time and effort at a minimum, and must represent most of the device properties that affect the circuit operation. The PSPICE models for Harris PMCTs are provided by the manufacturer and can be downloaded from the internet. However, a simple model presenting most of the characteristics of an MCT is available [9, 10]. It is derived from the transistorlevel equivalent circuit of the MCT by expanding the SCR model already reported the literature. The improved model [10] is capable of simulating the breakover and breakdown characteristics of an MCT and can be used for the simulation of highfrequency converters.
8.7 Generation1 and Generation2 MCTs The Generation1 MCTs were commercially introduced by Harris Semiconductors in 1992. However, the development of Generation2 MCTs is continuing. In Gen2 MCTs, each cell has its own turnon ﬁeldeffect transistor (FET). Preliminary test results on Generation2 devices and a comparison of their performance with those of Generation1 devices and highspeed IGBTs are available [11, 12]. The Generation2 MCTs have a lower forward drop compared to the Generation1 MCTs. They also have a higher dI/dt rating for a given value of capacitor used for discharge. During hard switching, the fall time and the switching losses are lower for the Gen2 MCTs. The Gen2 MCTs have the same conduction loss characteristics as Gen1 with drastic reductions in turnoff switching times and losses [13]. Under zerocurrent switching conditions, Gen2 MCTs have negligible switching losses [13]. Under zerovoltage switching, the turnoff losses in a Gen2 device are onehalf to onefourth (depending on temperature and current level) the turnoff losses in Gen1 devices. In all softswitching applications, the predominant loss, namely, the conduction loss, reduces drastically allowing the use of fewer switches in a module.
8.8 Nchannel MCT The PMCT discussed in this chapter uses an NMOSFET for turnoff and this results in a higher turnoff current capability.
The PMCT can only replace a Pchannel IGBT and inherits all the limitations of a Pchannel IGBT. The results of a 2D simulation show that the NMCT can have a higher controllable current [13]. It is reported that NMCT versions of almost all Harris PMCTs have been fabricated for analyzing the potential for a commercial product [3]. The NMCTs are also being evaluated for use in zerocurrent softswitching applications. However, the initial results are not quite encouraging in that the peak turnoff current of an NMCT is onehalf to onethird of the value achievable in a PMCT. It is hoped that the NMCTs will eventually have a lower switching loss and a larger SOA as compared to PMCTs and IGBTs.
8.9 Base Resistancecontrolled Thyristor [14] The base resistancecontrolled thyristor (BRT) is another gatecontrolled device that is similar to the MCT but with a different structure. The OffFET is not integrated within the pbase region but is formed within the nbase region. The diverter region is a shallow ptype junction formed adjacent to the pbase region of the thyristor. The fabrication process is simpler for this type of structure. The transistor level equivalent circuit of a BRT is shown in Fig. 8.5. The BRT will be in the forward blocking state with a positive voltage applied to the anode and with a zero gate bias. The forward blocking voltage will be equal to the breakdown voltage of the openbase pnp transistor. A positive gate bias turns on the BRT. At low current levels, the device behaves similarly to an IGBT. When the anode current increases, the operation changes to thyristor mode resulting
K
Cathode
R Gate G
A
Anode
FIGURE 8.5 Equivalent circuit of base resistancecontrolled thyristor (BRT).
128
S. Yuvarajan
in a low forward drop. Applying a negative voltage to its gate turns off the BRT. During the turnoff process, the anode current is diverted from the N + emitter to the diverter. The BRT has a current tail during turnoff that is similar to an MCT or an IGBT.
8.10 MOS Turnoff Thyristor [15] The MOS turnoff (MTO) thyristor or the MTOT is a replacement for the GTO and it requires a much smaller gate drive. It is more efﬁcient than a GTO, it can have a maximum blocking voltage of about 9 kV, and it will be used to build power converters in the 1–20 MVA range. Silicon Power Corporation (SPCO) manufactures the device. The transistorlevel equivalent circuit of the MTOT (hybrid design) and the circuit symbol are shown in Fig. 8.6. Applying a current pulse at the turnon gate (Gl), as with a conventional GTO, turns on the MTOT. The turnon action, including
K
Cathode
regeneration, is similar to a conventional SCR. Applying a positive voltage pulse to the turnoff gate (G2), as with an MCT, turns off the MTOT. The voltage pulse turns on the FET, thereby shorting the emitter and base of the npn transistor and breaking the regenerative action. The MTOT is a faster switch than a GTO in that it is turned off with a reduced storage time compared to a GTO. The disktype construction allows doubleside cooling.
8.11 Applications of PMCT The MCTs have been used in various applications, some of which are in the area of acdc and acac conversion where the input is 60 Hz ac. Variable power factor operation was achieved using the MCTs as a forcecommutated power switch [5]. The power circuit of an ac voltage controller capable of operating at a leading, lagging, and unity power factor is shown in Fig. 8.7. Because the switching frequency is low, the switching losses are negligible. Because the forward drop is low, the conduction losses are also small. The MCTs are also used in circuit breakers.
8.11.1 Softswitching
Turnon Gate G1 Turnoff Gate G2
The MCT is intended for highfrequency switching applications where it is supposed to replace a MOSFET or an IGBT. Similar to a Power MOSFET or an IGBT, the switching losses will be high at high switching frequencies. The typical characteristics of an MCT during turnon and turnoff under hard switching (without snubber) are shown in Fig. 8.8. During turnon and turn off, the device current and voltage take a ﬁnite time to reach their steadystate values. Each time the device changes state, there is a short period during which the voltage and current variations overlap. This results in a transient power loss that contributes to the average power loss. Softswitching converters are being designed primarily to enable operation at higher switching frequencies. In these
Anode
A
K M1
G2
G1
R–L load
Vac M2
A
FIGURE 8.6 Equivalent circuit and symbol of a MOS turnoff (MTO) thyristor.
FIGURE 8.7 Power circuit of MCT ac voltage controller.
8
129
MOS Controlled Thyristors (MCTs)
low and is close to that in a power diode with similar power ratings [12]. The Generation1 MCTs did not turn on rapidly in the vicinity of zero anodecathode voltage and this posed a problem in softswitching applications of an MCT. However, Generation2 MCTs have enhanced dynamic characteristics under zero voltage soft switching [16]. In an MCT, the PMOS OnFET together with the pnp transistor constitute a pIGBT. An increase in the number of turnon cells (decrease in the onresistance of the pIGBT) and an enhancement of their distribution across the MCT active area enable the MCT to turn on at a very low transient voltage allowing zero voltage switching (ZVS). During zero voltage turnon, a bipolar device such as the MCT takes more time to establish conductivity modulation. Before the device begins to conduct fully, a voltage spike appears, thus causing a modest switching loss [12]. Reducing the tailcurrent amplitude and duration by proper circuit design can minimize the turnoff losses in softswitching cases.
Vga
0
Vak
Ia 0 t Turnoff waveforms
8.11.2 Resonant Converters Resonant and quasiresonant converters are known for their reduced switching loss [17]. Resonant converters with zero current switching are built using MCTs and the circuit of one such, a buckconverter, is shown in Fig. 8.9. The resonant commutating network consisting of Lr , Cr , auxiliary switch Tr , and diode Dr enables the MCT to turn off under zero current. The MCT must be turned off during the conduction period of DZ . Commutating switch Tr must be turned off when the resonant current reaches zero. A resonant dc link circuit with twelve parallel MCTs has been reported [18]. In this circuit, the MCTs switch at zerovoltage instants. The elimination of the switching loss allows operation at higher switching frequencies, which in turn increases the power density and offers better control of the spectral content. The use of MCTs with the same forward drop provides good current sharing.
0
Vga
Ia
Vak 0
Dz t Turnon waveforms
FIGURE 8.8 The MCT turnoff and turnon waveforms under hard switching.
L1
Dr
converters, the power devices switch at zero voltage or zero current, thereby eliminating the need for a large safe operating area (SOA) and at the same time eliminating the switching losses entirely. The MCT converters will outperform IGBT and power MOSFET converters in such applications by giving the highest possible efﬁciency. In softswitching applications, the MCT will have only conduction loss, which is
Tr
MCT
Vin Cr
Lr
Load
Do
FIGURE 8.9 Power circuit of MCT resonant buck converter.
130
The MCTs are also used in acresonantlink converters with pulse density modulation (PDM) [19]. The advantages of the PDM converter, such as zerovoltage switching, combined with those of the MCT make the PDM converter a suitable candidate for many ac–ac converter applications. In an ac–ac PDM converter, a lowfrequency ac voltage is obtained by switching the high frequency ac link at zerocrossing voltages. Two MCTs with reverseconnected diodes form a bidirectional switch that is used in the circuit. A single capacitor was used as a simple snubber for both MCTs in the bidirectional switch.
S. Yuvarajan
Gate to Anode Voltage (Peak), VGAM Rate of Change of Voltage (VGA =15 V), dV/dt Rate of Change of Current, di/dt Peak Offstate Blocking Current (IDRM ) (VKA = −600 V VGA = +15 V, Tc = +25◦ C)v Onstate Voltage (VTM ) (IK = 100 A, VGA = −10VTc = +25◦ C)
±20 V 10 kV/ms 80 kA/m 200 mA 1.3 V
References 8.12 Conclusions The MCT is a power switch with a MOS gate for turnon and turnoff. It is derived from a thyristor by adding the features of a MOSFET. It has several advantages compared to modern devices like the power MOSFET and the IGBT. In particular, the MCT has a low forward drop and a higher current density which are required for highpower applications. The characteristics of Generation2 MCTs are better than those of Generation1 MCTs. The switching performance of Generation2 MCTs is comparable to the IGBTs. At one time, SPCO was developing both PMCTs and NMCTs. The only product that is currently under the product list of SPCO is the voltage/current controlled Solidtron, which is a discharge switch utlilizing an ntype MCT. The device features a high current and high dI/dt capability and is used in capacitor discharge applications. The data on Solidtron can be obtained at: http:// www.siliconpower.com/Solidtron/Solid_home.htm.
Acknowledgment The author is grateful to Ms. Jing He and Mr. Rahul Patil for their assistance in collecting the reference material for this chapter.
8.13 Appendix The following is a summary of the speciﬁcations on a 600 V/150 A PMCT made by SPC: Peak Offstate Voltage, VDRM −600 V Peak Reverse Voltage, VRRM +40V Continuous Cathode Current, (T = +90◦ C), IK90 150 A Nonrepetitive Peak Cathode Current, IKSM 5000 A Peak Controllable Current, IKC 300 A ±15V Gate to Anode Voltage (Continuous), VGA
1. V. A. K. Temple, “MOSControlled Thyristors — A new class of power devices,” IEEE Trans. on Electron Devices 33: 1609–1618 (1986). 2. T. M. Jahns, R. W. A. A. De Doncker, J. W. A. Wilson, V. A. K. Temple, and D. L. Waltrus, “Circuit utilization characteristics of MOSControlled Thyristors,” IEEE Trans. on Industry Applications 27:3, 589–597 (May/June 1991). 3. Harris Semiconductor, MCT/IGBTs/Diodes Databook, 1995. 4. P. Holdman and F. Lotuka, “SMPS IGBTs — High switching frequencies allow efﬁcient switchers,” PCIM Power Electronics Systems 25:2, 38–2 (February 1999). 5. D. Quek, Design of Protection and Control Strategies for Lowloss MCT Power Converters, Ph.D. Thesis, North Dakota State University, July 1994. 6. D. Quek and S. Yuvarajan, “A novel gate drive for the MCT incorporating overcurrent protection,” Proc. of IEEE IAS Annual Meeting 1994, pp. 1297–1302. 7. S. Yuvarajan, R. Nelson, and D. Quek, “A study of the effects of snubber on switching loss and EMI in an MCT converter,” Proc. of IEEE IAS Annual Meeting 1994, pp. 1344–1349. 8. T. C. Lee, M. E. Elbuluk, and D. S. Zinger, “Characterization and snubbing of a bidirectional MCT switch in a resonant ac link converter,” IEEE Trans. Industry Applications 31:5, 978–985 (Sept./Oct. 1995). 9. S. Yuvarajan and D. Quek, “A PSPICE model for the MOS Controlled Thyristor,” IEEE Trans, on Industrial Electronics 42:5, 554–558 (Oct. 1995). 10. G. L. Arsov and L. P. Panovski, “An improved PSPICE model for the MOSControlled Thyristor,” IEEE Trans. Industrial Electronics 46:2, 473–477 (April 1999). 11. P. D. Kendle, V. A. K. Temple, and S. D. Arthur, “Switching com parison of Generation1 and Generation2 PMCTs and ultrafast NIGBTs,” Proc. of IEEE IAS Annual Meeting 1993, pp. 1286–1292. 12. E. Yang, V. Temple, and S. Arthur, “Switching loss of Gen1 and Gen 2 PMCTs in softswitching circuits,” Proc. of IEEE APEC 1995, pp. 746–754. 13. Q. Huang, G. A. J. Amaratunga, E. M. Sankara Narayanan, and W. I. Milne, “Analysis of nchannel MOSControlled Thyristors,” IEEE Trans. Electron Devices 38:7, 1612–1618 (1991). 14. B. Jayant Baliga, Power Semiconductor Devices, PWS Publishing Co., Boston, 1996. 15. R. Rodrigues, A. Huang, and R. De Doncker, “MTO Thyristor Power Switches,” Proc. of PCIM’97 Power Electronics Conference 1997, pp. 41–412.
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16. R. W. A. A. De Doncker, T. M. Jahns, A. V. Radun, D. L. Waltrus, and V. A. K. Temple, “Characteristics of MOSControlled Thyristors under zero voltage softswitching conditions,” IEEE Trans. Industry Applications 28:2, 387–394 (March/April 1992). 17. A. Dmowski, R. Bugyi, and P. Szewczyk, “Design of a buck converter with zerocurrent turnoff MCT,” Proc. IEEE IAS Annual Meeting 1994, pp. 1025–1030.
131 18. H.R. Chang and A. V. Radun, “Performance of 500 V, 450 A Parallel MOS Controlled Thyristors (MCTs) in a resonant dclink circuit,” Proc. IEEE IAS Annual Meeting 1990, pp. 1613–1617. 19. M. E. Elbuluk, D. S. Zinger, and T. Lee, “Performance of MCT’s in a currentregulated ac/ac PDM converter,” IEEE Trans. Power Electro nics 11:1, 49–56 (January 1996).
9 Static Induction Devices Bogdan M. Wilamowski, Ph.D. Alabama Microelectronics Science and Technology Center, Auburn University, Alabama, USA
9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 9.10 9.11 9.12 9.13 9.14
Summary .............................................................................................. 133 Introduction .......................................................................................... 133 Theory of Static Induction Devices............................................................. 133 Characteristics of Static Induction Transistor ............................................... 134 Bipolar Mode Operation of SI devices (BSIT) .............................................. 136 Emitters for Static Induction Devices.......................................................... 136 Static Induction Diode ............................................................................. 137 Lateral Punchthrough Transistor .............................................................. 137 Static Induction Transistor Logic ............................................................... 137 BJT Saturation Protected by SIT ................................................................ 138 Static Induction MOS Transistor ............................................................... 138 Space Charge Limiting Load (SCLL)........................................................... 140 Power MOS Transistors ........................................................................... 140 Static Induction Thyristor ........................................................................ 142 Gate Turn Off Thyristor........................................................................... 142 References ............................................................................................. 142
Summary Several devices from the static induction family such as: static induction transistor (SIT), static induction diode (SID), static induction thyristor, lateral punchthrough transistor (LPTT), static induction transistor logic (SITL), static induction MOS transistor (SIMOS), and space charge limiting load (SCLL) are described. The theory of operation of static induction devices is given for both a current controlled by a potential barrier and a current controlled by space charge. The new concept of a punchthrough emitter (PTE), which operates with majority carrier transport, is presented.
9.1 Introduction Static induction devices were invented in 1975 by J. Nishizawa [1] and for many years Japan was the only country where static induction family devices were successfully fabricated. Static induction transistor can be considered as a short channel junction ﬁeld effect transistor (JFET) device operating in prepunchthrough region. The number of devices in this family is growing with time. The SIT can operate with the Copyright © 2007, 2001, Elsevier Inc. All rights reserved.
power over 100 kW at 100 kHz; above 150 W at 3 GHz. [2]. These devices may operate upto THz frequencies [3, 4]. Static induction transistor logic had 100 times smaller switching energy than its I2 L competitor [5, 6]. Static induction thyristor has many advantages over the traditional silicon controlled rectiﬁer (SCR), and SID exhibits high switching speed, large reverse voltage, and low forward voltage drops [7].
9.2 Theory of Static Induction Devices The cross section of the SIT is shown in Fig. 9.1, while its characteristics are shown in Fig. 9.2. An induced electrostatically potential barrier controls the current in static induction devices. The derivations of formulas will be done for an nchannel device, but the obtained results, with a little modiﬁcation can also be applied to pchannel devices. For a small electrical ﬁeld existing in the vicinity of the potential barrier, the drift and diffusion current can be approximated by Jn = −qn(x)µn
dϕ(x) dn(x) + qDn dx dx
(9.1) 133
134
B. M. Wilamowski
Eq. (9.3) reduces to
source n+ p+
p+
n–
n–
p+
Jn = p+
p+
gate
qDn NS x2
(9.5)
exp −ϕ(x)/VT dx
x1
n–
Note that the above equations derived for SIT can also be used to ﬁnd current in any devices controlled by a potential barrier, such as a bipolar transistor, MOS transistor operation in subthreshold mode, or in a Schottky diode.
n+ drain FIGURE 9.1 Cross section of the static induction transistor.
0
IDS [mA]
9.3 Characteristics of Static Induction Transistor –1 –2
–3
–4
Samples of the potential distribution in the SI devices are shown in Fig. 9.3 [7]. The vicinity of the potential barrier can be approximated using parabolic formulas (Fig. 9.4) along and across the channel [8, 9].
VGS
–6
600
–8
400
x 2 ϕ(x) = 1 − 2 − 1 L
–15 –20
(9.6)
–25
200
VDS 200
400
600
800
[V]
FIGURE 9.2 Characteristics of the early SIT design [1].
where Dn = µn VT and VT = kT /q. By multiplying both sides of the equation by exp −ϕ(x)/VT and rearranging Jn exp −
ϕ(x) VT
= qDn
ϕ(x) d n(x) exp − dx VT
20 0 –20 –40 –60 –80 –100 0
(9.2)
n(x2 ) exp −ϕ(x2 )/VT − n(x1 ) exp −ϕ(x1 )/VT Jn = qDn x2 exp −ϕ(x)/VT dx x1
(9.3)
(a)
20 0 –20 –40 –60 –80 –100 0
With the following boundary conditions n(x1 ) = NS
ϕ(x2 ) = VD ;
n(x2 ) = ND
20 30
Integrating from x1 to x2 one can obtain
ϕ(x1 ) = 0;
10
10
20
30
40
40 0
50 40
10
30
20
20
30
40
10
50
0
(b) (9.4)
FIGURE 9.3 Potential distribution in SIT: (a) view from the source side and (b) view from the drain side.
9
135
Static Induction Devices
where L is the channel length and vsat ≈ 1011 µm/s is the carrier saturation velocity. In practical devices, the current– voltage relationship is described by an exponential relationship, Eq. (9.9), for small currents, a quadratic relationship, Eq. (9.11), and ﬁnally for large voltages by an almost linear relationship, Eq. (9.12). Static induction transistor characteristics drawn in linear and logarithmic scales are shown in Figs. 9.5 and 9.6, respectively.
W Φ 2Φ
Φ L
FIGURE 9.4 Potential distribution in the vicinity of the barrier approximated by parabolic shapes.
2 y −1 ϕ(y) = 1 − 2 W
0 –2 –4 –6 IDS
(9.7)
–8
–10 –12
[mA]
–14
500
Integrating Eq. (9.5) ﬁrst along the channel and then across the channel, yields a very simple formula for drain currents in nchannel SITs ID = qDp NS Z
W exp L VT
(9.8)
–16
400 VG=–18 300
200
where is the potential barrier height in reference to the source potential, NS is the electron concentration at the source, W/L ratio describes the shape of the potential saddle in vicinity of the barrier, and Z is the length of the source strip. Since barrier height can be a linear function of gate and drain voltages; therefore, ID = qDp NS Z
W exp a VGS + bVDS + 0 /VT L
20
40
60
80
100
120
[V]
FIGURE 9.5 Characteristics of the SIT drawn in a linear scale.
IDS 0–1–2 –3 –4 –5 [A] –6 –7
–9
10–1
–11 –13
10–2
VG=–15
(9.10)
where A is the effective device cross section and v(x) is carrier velocity. For a small electrical ﬁeld v(x) = µE(x) and the solution of Eq. (9.10) is 9 2 A µεSi ε0 3 IDS = VDS 8 L
VDS
(9.9)
The above equation describes characteristics of SIT for small current range. For large current levels, the device current is controlled by the space charge of moving carriers. In the onedimensional case, the potential distribution is described by the Poisson equation: d 2ϕ ρ(x) IDS =− = dx2 εSi ε0 Av(x)
100
(9.11)
10–3 10–4 10–5 10–6 10–7
and for a large electrical ﬁeld v(x) = const and Eq. (9.10) results in: 20
IDS
A = 2VDS vsat εSi ε0 2 L
(9.12)
40
60
80
100
120
140 VDS [V]
FIGURE 9.6 Characteristics of the SIT drawn in a logarithmic scale.
136
B. M. Wilamowski
9.4 Bipolar Mode Operation of SI devices (BSIT)
IDS [µA]
Jn =
x2 x1
qDn NS dx exp − ϕ(x) VT
NB (x)NS ϕ(x) = VT ln ni2
IDS [µA]
VBE exp − VT
0
µA 5µ A 2µ A
I
G=
10
50 40 µA µA 30 µA 20 µA
I
50
2
(9.13)
4 VDS [V]
4
FIGURE 9.8 Small size SIT transistor characteristics, operating in both the normal and bipolar modes, ID = f (VDS ) with IG as a parameter.
where ϕ(x) is the proﬁle of the potential barrier along the channel. For example, in the case of npn bipolar transistors, the potential distribution across the base in reference to emitter potential at the reference impurity level NE = NS is described by:
100
G=
The bipolar mode of operation of SIT was ﬁrst reported in 1976 by Nishizawa and Wilamowski [5, 6]. Several complex theories for the bipolar mode of operation were developed [10–14], but actually the simple formula given by Eq. (9.5) works well not only for the typical mode of the SIT operation, but also for the bipolar mode of the SIT operation. Furthermore, the same formula works very well for the classical bipolar transistors. Typical characteristics of the SI transistor operating in normal and in bipolar modes are shown in Figs. 9.7 and 9.8. A potential barrier controls the current in the SIT and it is given by
After inserting Eq. (9.14) into Eq. (9.13), one can obtain the wellknown equation for electron current injected into the base Jn =
x2
qDn ni2
exp
NB (x)dx
VBE VT
(9.15)
x1
(9.14)
VGS=0.75V
If Eq. (9.13) is valid for SIT and BJT, then one may assume that it is also valid for the bipolar mode of operation of the SIT transistor. This is a wellknown equation for the collector current in the bipolar transistor, but this time it was derived using the concept of the current ﬂow through the potential barrier.
VGS=0.7V
9.5 Emitters for Static Induction Devices
VGS=0.65V 100 6V
0.
V 0.5 0.4V V 0.3 V 0 V .5 –0 –1V V –2 V –3
50
2
4
VDS [V]
FIGURE 9.7 Small size SIT transistor characteristics, operating in both the normal and bipolar modes, ID = f (VDS ) with VGS as a parameter.
One of the disadvantages of the SIT is the relatively ﬂat shape of the potential barrier (Fig. 9.9a). This leads to slow, diffusionbased transport of carriers in the vicinity of the potential barrier. The carrier transit time can be estimated using the formula: ttransit =
2 leff
D
(9.16)
where leff is the effective length of the channel and D = µVT is the diffusion constant. In the case of a traditional SIT transistor, this channel length is about 2 µm while in the case of SIT transistors with sharper barriers (Fig. 9.9b) the channel length is reduced to about 0.2 µm. The corresponding transient times are 2 ns and 20 ps, respectively.
9
137
Static Induction Devices
20
n–
p
10 0
(a)
–10 –20 –30 0
10
20 30
40 0
5
10
15
20
25
n–
(a) (b) 20
n+ p
10
n–
0 –10 –20 –30 0
(c) 10
20
30
40 0
5
10
15
20
25
FIGURE 9.10 Various structures of emitters: (a) p–n junction including heterostructure with SiGe materials; (b) Schottky junction; and (c) punchthrough emitter (in normal operation condition the p region is depleted from carriers).
(b) FIGURE 9.9 Potential distributions in SIT: (a) traditional and (b) with sharp potential barrier.
Potential distributions shown in Fig. 9.3 are valid for SIT with an emitter made of a traditional p–n junction. A much narrower potential barrier can be obtained when other type of emitter is being used. There are two wellknown emitters: (1) p–n junction (Fig. 9.10a) and (2) Schottky junction (Fig. 9.10b). For silicon devices, p–n junctions have a forward voltage drop of 0.7–0.8 V, while Schottky emitters have 0.2–0.3 V only. Since the Schottky diode is a majority carrier device, the carrier storage effect is negligible. Another interesting emitter structure is shown in Fig. 9.10c. This emitter has all the advantages of the Schottky diode, with majority carrier injection, even though it is fabricated out of p–n junctions. The concept of static induction devices can be used independently of the type of emitter shown in Fig. 9.10. With Schottky type and punchthrough type emitters, the potential barrier is much narrower and this results in faster response time and larger current gain in the bipolar mode of operation.
9.6 Static Induction Diode The bipolar mode of operation of SIT can also be used to obtain diodes with low forward voltage drop and negligible carrier storage effect [10, 11, 13, 15]. A static induction
diode (SID) can be obtained by shorting a gate to the emitter of the SIT [16, 17]. Such diode has all the advantages of the SIT such as thermal stability and short switching time. The cross section of such diode is shown in Fig. 9.11. The quality of the SID can be further improved with more sophisticated emitters (Figs. 9.10b and c). The SI diode with Schottky emitter was described by Wilamowski in 1983 [18] (Fig. 9.12). A similar structure was later published by Baliga [19].
9.7 Lateral Punchthrough Transistor Fabrications of SI transistors usually require very sophisticated technology. It is much simpler to fabricate a lateral punchthrough transistor, which operates on the same principle and has similar characteristics [20] (Fig. 9.14). The cross section of the LPTT is shown in Fig. 9.13.
9.8 Static Induction Transistor Logic The static induction transistor logic (SITL) was proposed by Nishizawa and Wilamowski [5, 6]. This logic circuit has almost 100 times better powerdelay product than its I2 L competitor. Such drastic improvement of the powerdelay product is possible because the SITL structure has a signiﬁcantly smaller junction parasitic capacitance and also the voltage swing
138
B. M. Wilamowski
SIT
SIT
Schottky
(a) (a)
cathode anode
p
p
p
n+
p
p
n– n+ anode
(b) n–
cathode p
p
p
p
p
p
p
p
p
p
emitter n– cathode
(b) FIGURE 9.11 Static induction diode: (a) circuit diagram and (b) cross section.
n+ anode
(c)
FIGURE 9.12 Schottky diode with enlarged breakdown voltages: (a) circuit diagram; (b) and (c) two cross section of possible implementation.
is reduced. Figs. 9.15 and 9.16 illustrate the concept of SITL. Measured characteristics of nchannel transistor of the static induction logic are shown in Fig. 9.17. n+
p
n+
(a)
The SI transistor can also be used instead of a Schottky diode to protect a bipolar junction transistor against saturation [21]. This leads to faster switching time. The concept is shown in Figs. 9.18 and 9.19. Note that this approach is advantageous to the solution with Schottky diode, since it does not require additional area on a chip and it does not introduce additional capacitance between the base and the collector. The base collector capacitance is always enlarged by the Miller effect and this leads to slower switching in the case of the solution with the Schottky diode.
9.10 Static Induction MOS Transistor The punchthrough transistor with MOScontrolled gate was described in 1983 [22, 23]. In the structure in Fig. 9.20a current
–
p
9.9 BJT Saturation Protected by SIT
Drain
p
Gate
n+ –
p+
n
(b)
Drain
n+
p
–
Gate
Emitter
n+ p
Emitter
Gate
p+
Drain
n+ –
n
Gate
Drain
FIGURE 9.13 Structures of the lateral punchthrough transistors: (a) simple and (b) with sharper potential barrier.
can ﬂow in a similar fashion as in the lateral punchthrough transistor [20]. In this mode of operation, carriers are moving far from the surface with a velocity close to the saturation velocity. The real advantage of such structure is the very low gate capacitance.
9
139
Static Induction Devices
ID
[mA]
ID
T=298K
1mA
T=400K
V –6 V V
6V
–1 – 1 4V
2V
–1 –1 0V
–8
1
VGS 0V to 0.8V with 0.1V step
V –4
–2
V
G =0
V
2
VDS 1V [V]
20
40
FIGURE 9.17 Measured characteristics of nchannel transistor of the logic circuit of Fig. 9.16.
VDS
60
FIGURE 9.14 Characteristics of lateral punchthrough transistor.
C Schottky
C B
p
p
n+
p
n+
p
n+
SIT
B
n–
(a)
n+
FIGURE 9.15 Cross section of SIT logic.
(b)
E
FIGURE 9.18 Protection of bipolar transistor against deep saturation: (a) using Schottky diode and (b) using SIT.
supply current
B
out1
out2
E
out3
p
p n+
n– p
in
E
C
n+
n+ –
p
n n+
p
FIGURE 9.19 Cross sections of bipolar transistors protected against deep saturation using SIT. FIGURE 9.16 Diagrams of SIT logic.
Another implementation of static induction MOS transistor (SIMOS) is shown in Fig. 9.21. The buried p+ layer is connected to the substrate, which has a large negative potential. As a result, the potential barrier is high and the emitter–drain current cannot ﬂow. The punchthrough current may start to ﬂow when the positive voltage is applied to the gate and in this way the potential barrier is lowered. The pimplant layer is depleted and due to the high horizontal electrical ﬁeld under
the gate there is no charge accumulation under this gate. Such a transistor has several advantages over the traditional MOS transistor. 1. The gate capacitance is very small, since there is no accumulation layer under the gate. 2. Carriers are moving with a velocity close to saturation velocity. 3. Much lower substrate doping and the existing depletion layer lead to much smaller drain capacitance.
140
B. M. Wilamowski –
–
p implant ga
te
p + ga
te
p
n+
n+
n+
n+
n+ n+
p+ depletion
n+
depletion
p–
Emitter Emitter
Drain
p–
Drain
(a)
(a)
Gate
ga
te
+
–
p
p n+
n+
n
n n+
n+ depletion
Emitter
n
p–
Drain
(b) Emitter
FIGURE 9.20 MOS controlled punchthrough transistor: (a) transistor in the punchthrough mode for the negative gate potential and (b) transistor in the onstate for the positive gate potential.
The device operates in a similar fashion as MOS transistor in subthreshold conditions, but this process occurs at much higher current levels. Such “bipolar mode” of operation may have many advantages in VLSI applications.
9.11 Space Charge Limiting Load (SCLL) Using the concept of the space charge limited current ﬂow it is possible to fabricate very large resistors on a very small area. Moreover these resistors have a very small parasitic capacitance. For example, a 50 k resistor requires only several square µm when 2 µm feature size technology is used [7]. Depending on the value of the electrical ﬁeld, the device current is described by the following two equations. For a small electrical ﬁeld v(x) = µE(x) A 9 2 IDS = VDS µεSi ε0 3 8 L
(9.17)
For a large electrical ﬁeld v(x) = const IDS = 2VDS vsat εSi ε0
A L2
(9.18)
Drain
(b) FIGURE 9.21 Static induction MOS structure: (a) cross section and (b) top view.
n+
n+ n+
p–
n+
FIGURE 9.22 Space charge limiting load (SCLL).
Moreover these resistors, which are based on the space charge limit ﬂow, have a very small parasitic capacitance.
9.12 Power MOS Transistors Power MOS transistors are being used for fast switching power supplies and for switching power converters. They can be driven with relatively small power and switching frequencies could be very high. High switching frequencies lead to compact circuit implementations with small inductors and small capacitances. Basically only two technologies, DMOS and VMOS, are used for power MOS devices as shown in Figs. 9.23 and 9.24.
9
141
Static Induction Devices source n+ p
gate
source n+ p
gate
gate
n– n+ drain
FIGURE 9.23 Cross section of the VMOS transistor.
source
poly gate
n+
poly gate
n+
p
n+
n+
p
p
n–
n– n+ drain
FIGURE 9.24 Cross section of the DMOS transistor.
A more popular structure is the DMOS shown in Fig. 9.24. This structure also uses the SIT concept. Note that for large drain voltages the nregion is depleted from carriers and statically induced electrical ﬁeld in the vicinity of the virtual drain is signiﬁcantly reduced. As a result this transistor may withstand much larger drain voltages and also the effect of channel length modulation is signiﬁcantly reduced. The later effect leads to larger output resistances of the transistor. Therefore, the drain current is less sensitive to drain voltage variations. The structure in Fig. 9.24 can be considered as a composition of the MOS transistor and the SIT transistor as is shown in Fig. 9.25.
The major disadvantage of power MOS transistors is relatively large drain series resistance and much smaller transconductance in comparison to bipolar transistors. Both of these parameters can be improved dramatically by a simple change of the type of drain. In the case of nchannel device from ntype to ptype drain. This way the integrated structure is being built where its equivalent diagram consists MOS transistor integrated with bipolar transistor. Such structure has β times larger transconductance (β is the current gain of bipolar transistor) and much smaller series resistance due to the conductivity modulation effect caused by holes injected into lightly doped drain region. Such device is known as insulated gate bipolar transistors (IGBT) shown in Fig. 9.26. Their main disadvantage is large switching time limited primarily by poor switching performance of bipolar transistor. Another difﬁculty is related to a possible latchup action of four layer n+ pn− p+ structure. This undesired effect could be suppressed by using heavily doped p+ region in the base of NPN structure, which leads to signiﬁcant reduction of the current gain of this parasitic transistor. The gain of other PNP transistor must be kept large so the transconductance of the entire device is large too. The IGBT transistor has breakdown voltages up to 1500 V, turnoff times are in range 0.1–0.5 µs. They may operate with currents above 100 A with a forward voltage drop about 3 V.
source
poly gate
n+
n+
p
p+
poly gate
n+
n+
p
p
p+
p+
n–
n– p+ drain
(a) D
C
PNP SIT
G G
MOS
NPN RP
S
FIGURE 9.25 Equivalent diagram with MOS and SIT of the structure of Fig. 9.24.
(b)
E
FIGURE 9.26 Insulated gate bipolar transistor (IGBT): (a) cross section and (b) equivalent diagram.
142
B. M. Wilamowski
9.13 Static Induction Thyristor
anode p+
There are several special semiconductor devices dedicated to high power applications. The most popular is thyristor known also as silicon control rectiﬁer (SCR). This device has a four layer structure Fig. 9.27a and it can be considered as two transistors npn and pnp connected as shown in Fig. 9.27b. In normal mode of operation (anode has positive potential) only one junction is reversebiased and it can be represented by capacitance C. A spike of anode voltage can therefore get through capacitor C and it can trigger SCR. This behavior is not acceptable in practical application and therefore a different device structure is being used as is shown in Fig. 9.28. Note that by shorting gate to cathode by resistor R it is much more difﬁcult to trigger the npn transistor by spike of anode voltage. This way rapid change of anode voltages is not able to trigger thyristor. Therefore this structure has very large dv/dt parameter. When NPN transistor is replaced with SI transistor parameters of a thyristor can be signiﬁcantly improved. For example, with breaking voltage in the range of 5 kV and current of 600 A the switching on time can be as short as 100 ns and dv/dt parameter can be as large as 50 kV/s [15, 24]. Most of the SCRs sold in the market comprise an integrated structure composed of two or more thyristors. This structure
anode p+ pnp n–
C
p
gate
p
p n+
p n+
n+
n+
n+
(a) cathode
(b)
FIGURE 9.29 Integrated structure of silicon control rectiﬁer: (a) cross section and (b) equivalent diagram.
anode
p+ pnp
n p
gate
–
p
p
SIT
n+ cathode
(a)
(b)
FIGURE 9.30 GTO–SIT: (a) cross section and (b) equivalent diagram.
has both large dv/dt and di/dt parameters. This structure consists of internal thyristor which signiﬁcantly ampliﬁes the gate signal. One can notice that the classical thyristor as shown in Fig. 9.27 can be turned off by the gate voltage while integrated SCR shown in Fig. 9.29 can be only turned off by reducing anode current to zero. Most of the SCRs sold in the market have an integrated structure composed of two or more thyristors. This structure has both large dv/dt and di/dt parameters.
9.14 Gate Turn Off Thyristor
(a)
(b)
FIGURE 9.27 Silicon control rectiﬁer: (a) cross section and (b) equivalent diagram.
anode p+ pnp n–
C
p gate
gate
npn
n+ cathode
n–
For the dc operation it is important to have a thyristor which can be turned off by the gate voltage. Such thyristor has a structure similar to the one shown in Fig. 9.27. It is important, however, to have signiﬁcantly different current gains β for pnp and npn transistors. The current gain of npn transistor should be as large as possible and the current gain of pnp transistor should be small. The product of βnpn and βpnp should be larger than one. This can be easily implemented using SI structure as shown in Fig. 9.30.
npn n+
n+
(a)
R
n+ cathode
(b)
FIGURE 9.28 Silicon control rectiﬁer with larger dv/dt parameter: (a) cross section and (b) equivalent diagram.
References 1. Nishizawa J., Terasaki T., and Shibata J., “FieldEffect Transistor versus Analog Transistor (Static Induction Transistor),” IEEE Trans. on Electron Devices, vol. 22, No. 4, pp. 185–197, April 1975.
9
Static Induction Devices
2. Tatsude M., Yamanaka E., and Nishizawa J., “HighFrequency HighPower Static Induction Transistor,” IEEE Industry Application Magazine, pp. 40–45, March/April 1995. 3. Nishizawa J., Plotka P., and Kurabayashi T., “Ballistic and Tunneling GaAs Static Induction Transistors: NanoDevices for THz Electronics,” IEEE Trans. on Electron Devices, vol. 49, No. 7, pp. 1102–1111, 2002. 4. Nishizawa J., Suto K., and Kurabayashi T., “Recent Advance in Tetrahertz Wave and Material Basis,” Russian Physics Journal, vol. 46, No. 6, pp. 615–622, 2003. 5. Nishizawa J. and Wilamowski B. M., “Integrated Logic – State Induction Transistor Logic,” International Solid State Circuit Conference, Philadelphia USA, pp. 222–223, 1977. 6. Nishizawa J. and Wilamowski B. M., “Static Induction Logic – A Simple Structure with Very Low Switching Energy and Very High Packing Density,” International Conference on Solid State Devices, Tokyo, Japan, pp. 53–54, 1976 and Journal of Japanese Soc. Appl. Physics, vol. 16, No. 1, pp. 158–162, 1977. 7. Wilamowski B. M., “High Speed, High Voltage, and Energy Efﬁcient Static Induction Devices,” 12 Symposium of Static Induction Devices – SSID’99, (invited speech) Tokyo, Japan, pp. 23–28, April 23, 1999. 8. Plotka P. and Wilamowski B. M., “Interpretation of Exponential Type Drain Characteristics of the SIT,” SolidState Electronics, vol. 23, pp. 693–694, 1980. 9. Plotka P. and Wilamowski B. M., “Temperature Properties of the Static Induction Transistor,” SolidState Electronics, vol. 24, pp. 105–107, 1981. 10. Kim C. W., Kimura M., Yano K., Tanaka, A., and Sukegawa, T., “BipolarMode Static Induction Transistor: Experiment and TwoDimensional Analysis,” IEEE Trans. on Electron Devices, vol. 37, No. 9, pp. 2070–2075, September 1990. 11. Nakamura Y., Tadano H., Takigawa M., Igarashi I., and Nishizawa J., “Experimental Study on Current Gain of BSIT,” IEEE Trans. on Electron Devices, vol. 33, No. 6, pp. 810–815, June 1986. 12. Nishizawa J., Ohmi T., and Chen H. L., “Analysis of Static Characteristics of a BipolarMode SIT (BSIT),” IEEE Trans. on Electron Devices, vol. 29, No. 8, pp. 1233–1244, August 1982.
143 13. Yano K., Henmi I., Kasuga M., and Shimizu A., “HighPower Rectiﬁer Using the BSIT Operation,” IEEE Trans. on Electron Devices, vol. 45, No. 2, pp. 563–565, February 1998. 14. Yano K., Masahito M., Moroshima H., Morita J., Kasuga M., and Shimizu A., “Rectiﬁer Characteristics Based on BipolarMode SIT Operation,” IEEE Electron Device Letters, vol. 15, No. 9, pp. 321–323, September 1994. 15. Hironaka R., Watanabe M., Hotta E., and Okino A. “Performance of Pulsed Power Generator using High Voltage Static Induction Thyristor,” IEEE Trans. on Plasma Science, vol. 28, No. 5, pp. 1524–1527, 2000. 16. Yano K., Honarkhah S., and Salama A., “Lateral SOI Static Induction Rectiﬁers”, Proc. of 2001 Int. Symp. on Power Semiconductor Devices, Osaka, pp. 247–250, 2001. 17. Yano K., Hattori N., Yamamoto Y., and Kasuga M., “Impacts of Channel Implantation on Performance of Static Shielding Diodes and Static Induction Rectiﬁers,” Proc. of 2001 Int. Symp. on Power Semiconductor Devices, Osaka, pp. 219–222, 2001. 18. Wilamowski B. M., “Schottky Diodes with High Breakdown voltage,” SolidState Electronics, vol. 26, No. 5, pp. 491–493, 1983. 19. Baliga B. J., “The Pinch Rectiﬁer: A Low ForwardDrop, HighSpeed Power Diode,” IEEE Electron Device Letters, vol. 5, pp. 194–196, 1984. 20. Wilamowski B. M. and Jaeger R. C., “The Lateral PunchThrough Transistor,” IEEE Electron Device Letters, vol. 3, No. 10, pp. 277–280, 1982. 21. Wilamowski B. M., Mattson R. H., and Staszak Z. J., “The SIT saturation protected bipolar transistor,” IEEE Electron Device Letters, vol. 5, pp. 263–265, 1984. 22. Wilamowski B. M., “The PunchThrough Transistor with MOS Controlled Gate,” Phys. Status Solidi (a), vol. 79, pp. 631–637, 1983. 23. Wilamowski B. M., Jaeger R. C., and Fordemwalt J. N., “Buried MOS Transistor with PunchThrough,” Solid State Electronics, vol. 27, No. 8/9, pp. 811–815, 1984. 24. Shimizu N., Sekiya T., Iida K., Imanishi Y., Kimura M., and Nishizawa J., “Over 55kV/us, dv/dt turnoff characteristics of 4kVStatic Induction Thyristor for Pulsed Power Applications,” Proc. of 2004 Int. Symp. on Power Semiconductor Devices, Kitakyushu, Japan, pp. 281–284, 2004.
10 Diode Rectiﬁers YimShu Lee and Martin H. L. Chow Department of Electronic and Information Engineering, The Hong Kong Polytechnic, University Hung Hom, Hong Kong
10.1 Introduction .......................................................................................... 145 10.2 Singlephase Diode Rectiﬁers .................................................................... 145 10.2.1 Singlephase Halfwave Rectiﬁers • 10.2.2 Singlephase Fullwave Rectiﬁers • 10.2.3 Performance Parameters • 10.2.4 Design Considerations
10.3 Threephase Diode Rectiﬁers .................................................................... 150 10.3.1 Threephase Star Rectiﬁers • 10.3.2 Threephase Bridge Rectiﬁers • 10.3.3 Operation of Rectiﬁers with Finite Source Inductance
10.4 Polyphase Diode Rectiﬁers ...................................................................... 155 10.4.1 Sixphase Star Rectiﬁer • 10.4.2 Sixphase Series Bridge Rectiﬁer • 10.4.3 Sixphase Parallel Bridge Rectiﬁer
10.5 Filtering Systems in Rectiﬁer Circuits ......................................................... 158 10.5.1 Inductiveinput DC Filters • 10.5.2 Capacitiveinput DC Filters
10.6 Highfrequency Diode Rectiﬁer Circuits...................................................... 162 10.6.1 Forward Rectiﬁer Diode, Flywheel Diode, and Magneticreset Clamping Diode in a Forward Converter • 10.6.2 Flyback Rectiﬁer Diode and Clamping Diode in a Flyback Converter • 10.6.3 Design Considerations • 10.6.4 Precautions in Interpreting Simulation Results
Further Reading ..................................................................................... 177
10.1 Introduction
10.2 Singlephase Diode Rectiﬁers
This chapter describes the application and design of diode rectiﬁer circuits. It covers singlephase rectiﬁer circuits, threephase rectiﬁer circuits, polyphase rectiﬁer circuits, and highfrequency rectiﬁer circuits. The objectives of this chapter are:
There are two types of singlephase diode rectiﬁer that convert a singlephase ac supply into a dc voltage, namely, singlephase halfwave rectiﬁers and singlephase fullwave rectiﬁers. In the following subsections, the operations of these rectiﬁer circuits are examined and their performances are analyzed and compared in a tabulated form. For the sake of simplicity, the diodes are considered to be ideal, i.e. they have zero forward voltage drop and reverse recovery time. This assumption is generally valid for the case of diode rectiﬁers which use the mains, a lowfrequency source, as the input, and when the forward voltage drop is small compared with the peak voltage of the mains. Furthermore, it is assumed that the load is purely resistive such that the load voltage and the load current have similar waveforms. In Section 10.5, Filtering Systems in Rectiﬁers, the effects of inductive load and capacitive load on a diode rectiﬁer are considered in detail.
• • •
To enable the readers to understand the operation of typical rectiﬁer circuits. To enable the readers to appreciate the different qualities of rectiﬁers required for different applications. To enable the reader to design practical rectiﬁer circuits.
The highfrequency rectiﬁer waveforms given are obtained from PSPICE simulations, which take into account the secondary effects of stray and parasitic components. In this way, the waveforms can closely resemble the real ones. These waveforms are particularly useful to help designers determine the practical voltage, current, and other ratings of highfrequency rectiﬁers.
Copyright © 2007, 2001, Elsevier Inc. All rights reserved.
145
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Y. S. Lee and M. H. L. Chow
10.2.1 Singlephase Halfwave Rectiﬁers The simplest singlephase diode rectiﬁer is the singlephase halfwave rectiﬁer. A singlephase halfwave rectiﬁer with resistive load is shown in Fig. 10.1. The circuit consists of only one diode that is usually fed with a secondary transformer as shown. During the positive halfcycle of the transformer secondary voltage, diode D conducts. During the negative halfcycle, diode D stops conducting. Assuming that the transformer has zero internal impedance and provides perfect sinusoidal voltage on its secondary winding, the voltage and current waveforms of resistive load R and the voltage waveform of diode D are shown in Fig. 10.2. By observing the voltage waveform of diode D in Fig. 10.2, it is clear that the peak inverse voltage (PIV) of diode D is equal to Vm during the negative halfcycle of the transformer secondary voltage. Hence the peak repetitive reverse voltage (VRRM ) rating of diode D must be chosen to be higher than Vm to avoid reverse breakdown. In the positive halfcycle of the transformer secondary voltage, diode D has a forward current which is equal to the load current, therefore the peak repetitive forward current (IFRM ) rating of diode D must be chosen to
vD iL
D +
vs = Vm Sin ωt
–
vL
R
FIGURE 10.1 A singlephase halfwave rectiﬁer with resistive load.
vS Vm π/2
π
2π
3π
π/2
π
2π
3π
ωt
vL Vm
iL Vm = R
be higher than the peak load current, Vm = R, in practice. In addition, the transformer has to carry a dc current that may result in a dc saturation problem of the transformer core.
10.2.2 Singlephase Fullwave Rectiﬁers There are two types of singlephase fullwave rectiﬁer, namely, fullwave rectiﬁers with centertapped transformer and bridge rectiﬁers. A fullwave rectiﬁer with a centertapped transformer is shown in Fig. 10.3. It is clear that each diode, together with the associated half of the transformer, acts as a halfwave rectiﬁer. The outputs of the two halfwave rectiﬁers are combined to produce fullwave rectiﬁcation in the load. As far as the transformer is concerned, the dc currents of the two halfwave rectiﬁers are equal and opposite, such that there is no dc current for creating a transformer core saturation problem. The voltage and current waveforms of the fullwave rectiﬁer are shown in Fig. 10.4. By observing diode voltage waveforms vD1 and vD2 in Fig. 10.4, it is clear that the PIV of the diodes is equal to 2Vm during their blocking state. Hence the VRRM rating of the diodes must be chosen to be higher than 2Vm to avoid reverse breakdown. (Note that, compared with the halfwave rectiﬁer shown in Fig. 10.1, the fullwave rectiﬁer has twice the dc output voltage, as shown in Section 10.2.4.) During its conducting state, each diode has a forward current which is equal to the load current, therefore the IFRM rating of these diodes must be chosen to be higher than the peak load current, Vm = R, in practice. Employing four diodes instead of two, a bridge rectiﬁer as shown in Fig. 10.5 can provide fullwave rectiﬁcation without using a centertapped transformer. During the positive halfcycle of the transformer secondary voltage, the current ﬂows to the load through diodes D1 and D2 . During the negative halfcycle, D3 and D4 conduct. The voltage and current waveforms of the bridge rectiﬁer are shown in Fig. 10.6 As with the fullwave rectiﬁer with centertapped transformer, the IFRM rating of the employed diodes must be chosen to be higher than the peak load current, Vm = R. However, the PIV of the diodes is reduced from 2Vm to Vm during their blocking state.
wt
vD1
D1 π/2
π
2π
3π
wt
–
vD π
2π
3π
+
vs
wt
–V
FIGURE 10.2 Voltage and current waveforms of the halfwave rectiﬁer with resistive load.
vL
iL
R vs vs = Vm sin wt
D2
vD2
FIGURE 10.3 Fullwave rectiﬁer with centertapped transformer.
10
147
Diode Rectiﬁers vs
vs
Vm
Vm
2p
p
p/2
wt
3p
Vm
p
2p
3p
p/2
p
2p
3p
wt
vL Vm
vL Vm
iL =R
p/2
2p
p
p/2
wt
3p
iL Vm =R
D1,D2 conduct D1 conducts p/2
D2 conducts
D1 conducts
2p
p
wt
3p
wt
3p
2p
D1,D2 conduct
p
2p
3p
p
2p
3p
wt
vD1,vD2
vD1 p
p/2
D3,D4 conduct
wt
wt
–Vm vD3, vD4 –2V
p
3p
wt
–Vm
vD2 p
wt
3p
2p
–2V
FIGURE 10.4 Voltage and current waveforms of the fullwave rectiﬁer with centertapped transformer.
D1
D3
vs
R D4
FIGURE 10.6 Voltage and current waveforms of the bridge rectiﬁer.
10.2.3.1 Voltage Relationships The average value of the load voltage vL is Vdc and it is deﬁned as 1 T vL (t ) dt (10.1) Vdc = T 0 In the case of a halfwave rectiﬁer, Fig. 10.2 indicates that load voltage vL (t ) = 0 for the negative halfcycle. Note that the angular frequency of the source ω = 2π = T , and Eq. (10.1) can be rewritten as π 1 Vdc = Vm sin ωt d(ωt ) (10.2) 2π 0
iL
+ −
2p
vL
Therefore,
D2
Halfwave
Vdc =
vs = Vm sin wt
FIGURE 10.5 Bridge rectiﬁer.
10.2.3 Performance Parameters In this subsection, the performance of the rectiﬁers mentioned above will be evaluated in terms of the following parameters.
Vm = 0.318Vm π
(10.3)
In the case of a fullwave rectiﬁer, Figs. 10.4 and 10.6 indicate that vL (t ) = Vm  sin ωt  for both the positive and negative halfcycles. Hence Eq. (10.1) can be rewritten as 1 π Vdc = Vm sin ωt d(ωt ) (10.4) π 0 Therefore, Fullwave
Vdc =
2Vm = 0.636Vm π
(10.5)
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The rootmeansquare (rms) value of load voltage vL is VL , which is deﬁned as VL =
1 T
T
0
1/2 vL2 (t )dt
Fullwave
VL =
1 2π
(10.15)
Fullwave
IL =
0.707Vm R
(10.16)
π
(Vm sin ωt )2 d(ωt )
(10.7)
or VL =
Vm = 0.5Vm 2
10.2.3.3 Rectiﬁcation Ratio The rectiﬁcation ratio, which is a ﬁgure of merit for comparing the effectiveness of rectiﬁcation, is deﬁned as
(10.8)
In the case of a fullwave rectiﬁer, vL (t ) = Vm  sin ωt  for both the positive and negative halfcycles. Hence Eq. (10.6) can be rewritten as 1 π VL = (Vm sin ωt )2 d(ωt ) (10.9) π 0
Vm VL = √ = 0.707Vm 2
(10.10)
The result of Eq. (10.10) is as expected because the rms value of a fullwave rectiﬁed voltage should be equal to that of the original ac voltage. 10.2.3.2 Current Relationships The average value of load current iL is Idc and because load R is purely resistive it can be found as Idc =
Vdc R
Halfwave σ =
(10.12)
Idc
0.318Vm = R
Fullwave
IL =
σ=
0.5Vm R
(0.636Vm )2 = 81% (0.707Vm )2
(10.19)
10.2.3.4 Form Factor The form factor (FF) is deﬁned as the ratio of the rootmeansquare value (heating component) of a voltage or current to its average value, VL Vdc
or
IL Idc
(10.20)
In the case of a halfwave rectiﬁer, the FF can be found by substituting Eqs. (10.8) and (10.3) into Eq. (10.20). Halfwave FF =
0.5Vm = 1.57 0.318Vm
(10.21)
(10.13) In the case of a fullwave rectiﬁer, the FF can be found by substituting Eqs. (10.16) and (10.15) into Eq. (10.20).
and from Eq. (10.8) Halfwave
(10.18)
In the case of a fullwave rectiﬁer, the rectiﬁcation ratio is obtained by substituting Eqs. (10.5), (10.15), (10.10), and (10.16) into Eq. (10.17).
FF =
In the case of a halfwave rectiﬁer, from Eq. (10.3) Halfwave
(0.318Vm )2 = 40.5% (0.5Vm )2
(10.11)
VL R
(10.17)
In the case of a halfwave diode rectiﬁer, the rectiﬁcation ratio can be determined by substituting Eqs. (10.3), (10.13), (10.8), and (10.14) into Eq. (10.17).
The rms value of load current iL is IL and it can be found as IL =
Pdc Vdc Tdc = PL VL IL
σ=
or Fullwave
0.636Vm R
and from Eq. (10.10)
0
Halfwave
Idc =
(10.6)
In the case of a halfwave rectiﬁer, vL (t ) = 0 for the negative halfcycle, therefore Eq. (10.6) can be rewritten as
In the case of a fullwave rectiﬁer, from Eq. (10.5)
(10.14)
Fullwave
FF =
0.707Vm = 1.11 0.636Vm
(10.22)
10
149
Diode Rectiﬁers
10.2.3.5 Ripple Factor The ripple factor (RF), which is a measure of the ripple content, is deﬁned as RF =
Vac Vdc
(10.23)
where Vac is the effective (rms) value of the ac component of load voltage vL . Vac =
VL2 − Vdc2
(10.24)
Substituting Eq. (10.24) into Eq. (10.23), the RF can be expressed as RF =
VL Vdc
2 −1=
FF2 − 1
(10.25)
In the case of a halfwave rectiﬁer, Halfwave RF =
1.572 − 1 = 1.21
(10.26)
In the case of a fullwave rectiﬁer, Fullwave RF = 1.112 − 1 = 0.482
Pdc Vdc Idc = Vs Is Vs Is
(10.28)
Is =
0.5Vm R
(10.30)
For a fullwave rectiﬁer, Is is found from Eq. (10.16). Fullwave
Is =
0.707Vm R
(10.32)
The poor TUF of a halfwave rectiﬁer signiﬁes that the transformer employed must have a 3.496 (1/0.286) VA rating in order to deliver 1 W dc output power to the load. In addition, the transformer secondary winding has to carry a dc current that may cause magnetic core saturation. As a result, halfwave rectiﬁers are used only when the current requirement is small. In the case of a fullwave rectiﬁer with centertapped transformer, the circuit can be treated as two halfwave rectiﬁers operating together. Therefore, the transformer secondary VA rating, Vs Is , is double that of a halfwave rectiﬁer, but the output dc power is increased by a factor of four due to higher the rectiﬁcation ratio as indicated by Eqs. (10.5) and (10.15). Therefore, the TUF of a fullwave rectiﬁer with centertapped transformer can be found from Eq. (10.32) 4 × 0.3182 = 0.572 2 × 0.707 × 0.5
(10.33)
In the case of a bridge rectiﬁer, it has the highest TUF in singlephase rectiﬁer circuits because the currents ﬂowing in both the primary and secondary windings are continuous sinewaves. By substituting Eqs. (10.5), (10.15), (10.29), and (10.31) into Eq. (10.28), the TUF of a bridge rectiﬁer can be found.
Bridge
TUF =
0.6362 = 0.81 (0.707)2
(10.34)
The transformer primary VA rating of a fullwave rectiﬁer is equal to that of a bridge rectiﬁer since the current ﬂowing in the primary winding is also a continuous sinewave.
(10.29)
The rms value of the transformer secondary current Is is the same as that of the load current IL . For a halfwave rectiﬁer, Is can be found from Eq. (10.14). Halfwave
0.3182 = 0.286 0.707 × 0.5
(10.27)
where Vs and Is are the rms voltage and rms current ratings of the secondary transformer. Vm Vs = √ = 0.707Vm 2
Halfwave TUF =
Fullwave TUF =
10.2.3.6 Transformer Utilization Factor The transformer utilization factor (TUF), which is a measure of the merit of a rectiﬁer circuit, is deﬁned as the ratio of the dc output power to the transformer volt–ampere (VA) rating required by the secondary winding, TUF =
Therefore, the TUF of a halfwave rectiﬁer can be obtained by substituting Eqs. (10.3), (10.13), (10.29), and (10.30) into Eq. (10.28).
(10.31)
10.2.3.7 Harmonics Fullwave rectiﬁer circuits with resistive load do not produce harmonic currents in their transformers. In halfwave rectiﬁers, harmonic currents are generated. The amplitudes of the harmonic currents of a halfwave rectiﬁer with resistive load, relative to the fundamental, are given in Table 10.1. The extra loss caused by the harmonics in the resistive loaded rectiﬁer circuits is often neglected because it is not high compared with other losses. However, with nonlinear loads, harmonics can cause appreciable loss and other problems such as poor power factor and interference.
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Y. S. Lee and M. H. L. Chow
TABLE 10.1 Harmonic percentages of a halfwave rectiﬁer with resistive load Harmonic
2nd
3rd
4th
5th
6th
7th
8th
%
21.2
0
4.2
0
1.8
0
1.01
In the case of a fullwave rectiﬁer with centertapped transformer, from Eq. (10.5), VRRM = 2Vm =
Fullwave
2Vdc = 3.14Vdc 0.636
(10.38)
In the case of a bridge rectiﬁer, also from Eq. (10.5),
10.2.4 Design Considerations
Bridge
In a practical design, the goal is to achieve a given dc output voltage. Therefore, it is more convenient to put all the design parameters in terms of Vdc . For example, the rating and turns ratio of the transformer in a rectiﬁer circuit can be easily determined if the rms input voltage to the rectiﬁer is in terms of the required output voltage Vdc . Denote the rms value of the input voltage to the rectiﬁer as Vs , which is equal to 0.707Vm . Based on this relation and Eq. (10.3), the rms input voltage to a halfwave rectiﬁer is found as
VRRM = Vm =
Vs = 2.22Vdc
Halfwave IFRM =
Vm Idc = = 3.41Idc R 0.318
(10.40)
In the case of fullwave rectiﬁers, from Eq. (10.15),
(10.35)
Similarly, from Eqs. (10.5) and (10.29), the rms input voltage per secondary winding of a fullwave rectiﬁer is found as
(10.39)
It is important to evaluate the IFRM rating of the employed diodes in rectiﬁer circuits. In the case of a halfwave rectiﬁer, from Eq. (10.13),
Fullwave IFRM = Halfwave
Vdc = 1.57Vdc 0.636
Vm Idc = = 1.57Idc R 0.636
(10.41)
The important design parameters of basic singlephase rectiﬁer circuits with resistive loads are summarized in Table 10.2.
10.3 Threephase Diode Rectiﬁers Fullwave
Vs = 1.11Vdc
(10.36)
Another important design parameter is the VRRM rating of the diodes employed. In the case of a halfwave rectiﬁer, from Eq. (10.3),
Halfwave
VRRM = Vm =
TABLE 10.2
Vdc = 3.14Vdc 0.318
(10.37)
It has been shown in Section 10.2 that singlephase diode rectiﬁers require a rather high transformer VA rating for a given dc output power. Therefore, these rectiﬁers are suitable only for low to medium power applications. For power output higher than 15 kW, threephase or polyphase diode rectiﬁers should be employed. There are two types of threephase diode rectiﬁer that convert a threephase ac supply into a dc voltage, namely, star rectiﬁers and bridge rectiﬁers. In the following subsections,
Important design parameters of basic singlephase rectiﬁer circuits with resistive load
Peak repetitive reverse voltage VRRM RMS input voltage per transformer leg Vs Diode average current IF (AV) Peak repetitive forward current IFRM Diode rms current IF (RMS) Form factor of diode current IF (RMS) /IF (AV) Rectiﬁcation ratio Form factor Ripple factor Transformer rating primary VA Transformer rating secondary VA Output ripple frequency fr
Halfwave rectiﬁer
Fullwave rectiﬁer with centertapped transformer
Fullwave bridge rectiﬁer
3.14Vdc 2.22Vdc 1.00Idc 3.14IF (AV) 1.57Idc 1.57 0.405 1.57 1.21 2.69Pdc 3.49Pdc 1fi
3.14Vdc 1.11Vdc 0.50Idc 1.57IF (AV) 0.785Idc 1.57 0.81 1.11 0.482 1.23Pdc 1.75Pdc 2fi
1.57Vdc 1.11Vdc 0.50Idc 1.57IF (AV) 0.785Idc 1.57 0.81 1.11 0.482 1.23Pdc 1.23Pdc 2fi
10
151
Diode Rectiﬁers
the operations of these rectiﬁers are examined and their performances are analyzed and compared in tabulated form. For the sake of simplicity, the diodes and the transformers are considered to be ideal, i.e. the diodes have zero forward voltage drop and reverse current, and the transformers possess no resistance and no leakage inductance. Furthermore, it is assumed that the load is purely resistive, such that the load voltage and the load current have similar waveforms. In Section 10.5 Filtering Systems in Rectiﬁer Circuits, the effects of inductive load and capacitive load on a diode rectiﬁer are considered in detail.
10.3.1 Threephase Star Rectiﬁers 10.3.1.1 Basic Threephase Star Rectiﬁer Circuit A basic threephase star rectiﬁer circuit is shown in Fig. 10.7. This circuit can be considered as three singlephase halfwave rectiﬁers combined together. Therefore it is sometimes referred to as a threephase halfwave rectiﬁer. The diode in a particular phase conducts during the period when the voltage on that phase is higher than that on the other two phases. The voltage waveforms of each phase and the load are shown in Fig. 10.8. It is clear that, unlike the singlephase rectiﬁer circuit, the conduction angle of each diode is 2π/3, instead of π. This circuit ﬁnds uses where the required dc output voltage is relatively low and the required output current is too large for a practical singlephase system.
vRN
Vm
vYN
B
vRN
vBN
N vYN
vD R
Y
Vdc =
3 2π
5π/6
Vm sin θdθ
Vdc
√ 3 3 = 0.827Vm = Vm π 2
(10.43)
Similarly, using Eq. (10.6), the rms value of the output voltage can be found as VL =
3 2π
5π/6
(Vm sin θ)2 dθ
π/6
vBN wt 3p
p
2p
3p
2p
3p
wt
wt p
(10.42)
π/6
vL
vD
vL
or
2p
5p/6
R
Taking phase R as an example, diode D conducts from π/6 to 5π/6. Therefore, using Eq. (10.1) the average value of the output can be found as
Vm
p/6
iD
FIGURE 10.7 Threephase star rectiﬁer.
p
iD Vm /R
D
wt
–1.73Vm
FIGURE 10.8 Waveforms of voltage and current of the threephase star rectiﬁer shown in Fig. 10.7.
(10.44)
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Y. S. Lee and M. H. L. Chow TABLE 10.3
Important design parameters of the threephase rectiﬁer circuits with the resistive load
Peak repetitive reverse voltage VRRM RMS input voltage per transformer leg Vs Diode average current IF (AV) Peak repetitive forward current IFRM Diode rms current IF (RMS) Form factor of diode current IF (RMS) /IF (AV) Rectiﬁcation ratio Form factor Ripple factor Transformer rating primary VA Transformer rating secondary VA Output ripple frequency fr
Threephase star rectiﬁer
Threephase doublestar rectiﬁer with interphase transformer
Threephase bridge rectiﬁer
2.092Vdc 0.855Vdc 0.333Idc 3.63IF (AV) 0.587Idc 1.76 0.968 1.0165 0.182 1.23Pdc 1.51Pdc 3fi
1.06Vdc 0.855Vdc 0.167Idc 3.15IF (AV) 0.293Idc 1.76 0.998 1.0009 0.042 1.06Pdc 1.49Pdc 6fi
1.05Vdc 0.428Vdc 0.333Idc 3.14IF (AV) 0.579Idc 1.74 0.998 1.0009 0.042 1.05Pdc 1.05Pdc 6fi
or
√
3 π 3 VL = Vm + = 0.84Vm 2π 3 4
to zero. Therefore it is preferable not to have starconnected primary windings. (10.45) 10.3.1.2 Threephase Interstar Rectiﬁer Circuit The transformer core saturation problem in the threephase star rectiﬁer can be avoided by a special arrangement in its secondary windings, known as zigzag connection. The modiﬁed circuit is called the threephase interstar or zigzag rectiﬁer circuit, as shown in Fig. 10.9. Each secondary phase voltage is obtained from two equalvoltage secondary windings (with a phase displacement of π/3) connected in series so that the dc magnetizing forces due to the two secondary windings on any limb are equal and opposite. At the expense of extra secondary windings (increasing the transformer secondary rating factor from 1.51 to 1.74 VA/W), this circuit connection eliminates the effects of core saturation and reduces the transformer primary rating factor to the minimum of 1.05 VA/W. Apart from transformer ratings, all the design parameters of this circuit are the same as those of a threephase star rectiﬁer (therefore not separately listed in Table 10.3). Furthermore, a starconnected primary winding with no neutral connection
In addition, the rms current in each transformer secondary winding can also be found as
√
1 π 3 Is = Im + = 0.485Im 2π 3 4
(10.46)
where Im = Vm /R. Based on the relationships stated in Eqs. (10.43), (10.45), and (10.46), all the important design parameters of the threephase star rectiﬁer can be evaluated, as listed in Table 10.3, which is given at the end of Subsection 10.3.2. Note that, as with a singlephase halfwave rectiﬁer, the threephase star rectiﬁer shown in Fig. 10.7 has direct currents in the secondary windings that can cause a transformer core saturation problem. In addition, the currents in the primary do not sum
Y’ B R R’
Y
B’
FIGURE 10.9 Threephase interstar rectiﬁer.
10
153
Diode Rectiﬁers
is equally permissible because the sum of all primary phase currents is zero at all times. 10.3.1.3 Threephase Doublestar Rectiﬁer with Interphase Transformer This circuit consists essentially of two threephase star rectiﬁers with their neutral points interconnected through an interphase transformer or reactor (Fig. 10.10). The polarities of the corresponding secondary windings in the two interconnected systems are reversed with respect to each other, so that the rectiﬁer output voltage of one threephase unit is at a minimum when the rectiﬁer output voltage of the other unit is at a maximum as shown in Fig. 10.11. The function of the interphase transformer is to cause the output voltage vL to be the average of the rectiﬁed voltages v1 and v2 as shown in Fig. 10.11. In addition, the ripple frequency of the output voltage is now six times that of the mains and therefore the component size of the ﬁlter (if there is any) becomes smaller. In a balanced circuit, the output currents of two threephase units ﬂowing in opposite directions in the interphase transformer winding will produce no dc magnetization current. Similarly, the dc magnetization currents in the secondary windings of two threephase units cancel each other out. By virtue of the symmetry of the secondary circuits, the three primary currents add up to zero at all times. Therefore, a star primary winding with no neutral connection would be equally permissible.
The diodes are numbered in the order of conduction sequences and the conduction angle of each diode is 2π/3. The conduction sequence for diodes is 12, 23, 34, 45, 56, and 61. The voltage and the current waveforms of the threephase bridge rectiﬁer are shown in Fig. 10.13. The line voltage is 1.73 times the phase voltage of a threephase starconnected source. It is permissible to use any combination of star or deltaconnected primary and secondary windings because the currents associated with the secondary windings are symmetrical. Using Eq. (10.1) the average value of the output can be found as Vdc
6 = 2π
Vdc
3Vm sin θdθ
(10.47)
π/3
√ 3 3 = Vm = 1.654Vm π
(10.48)
Similarly, using Eq. (10.6), the rms value of the output voltage can be found as VL =
9 π
2π/3
(Vm sin θ)2 dθ
(10.49)
π/3
or VL = Vm
Threephase bridge rectiﬁers are commonly used for high power applications because they have the highest possible transformer utilization factor for a threephase system. The circuit of a threephase bridge rectiﬁer is shown in Fig. 10.12.
2π/3 √
or
10.3.2 Threephase Bridge Rectiﬁers
√ 3 9 3 + = 1.655Vm 2 4π
(10.50)
In addition, the rms current in each transformer secondary winding can also be found as
√
2 π 3 Is = Im + = 0.78Im π 6 4
(10.51)
and the rms current through a diode is v1 vL
v2
FIGURE 10.10 Threephase doublestar rectiﬁer with interphase transformer.
√
1 π 3 ID = Im + = 0.552Im π 6 4
(10.52)
where Im = 1.73Vm /R. Based on Eqs. (10.48), (10.50), (10.51), and (10.52), all the important design parameters of the threephase star rectiﬁer can be evaluated, as listed in Table 10.3. The dc output voltage is slightly lower than the peak line voltage or 2.34 times the rms phase voltage. The VRRM rating of the employed diodes is 1.05 times the dc output voltage, and the IFRM rating of the employed diodes is 0.579 times the dc output current. Therefore, this threephase bridge rectiﬁer is very efﬁcient and
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Y. S. Lee and M. H. L. Chow v1
v2
vL
wt
p/3
FIGURE 10.11 Voltage waveforms of the threephase doublestar rectiﬁer.
D3 D1
D5
B R vL Y D4
D2 D6
FIGURE 10.12 Threephase bridge rectiﬁer.
1.73Vm
vRY
vBY
vYB
vRB
vYR
vBR
wt p
2p
p/2
vL
3p/2
1.73Vm wt iDi
p/3
2p/3
p
4p/3
5p/3
2p
p
4p/3
5p/3
2p
1.73Vm / R
wt D5 conducts
p/3 D6 conducts
2p/3 D1 conducts
D2 conducts D3 conducts
D4 conducts D5 conducts
FIGURE 10.13 Voltage and current waveforms of the threephase bridge rectiﬁer.
10
155
Diode Rectiﬁers
popular wherever both dc voltage and current requirements are high. In many applications, no additional ﬁlter is required because the output ripple voltage is only 4.2%. Even if a ﬁlter is required, the size of the ﬁlter is relatively small because the ripple frequency is increased to six times the input frequency.
10.3.3 Operation of Rectiﬁers with Finite Source Inductance It has been assumed in the preceding sections that the commutation of current from one diode to the next takes place instantaneously when the interphase voltage assumes the necessary polarity. In practice this is hardly possible, because there are ﬁnite inductances associated with the source. For the purpose of discussing the effects of the ﬁnite source inductance, a threephase star rectiﬁer with transformer leakage inductances is shown in Fig. 10.14, where l1 , l2 , l3 denote the leakage inductances associated with the transformer secondary windings. Refer to Fig. 10.15. At the time when vYN is about to become larger than vRN , due to leakage inductance l1 , the current in D1 cannot fall to zero immediately. Similarly, due to the leakage inductance l2 , the current in D2 cannot increase immediately
l3 D 3 B l1 D 1 N
R
l2 D 2 Y
R
vL
FIGURE 10.14 Threephase star rectiﬁer with the transformer leakage inductances.
VL Vm
vRN
vYN
to the full value. The result is that both the diodes conduct for a certain period, which is called the overlap (or commutation) angle. The overlap reduces the rectiﬁed voltage vL as shown in the upper voltage waveform of Fig. 10.15. If all the leakage inductances are equal, i.e. l1 = l2 = l3 = lc , then the amount of reduction of dc output voltage can be estimated as mfi lc Idc , where m is the ratio of the lowestripple frequency to the input frequency. For example, for a threephase star rectiﬁer operating from a 60Hz supply with an average load current of 50 A, the amount of reduction of the dc output voltage is 2.7 V if the leakage inductance in each secondary winding is 300 µH.
10.4 Polyphase Diode Rectiﬁers 10.4.1 Sixphase Star Rectiﬁer A basic sixphase star rectiﬁer circuit is shown in Fig. 10.16. The sixphase voltages on the secondary are obtained by means of a centertapped arrangement on a starconnected threephase winding. Therefore, it is sometimes referred to as a threephase fullwave rectiﬁer. The diode in a particular phase conducts during the period when the voltage on that phase is higher than that on the other phases. The voltage waveforms of each phase and the load are shown in Fig. 10.17. It is clear that, unlike the threephase star rectiﬁer circuit, the conduction angle of each diode is π/3, instead of 2π/3. Currents ﬂow in only one rectifying element at a time, resulting in a low average current, but a high peak to an average current ratio in the diodes and poor transformer secondary utilization. Nevertheless, the dc currents in the secondary of the sixphase star rectiﬁer cancel in the secondary windings like a fullwave rectiﬁer and, therefore, core saturation is not encountered. This sixphase star circuit is attractive in applications which require a low ripple factor and a common cathode or anode for the rectiﬁers. By considering the output voltage provided by vRN between π/3 and 2π/3, the average value of the output voltage can be
D1 wt iD
D2
R Y
overlap angle
Vm /R D1 conducts
B
D3
Y
D4
N
D2 conducts wt
B
R
D5 D6
FIGURE 10.15 Waveforms during commutation in Fig. 10.14.
FIGURE 10.16 Sixphase star rectiﬁer.
vL
156
Y. S. Lee and M. H. L. Chow vYN
Vm
vBN
vRN
vRN
vYN
vBN
wt 2p p/2
VL
3p/2
Vm D1 conducts
D2 conducts p/3
D3 conducts
D4 conducts p
2p/3
D5 conducts
4p/3
D6 conducts
5p/3
wt
2p
FIGURE 10.17 Voltage waveforms of the sixphase star rectiﬁer.
found as Vdc =
6 2π
In addition, the rms current in each transformer secondary winding can also be found as
2π/3
Vm sin θdθ
√
1 π 3 Is = Im + = 0.39Im 2π 6 4
(10.53)
π/3
or 61 = 0.955Vm π2
Vdc = Vm
(10.54)
Similarly, the rms value of the output voltage can be found as
VL =
or
6 2π
2π/3
(Vm sin θ)2 dθ
(10.57)
where Im = Vm /R. Based on the relationships stated in Eqs. (10.55), (10.56), and (10.57), all the important design parameters of the sixphase star rectiﬁer can be evaluated, as listed in Table 10.4 (given at the end of Subsection 10.4.3).
(10.55)
π/3
10.4.2 Sixphase Series Bridge Rectiﬁer
√
6 π 3 VL = Vm + = 0.956Vm 2π 6 4
TABLE 10.4
(10.56)
The star and deltaconnected secondaries have an inherent π/6phase displacement between their output voltages. When a star and a deltaconnected bridge rectiﬁer are connected
Important design parameters of the sixphase rectiﬁer circuits with resistive load
Peak repetitive reverse voltage VRRM RMS input voltage per transformer leg Vs Diode average current IF (AV) Peak repetitive forward current IFRM Diode rms current IF (RMS) Form factor of diode current IF (RMS) /IF (AV) Rectiﬁcation ratio Form factor Ripple factor Transformer rating primary VA Transformer rating secondary VA Output ripple frequency fr
Sixphase star rectiﬁer
Sixphase series bridge rectiﬁer
Sixphase parallel bridge rectiﬁer (with interphase transformer)
2.09Vdc 0.74Vdc 0.167Idc 6.28IF (AV) 0.409Idc 2.45 0.998 1.0009 0.042 1.28Pdc 1.81Pdc 6fi
0.524Vdc 0.37Vdc 0.333Idc 3.033IF (AV) 0.576Idc 1.73 1.00 1.00005 0.01 1.01Pdc 1.05Pdc 12fi
1.05Vdc 0.715Vdc 0.167Idc 3.14IF (AV) 0.409Idc 2.45 1.00 1.00005 0.01 1.01Pdc 1.05Pdc 12fi
10
157
Diode Rectiﬁers
The rms value of the output voltage can be found as 1
1
12 2π
VL = 1
vL
7π/12
(Vm sin θ)2 dθ
(10.60)
= 0.98867Vm
(10.61)
5π/12
or
1
12 2π
VL = Vm
1
π 1 + 12 4
1
The rms current in each transformer secondary winding is
FIGURE 10.18 Sixphase series bridge rectiﬁer.
Is = Im in series as shown in Fig. 10.18, the combined output voltage will have a doubled ripple frequency (12 times that of the mains). The ripple of the combined output voltage will also be reduced from 4.2% (for each individual bridge rectiﬁer) to 1%. The combined bridge rectiﬁer is referred to as a sixphase series bridge rectiﬁer. In the sixphase series bridge rectiﬁer shown in Fig. 10.18, let Vm∗ be the peak voltage of the deltaconnected secondary. The peak voltage between the lines of the starconnected secondary is also Vm∗ . The peak voltage across the load, denoted as Vm , is equal to 2Vm∗ × cos(π/12) or 1.932Vm∗ because there is π/6phase displacement between the secondaries. The ripple frequency is twelve times the mains frequency. The average value of the output voltage can be found as
Vdc
12 = 2π
Is = Im
(10.62)
2 π
π 1 + 12 4
= 0.57Im
(10.63)
The sixphase series bridge rectiﬁer described above is useful for high output voltage applications. However, for high output current applications, the sixphase parallel bridge rectiﬁer (with an interphase transformer) shown in Fig. 10.19 should be used. The function of the interphase transformer is to cause the output voltage vL to be the average of the rectiﬁed voltages v1 and v2 as shown in Fig. 10.20. As with the sixphase series
(10.58)
(10.59)
1
= 0.807Im
10.4.3 Sixphase Parallel Bridge Rectiﬁer
5π/12
√ 12 3−1 √ = 0.98862Vm π 2 2
where Im = Vm /R. Based on Eqs. (10.59), (10.61), (10.62), and (10.63), all the important design parameters of the sixphase series bridge rectiﬁer can be evaluated, as listed in Table 10.4 (given at the end of Subsection 10.4.3).
or Vdc = Vm
π 1 + 12 4
The rms current through a diode is
7π/12
Vm sin θdθ
4 π
1 v2 vL 1
1 1 v1 1
FIGURE 10.19 Sixphase parallel bridge rectiﬁer.
158
Y. S. Lee and M. H. L. Chow v1
v2
vL
wt p/6
FIGURE 10.20 Voltage waveforms of the sixphase bridge rectiﬁer with interphase transformer.
bridge rectiﬁer, the output ripple frequency of the sixphase parallel bridge rectiﬁer is also 12 times that of the mains. Further ﬁltering on the output voltage is usually not required. Assuming a balanced circuit, the output currents of two threephase units (ﬂowing in opposite directions in the interphase transformer winding) produce no dc magnetization current. All the important design parameters of the sixphase parallel rectiﬁers with interphase transformer are also listed in Table 10.4.
10.5 Filtering Systems in Rectiﬁer Circuits Filters are commonly employed in rectiﬁer circuits for smoothing out the dc output voltage of the load. They are classiﬁed as inductorinput dc ﬁlters and capacitorinput dc ﬁlters. Inductorinput dc ﬁlters are preferred in highpower applications because more efﬁcient transformer operation is obtained due to the reduction in the form factor of the rectiﬁer current. Capacitorinput dc ﬁlters can provide volumetrically efﬁcient operation, but they demand excessive turnon and repetitive surge currents. Therefore, capacitorinput dc ﬁlters are suitable only for lowerpower systems where close regulation is usually achieved by an electronic regulator cascaded with the rectiﬁer.
10.5.1 Inductiveinput DC Filters The simplest inductiveinput dc ﬁlter is shown in Fig. 10.21a. The output current of the rectiﬁer can be maintained at a steady value if the inductance of Lf is sufﬁciently large (ωLf R). The ﬁltering action is more effective in heavy load conditions than in light load conditions. If the ripple attenuation is not sufﬁcient even with large values of inductance, an Lsection ﬁlter as shown in Fig. 10.21b can be used for further ﬁltering. In practice, multiple Lsection ﬁlters can also be employed if the requirement on the output ripple is very stringent. For a simple inductiveinput dc ﬁlter shown in Fig. 10.21a, the ripple is reduced by the factor vo = vL
vL
where fr is the ripple frequency, if R 1/2πfr Cf .
(a)
Lf
R
vo
(10.64)
where vL is the ripple voltage before ﬁltering, vo is the ripple voltage after ﬁltering, and fr is the ripple frequency. For the inductiveinput dc ﬁlter shown in Fig. 10.21b, the amount of reduction in the ripple voltage can be estimated as vo 1 (10.65) = 2 1 − 2πfr Lf Cf vL
Lf
Rectifier
R 2 R 2 + 2πfr Lf
Rectifier
vL
(b)
FIGURE 10.21 Inductiveinput dc ﬁlters.
Cf
R
vo
10
159
Diode Rectiﬁers
10.5.1.1 Voltage and Current Waveforms of Fullwave Rectiﬁer with Inductorinput DC Filter Figure 10.22 shows a singlephase fullwave rectiﬁer with an inductorinput dc ﬁlter. The voltage and current waveforms are illustrated in Fig. 10.23.
iL
10.5.1.2 Critical inductance LC In the case of singlephase fullwave rectiﬁers, the critical inductance can be found as Fullwave
Lf
Polyphase
+ −
vL
R 6πfi
R
vo
LC =
R 3πm m 2 − 1 fi
10.5.1.3 Determining the Input Inductance for a Given Ripple Factor In practice, the choice of the input inductance depends on the required ripple factor of the output voltage. The ripple voltage of a rectiﬁer without ﬁltering can be found by means of Fourier Analysis. For example, the coefﬁcient of the nth harmonic component of the rectiﬁed voltage vL shown in Fig. 10.22 can be expressed as:
When the inductance of Lf is inﬁnite, the current through the inductor and the output voltage are constant. When inductor Lf is ﬁnite, the current through the inductor has a ripple component, as shown by the dotted lines in Fig. 10.23. If the input inductance is too small, the current decreases to zero (becoming discontinuous) during a portion of the time between the peaks of the rectiﬁer output voltage. The minimum value of inductance required to maintain a continuous current is known as the critical inductance LC .
vLn =
−4Vm π n2 − 1
where n = 2, 4, 8, . . . etc.
vs
wt
p
2p
3p
is
inductor with infinite inductance
Im p/2
p
2p
wt
3p
inductor with finite inductance
vL
iL,vo
p/2
p
wt 2p
3p
inductor with infinite inductance inductor with finite inductance p/2
p
(10.67)
where m is ratio of the lowest ripple frequency to the input frequency, e.g. m = 6 for a threephase bridge rectiﬁer.
FIGURE 10.22 A fullwave rectiﬁer with inductorinput dc ﬁlter.
p/2
(10.66)
where fi is the input mains frequency. In the case of polyphase rectiﬁers, the critical inductance can be found as
is vs
LC =
2p
wt
3p
FIGURE 10.23 Voltage and current waveforms of fullwave rectiﬁer with inductorinput dc ﬁlter.
(10.68)
160
Y. S. Lee and M. H. L. Chow
The dc component of the rectiﬁer voltage is given by Eq. (10.5). Therefore, in addition to Eq. (10.27), the ripple factor can also be expressed as
RF = 2 n=2,4,8,
1 n2 − 1
+
2
−
Filtered
(10.72)
n=2,3,4,
where Isn is the rms value of the nth harmonic component of the input current. Moreover, the input power factor is deﬁned as Is1 cos φ Is
(10.73)
where φ is the displacement angle between the fundamental components of the input current and voltage. Assume that inductor Lf of the circuit shown in Fig. 10.22 has an inﬁnitely large inductance. The input current is then a square wave. This input current contains undesirable higher harmonics that reduce the input power factor of the system. The input current can be easily expressed as is =
4Im 1 sin 2nπfi t π n
Li
Isn
where Is is the rms value of the input current and Is1 and the rms value of the fundamental component of the input current. The THD can also be expressed as
PF =
FIGURE 10.24 Rectiﬁer with input ac ﬁlter.
(10.70)
10.5.1.4 Harmonics of the Input Current In general, the total harmonic distortion (THD) of an input current is deﬁned as Is 2 THD = −1 (10.71) Is1
2
Isn THD = Is1
Ci
(10.69)
Considering only the lowestorder harmonic (n = 2), the output ripple factor of a simple inductorinput dc ﬁlter (without Cf ) can be found, from Eqs. (10.64) and (10.69), as 0.4714 RF = 2 1 + 4πfi Lf /R
Li
(10.74)
n=1,3,5,
The rms values of the input √ current and its fundamental component are Im and 4Im /(π 2) respectively. Therefore, the THD of the input current of this circuit is 0.484.√Since the displacement angle φ = 0, the power factor is 4/(π 2) = 0.9.
Ci
Irn
FIGURE 10.25 Equivalent circuit for input ac ﬁlter.
The power factor of the circuit shown in Fig. 10.22 can be improved by installing an ac ﬁlter between the source and the rectiﬁer, as shown in Fig. 10.24. Considering only the harmonic components, the equivalent circuit of the rectiﬁer given in Fig. 10.24 can be found as shown in Fig. 10.25. The rms value of the nth harmonic current appearing in the supply can then be obtained using the currentdivider rule, 1 Isn = (10.75) I 1 − 2nπfi 2 Li Ci rn where Irn is the rms value of the nth harmonic current of the rectiﬁer. Applying Eq. (10.73) and knowing Irn /Ir1 = 1/n from Eq. (10.74), the THD of the rectiﬁer with input ﬁlter shown in Fig. 10.24 can be found as 2
1 1 Filtered THD = (10.76) n 2 1 − 2nπfi 2 Li Ci n=3,5
The important design parameters of typical singlephase and threephase rectiﬁers with inductorinput dc ﬁlter are listed in Table 10.5. Note that, in a singlephase halfwave rectiﬁer, a freewheeling diode is required to be connected across the input of the dc ﬁlters such that the ﬂow of load current can be maintained during the negative halfcycle of the supply voltage.
10.5.2 Capacitiveinput DC Filters Figure 10.26 shows a fullwave rectiﬁer with capacitorinput dc ﬁlter. The voltage and current waveforms of this rectiﬁer
10
161
Diode Rectiﬁers
TABLE 10.5
Important design parameters of typical rectiﬁer circuits with inductorinput dc ﬁlter
Peak repetitive reverse voltage VRRM RMS input voltage per transformer leg Vs Diode average current IF (AV) Peak repetitive forward current IFRM Diode rms current IF (RMS) Form factor of diode current IF (RMS) /IF (AV) Transformer rating primary VA Transformer rating secondary VA Output ripple frequency fr Ripple component Vr at (a) fundamental, (b) second harmonic, (c) third harmonic of the ripple frequency
Fullwave rectiﬁer with centertapped transformer
Fullwave bridge rectiﬁer
Threephase star rectiﬁer
Threephase bridge rectiﬁer
Threephase doublestar rectiﬁer with interphase transformer
3.14Vdc 1.11Vdc 0.5Idc 2.00IF (AV) 0.707Idc 1.414 1.11Pdc 1.57Pdc 2fi
1.57Vdc 1.11Vdc 0.5Idc 2.00IF (AV) 0.707Idc 1.414 1.11Pdc 1.11Pdc 2fi
2.09Vdc 0.885Vdc 0.333Idc 3.00IF (AV) 0.577Idc 1.73 1.21Pdc 1.48Pdc 3fi
1.05Vdc 0.428Vdc 0.333Idc 3.00IF (AV) 0.577Idc 1.73 1.05Pdc 1.05Pdc 6fi
2.42Vdc 0.885Vdc 0.167Idc 3.00IF (AV) 0.289Idc 1.73 1.05Pdc 1.48Pdc 6fi
0.667Vdc 0.133Vdc 0.057Vdc
0.667Vdc 0.133Vdc 0.057Vdc
0.250Vdc 0.057Vdc 0.025Vdc
0.057Vdc 0.014Vdc 0.006Vdc
0.057Vdc 0.014Vdc 0.006Vdc
D1
vs
R inrush + −
Vm is
vs vs
vs= Vm sin wt
vL
C
p/2
R
p
FIGURE 10.26 Fullwave rectiﬁer with capacitorinput dc ﬁlter.
Vr(pp)
p/2
p
Vm fr RC
where fr is the output ripple frequency of the rectiﬁer.
2p
wt
3p
qc
is
are shown in Fig. 10.27. When the instantaneous voltage of the secondary winding vs is higher than the instantaneous value of capacitor voltage vL , either D1 or D2 conducts, and the capacitor C is charged up from the transformer. When the instantaneous voltage of the secondary winding vs falls below the instantaneous value of capacitor voltage vL , both the diodes are reverse biased and the capacitor C is discharged through load resistance R. The resulting capacitor voltage vL varies between a maximum value of Vm and a minimum value of Vm − Vr(pp) as shown in Fig. 10.27. (Vr(pp) is the peaktopeak ripple voltage.) As shown in Fig. 10.27, the conduction angle θc of the diodes becomes smaller when the outputripple voltage decreases. Consequently, the power supply and the diodes suffer from high repetitive surge currents. An LC ac ﬁlter, as shown in Fig. 10.24, may be required to improve the input power factor of the rectiﬁer. In practice, if the peaktopeak ripple voltage is small, it can be approximated as
wt
3p
vL Vm
D2
Vr (pp ) =
2p
D2 conducts p/2 p D1 conducts
2p
wt
3p D1 conducts
FIGURE 10.27 Voltage and current waveforms of the fullwave rectiﬁer with capacitorinput dc ﬁlter.
Therefore, the average output voltage Vdc is given by Vdc = Vm
1 1− 2fr RC
(10.78)
The rms output ripple voltage Vac is approximately given by
(10.77) Vm Vac = √ 2 2fr RC
(10.79)
162
Y. S. Lee and M. H. L. Chow
The ripple factor RF can be found from 1 RF = √ 2 2fr RC − 1
(10.80)
10.5.2.1 Inrush Current The resistor Rinrush in Fig. 10.26 is used to limit the inrush current imposed on the diodes during the instant when the rectiﬁer is being connected to the supply. The inrush current can be very large because capacitor C has zero charge initially. The worst case occurs when the rectiﬁer is connected to the supply at its maximum voltage. The worstcase inrush current can be estimated from Iinrush =
Vm Rsec + RESR
(10.81)
where Rsec is the equivalent resistance looking from the secondary transformer and RESR is the equivalent series resistance (ESR) of the ﬁltering capacitor. Hence the employed diode should be able to withstand the inrush current for a half cycle of the input voltage. In other words, the Maximum Allowable Surge Current (IFSM ) rating of the employed diodes must be higher than the inrush current. The equivalent resistance associated with the transformer windings and the ﬁltering capacitor is usually sufﬁcient to limit the inrush current to an acceptable level. However, in cases where the transformer is omitted, e.g. the rectiﬁer of an offline switchmode supply, resistor Rinrush must be added for controlling the inrush current. Consider as an example, a singlephase bridge rectiﬁer, which is to be connected to a 120V–60Hz source (without transformer). Assume that the IFSM rating of the diodes is 150 A for an interval of 8.3 ms. If the ESR of the ﬁltering capacitor is zero, the value of the resistor for limiting inrush current resistance can be estimated to be 1.13 using Eq. (10.81).
(which is known as forced turnoff). The temporary short circuit during the reverse recovery period may result in large reverse current, excessive ringing, and large power dissipation, all of which are highly undesirable. The forward recovery time of a diode may be understood as the time a nonconducting diode takes to change to the fullyon state when a forward current is suddenly forced into it (which is known as forced turnon). Before the diode reaches the fullyon state, the forward voltage drop during the forward recovery time can be signiﬁcantly higher than the normal onstate voltage drop. This may cause voltage spikes in the circuit. It should be interesting to note that, as far as circuit operation is concerned, a diode with a long reverse recovery time is similar to a diode with a large parasitic capacitance. A diode with a long forward recovery time is similar to a diode with a large parasitic inductance. (Spikes caused by the slow forward recovery of diodes are often wrongly thought to be caused by leakage inductance.) Comparatively, the adverse effect of a long reverse recovery time is much worse than that of a long forward recovery time. Among commonly used diodes, the Schottky diode has the shortest forward and reverse recovery times. Schottky diodes are therefore most suitable for highfrequency applications. However, Schottky diodes have relatively low reverse breakdown voltage (normally lower than 200 V) and large leakage current. If, due to these limitations, Schottky diodes cannot be used, ultrafast diodes should be used in highfrequency converter circuits. Using the example of a forward converter, the operations of a forward rectiﬁer diode, a ﬂywheel diode, and a clamping diode will be studied in Subsection 10.6.1. Because of the difﬁculties encountered in the full analyses taking into account parasitic/stray/leakage components, PSpice simulations are extensively used here to study the following: • •
•
10.6 Highfrequency Diode Rectiﬁer Circuits In highfrequency converters, diodes perform various functions, such as rectifying, ﬂywheeling, and clamping. One special quality a highfrequency diode must possess is a fast switching speed. In technical terms, it must have a short reverse recovery time and a short forward recovery time. The reverse recovery time of a diode may be understood as the time a forwardly conducting diode takes to recover to a blocking state when the voltage across it is suddenly reversed
• • •
The idealized operation of the converter. The adverse effects of relatively slow rectiﬁers (e.g. the socalled ultrafast diodes, which are actually much slower than Schottky diodes). The improvement achievable by using highspeed rectiﬁers (Schottky diodes). The effects of leakage inductance of the transformer. The use of snubber circuits to reduce ringing. The operation of a practical converter with snubber circuits.
Using the example of a ﬂyback converter, the operations of a ﬂyback rectiﬁer diode and a clamping diode will also be studied in Subsection 10.6.2. The design considerations for highfrequency diode rectiﬁer circuits will be discussed in Subsection 10.6.3. Some precautions which must be taken in the interpretation of computer simulation results are briefed in Subsection 10.6.4.
10
163
Diode Rectiﬁers
The switch M1 is turned on at t = 0. The voltage at node 3, denoted as V(3), is
10.6.1 Forward Rectiﬁer Diode, Flywheel Diode, and Magneticreset Clamping Diode in a Forward Converter
V (3) = 0
10.6.1.1 Ideal Circuit Figure 10.28 shows the basic circuit of a forward converter. Figure 10.29 shows the idealized steadystate waveforms for continuousmode operation (the current in L1 being continuous). These waveforms are obtained from PSpice simulations, based on the following assumptions: •
•
V (6) = VIN Ns /Np
Rectiﬁer diode DR , ﬂywheel diode DF , and magneticreset clamping diode DM are ideal diodes with inﬁnitely fast switching speed. Electronic switch M1 is an idealized MOS switch with inﬁnitely fast switching speed and
d I (DR) NS 1 − Vo = VIN dt NP L1
V (9) = VIN (NS /NP )
V (100) = −VIN
1. For 0 < t < DT (D is the duty cycle of the MOS switch M1 and T is the switching period of the converter. M1 is turned on when V1(VPULSE) is 15 V, and turned off when V1(VPULSE) is 0 V).
for
for 0 < t < DT
Notes:
T1 I(DR) DR LSNS
LPNP
VIN 5 Pulse
99
DF
Io Vo
I(L1) CL
3 M1
L1
9
RL
VIN = 50 V L1 = 8 mH CL = 300 mF LP = 0.576 mH LM = 0.576 mH
LM NM
0
0V
LS = 0.036 mH RL = 0.35 W NP : NM : NS = 4 : 4 : 1
0V
0 < t < DT
(10.85)
(10.86)
A magnetizing current builds up linearly in LP . This magnetizing current reaches the maximum value of (VIN DT )/LP at t = DT .
100 6
(10.84)
The magneticrest clamping diode DM is reversely biased by the negative voltage at node 100. Assuming that LM and LP have the same number of turns, we have
Referring to the circuit shown in Fig. 10.28 and the waveforms shown in Fig. 10.29, the operation of the converter can be explained as follows:
1
(10.83)
where Vo is the dc output voltage of the converter. The ﬂywheel diode DF is reversely biased by V(9), the voltage at node 9.
It should be noted that PSpice does not allow a switch to have zero onstate resistance and inﬁnite offstate resistance. Transformer T1 has a coupling coefﬁcient of 0.99999999. PSpice does not accept a coupling coefﬁcient of 1. The switching operation of the converter has reached a steady state.
DM
(10.82)
This voltage drives a current I(DR) (current through rectiﬁer diode DR ) into the output circuit to produce the output voltage Vo . The rate of increase of I(DR) is given by
Offstate resistance = 1 M
•
0 < t < DT
The voltage induced at node 6 of the secondary winding LS is
Onstate resistance = 0.067
•
for
0
FIGURE 10.28 Basic circuit of forward converter.
164
Y. S. Lee and M. H. L. Chow 20V
ON 0V V1(VPULSE)
OFF DT
ON
OFF
T
500mA 0A –500mA I(DM) 5.0A 0A –5.0A ID(M1) 100V 0V –100V V(100) 200V 0V –200V V(3) 20V 0V –20V V(6) 20V 0V –20V V(9) 20V 0V –20V V(6,9) 20A 0A –20A I(DR) 20A 0A –20A I(DF) 20A 15A 10A I(L1) 5.1V 5.0V 4.9V 0s V(99)
4us 5us DT
10us T
15us Time
FIGURE 10.29 Idealized steadystate waveforms of forward converter for continuousmode operation.
20us
10
165
Diode Rectiﬁers
2. For DT < t < 2DT The switch M1 is turned off at t = DT . The collapse of magnetic ﬂux induces a back emf in LM , which is equal to LP , to turnon the clamping diode DM . The magnetizing current in LM drops (from the maximum value of (VIN DT )/LP , as mentioned above) at the rate of VIN /LP . It reaches zero at t = 2DT . The back emf induced across LP is equal to VIN . The voltage at node 3 is V (3) = 2VIN
for DT < t < 2DT
The maximum current in the forward rectifying diode DR and ﬂywheel diode DF is I (DR)max = I (DF )max = Io +
•
(10.87)
The back emf across LS forces DR to stop conducting. The inductive current in L1 forces the ﬂywheel diode DF to conduct. I(L1) (current through L1 ) falls at the rate of −Vo d I (L1) = dt L1
•
V (DR)max = V (DF )max = V (6, 9)max = VIN •
V (DM )max = VIN •
•
V (3) = VIN
(10.91)
Inductive current I(L1) continues to fall at the rate of −Vo d I (L1) = dt L1
(10.92)
The switching cycle restarts when the switch M1 is turned on again at t = T . From the waveforms shown in Fig. 10.29, the following useful information (for continuousmode operation) can be found: •
The output voltage Vo is equal to the average value of V(9). Vo = D
NS VIN NP
VIN LP
(10.97)
NS I (DR)max + I (DM )max NP NS 1 Vo VIN (1 − D) T + DT Io + = NP 2 L1 LP (10.98)
(10.90)
The voltage across LS is also zero. V (6) = 0
(10.96)
The maximum current in the switch M1, denoted as ID(M1), is ID(M 1)max =
3. For 2DT < t < T DM stops conducting at t = 2DT . The voltage across LM then falls to zero. The voltage across LP is zero.
(10.95)
The maximum current in DM is I (DM )max = DT
for DT < t < 2DT (10.89)
NS NP
The maximum reverse voltage of DM is
The voltage across DR , denoted as V(6,9) (the voltage at node 6 with respect to node 9), is
= −VIN (NS /NP )
(10.94)
where Vo = DVIN (NS /NP ) and Io is the output loading current. The maximum reverse voltage of DR and DF is
(10.88)
V (DR) = V (6, 9)
1 Vo (1 − D) T 2 L1
(10.93)
It should, however, be understood that, due to the nonideal characteristics of practical components, the idealized waveforms shown in Fig. 10.29 cannot actually be achieved in the real world. In the following, the effects of nonideal diodes and transformers will be examined. 10.6.1.2 Circuit Using Ultrafast Diodes Figure 10.30 shows the waveforms of the forward converter (circuit given in Fig. 10.28) when ultrafast diodes are used as DM , DR , and DF . (Note that ultrafast diodes are actually much slower than Schottky diodes.) The waveforms are obtained by PSpice simulations, based on the following assumptions: • • • •
DM is an MUR460 ultrafast diode. DR and DF are MUR1560 ultrafast diodes. M1 is an IRF640 MOS transistor. Transformer T1 has a coupling coefﬁcient of 0.99999999 (which may be assumed to be 1). The switching operation of the converter has reached a steady state.
166
Y. S. Lee and M. H. L. Chow 20V ON 0V V1(VPULSE)
OFF DT
ON
OFF
T
500mA 0A –500mA I(DM) 40A 0A –40A ID(M1) 100V 0V –100V V(100) 200V 0V –200V V(3) 20V 0V –20V V(6) 20V 0V –20V V(9) 20V 0V –20V V(6,9) 100A 0A –100A I(DR) 100A 0A –100A I(DF) 15A 10A 5A I(L1) 3.8V 3.7V 3.6V 0s V(99)
4us 5us DT
10us T
15us
20us
Time
FIGURE 10.30 Waveforms of forward converter using “ultrafast” diodes (which are actually much slower than Schottky diodes).
10
167
Diode Rectiﬁers
It is observed that a large spike appears in the current waveforms of diodes DR and DF (denoted as I(DR) and I(DF) in Fig. 10.30) whenever the MOS transistor M1 is turned on. This is due to the relatively slow reverse recovery of the ﬂywheel diode DF . During the reverse recovery time, the positive voltage suddenly appearing across LS (which is equal to VIN (NS /NP )) drives a large transient current through DR and DF . This current spike results in large current stress and power dissipation in DR , DF , and M1 . A method of reducing the current spikes is to use Schottky diodes as DR and DF , as described below.
10.6.1.3 Circuit Using Schottky Diodes In order to reduce the current spikes caused by the slow reverse recovery of rectiﬁers, Schottky diodes are now used as DR and DF .The assumptions made here are (referring to the circuit shown in Fig. 10.28): • • • • •
DR and DF are MBR2540 Schottky diodes. DM is an MUR460 ultrafast diode. M1 is an IRF640 MOS transistor. Transformer T1 has a coupling coefﬁcient of 0.99999999. The switching operation of the converter has reached a steady state.
The new simulated waveforms are given in Fig. 10.31. It is found that, by employing Schottky diodes as DR and DF , the amplitudes of the current spikes in ID(M1), I(DR), and I(DF) can be reduced to practically zero. This solves the slowspeed problem of ultrafast diodes.
10.6.1.4 Circuit with Practical Transformer The simulation results given above in Figs. 10.29–10.31 (for the forward converter circuit shown in Fig. 10.28) are based on the assumption that transformer T1 has effectively no leakage inductance (with coupling coefﬁcient K = 0.99999999). It is, however, found that when a practical transformer (having a slightly lower K ) is used, severe ringings occur. Figure 10.32 shows some simulation results to demonstrate this phenomenon, where the following assumptions are made: • • • •
• •
DR and DF are MBR2540 Schottky diodes. DM is an MUR460 ultrafast diode. M1 is an IRF640 MOS transistor. Transformer T1 has a practical coupling coefﬁcient of 0.996. The effective winding resistance of LP is 0.1 . The effective winding resistance of LM is 0.4 . The effective winding resistance of LS is 0.01 . The effective series resistance of the output ﬁltering capacitor is 0.05 . The switching operation of the converter has reached a steady state.
The resultant waveforms shown in Fig. 10.32 indicate that there are large voltage and current ringings in the circuit. These ringings are caused by the resonant circuits formed by the leakage inductance of the transformer and the parasitic capacitances of diodes and transistor. A practical converter may therefore need snubber circuits to damp these ringings, as described below.
10.6.1.5 Circuit with Snubber Across the Transformer In order to suppress the ringing voltage caused by the resonant circuit formed by transformer leakage inductance and the parasitic capacitance of the MOS switch, a snubber circuit, shown as R1 and C1 in Fig. 10.33, is now connected across the primary winding of transformer T1 . The new waveforms are shown in Fig. 10.34. Here the draintosource voltage waveform of the MOS transistor, V(3), is found to be acceptable. However, there are still large ringing voltages across the output rectiﬁers (V(6,9) and V(9)). In order to damp the ringing voltages across the output rectiﬁers, additional snubber circuits across the rectiﬁers may therefore also be required in a practical circuit, as described below.
10.6.1.6 Practical Circuit Figure 10.35 shows a practical forward converter with snubber circuits added also to rectiﬁers (R2 C2 for DR and R3 C3 for DF ) to reduce the voltage ringing. Figures 10.36 and 10.37 show the resultant voltage and current waveforms. Figure 10.36 is for continuousmode operation (RL = 0.35 ), where I(L1) (current in L1 ) is continuous. Figure 10.37 is for discontinuousmode operation (RL = 10 ), where I(L1) becomes discontinuous due to an increased value of RL . These waveforms are considered to be acceptable. The design considerations of diode rectiﬁer circuits in highfrequency converters will be discussed later in Subsection 10.6.3.
10.6.2 Flyback Rectiﬁer Diode and Clamping Diode in a Flyback Converter 10.6.2.1 Ideal Circuit Figure 10.38 shows the basic circuit of a ﬂyback converter. Due to its simple circuit, this type of converter is widely used in lowcost lowpower applications. Discontinuousmode operation (meaning that the magnetizing current in the transformer falls to zero before the end of each switching cycle) is often used because it offers the advantages of easy control and low diode reverserecovery loss. Figure 10.39 shows the idealized steadystate waveforms for discontinuousmode operation. These waveforms are obtained from PSpice simulations, based on
168
Y. S. Lee and M. H. L. Chow
20V ON 0V V1(VPULSE)
OFF DT
ON
OFF
T
500mA 0A –500mA I(DM) 5.0A 0A –5.0A ID(M1) 100V 0V –100V V(100) 200V 0V –200V V(3) 20V 0V –20V V(6) 20V 0V –20V V(9) 20V 0V –20V V(6,9) 20A 0A –20A I(DR) 20A 0A –20A I(DF) 20A 15A 10A I(L1) 4.9V 4.8V 4.7V 0s V(99)
4us 5us DT
10us T
15us Time
FIGURE 10.31 Waveforms of forward converter using Schottky (fastspeed) diodes as output rectiﬁers.
20us
10
169
Diode Rectiﬁers 20V ON 0V V1(VPULSE)
OFF DT
ON
OFF
T
4.0A 0A –4.0A I(DM) 4.0A 0A –4.0A ID(M1) 400V 0V –400V V(100) 400V 0V –400V V(3) 100V 0V –100V V(6) 40V 0V –40V V(9) 100V 0V –100V V(6,9) 20A 0A –20A I(DR) 20A 0A –20A I(DF) 15.0A 12.5A 10.0A I(L1) 4.2V 4.1V 0s V(99)
4us 5us DT
10us T
15us
20us
Time
FIGURE 10.32 Waveforms of forward converter with practical transformer and output ﬁltering capacitor having nonzero series effective resistance.
170
Y. S. Lee and M. H. L. Chow VIN = 50 V, DM = MUR460
DM 100 T1 6
1 R1 LP
2 N VIN C1 P 3 LM M1 5 NM Pulse
DR
9
LSNS DF
L1
DR = MBR2540, DF = MBR2540 99
CL
Vo RL
M1 = IRF640, R1 = 24 W C1 = 3000 pF, CL = 3500 mF ESR of CL = 0.05 W, L1 = 8 mH LP = 0.576 mH, LM = 0.576 mH LS = 0.036 mH, NP : NM : NS = 4 : 4 : 1
0
RL = 0.35 W Effective winding resistance of LP =0.1 W Effective winding resistance of LM =0.4 W Effective winding resistance of LS = 0.01 W
0
Coupling coefficient K = 0.996
FIGURE 10.33 Forward converter with snubber circuit (R1 C1 ) across transformer.
the following assumptions: • •
DR is an idealized rectiﬁer diode with inﬁnitely fast switching speed. M1 is an idealized MOS switch with inﬁnitely fast switching speed and Onstate resistance = 0.067 Offstate resistance = 1 M
• •
Transformer T1 has a coupling coefﬁcient of 0.99999999. The switching operation of the converter has reached a steady state.
Referring to the circuit shown in Fig. 10.38 and the waveforms shown in Fig. 10.39, the operation of the converter can be explained as follows:
t = DT to the energy stored in the secondarywinding current I(LS) just after t = DT : 1 1 LP [I (LP)]2 = LS [I (LS)]2 2 2 2 VIN 1 1 DT = LS [I (LS)]2 LP LP 2 2 LP VIN I (LS) = DT LS LP I (LS) =
NP VIN DT N S LP
(10.100) (10.101)
(10.102) (10.103)
The amplitude of I(LS) falls at the rate of
1. For 0 < t < DT The switch M1 is turned on at t = 0.
−Vo dI (LS) = dt LS
V (3) = 0
and I(LS) falls to zero at t = (D + D2 )T. Since D2 Vo = VIN (NS /NP )D
for 0 < t < DT
The current in M1 , denoted as ID(M1), increases at the rate of VIN d ID(M 1) = dt LP
(10.99)
The output rectiﬁer DR is reversely biased. 2. For DT < t < (D + D2 )T The switching M1 is turned off at t = DT . The collapse of magnetic ﬂux induces a back emf in LS to turnon the output rectiﬁer DR . The initial amplitude of the rectiﬁer current I(DR), which is also denoted as I(LS), can be found by equating the energy stored in the primarywinding current I(LP) just before
D2 =
VIN NS D Vo N P
(10.104)
(10.105)
D2 is effectively the duty cycle of the output rectiﬁer DR . 3. For (D + D2 )T < t < T The output rectiﬁer DR is off. The output capacitor CL provides the output current to the load RL . The switching cycle restarts when the switch M1 is turned on again at t = T . From the waveforms shown in Fig. 10.39, the following information (for discontinuousmode operation)
10
171
Diode Rectiﬁers
20V ON 0V V1(VPULSE)
OFF DT
ON
OFF
T
1.0A 0A –1.0A I(DM) 4.0A 0A –4.0A ID(M1) 100V 0V –100V V(100) 200V 0V –200V V(3) 50V 0V –50V V(6) 40V 0V –40V V(9) 40V 0V –40V V(6,9) 20A 0A –20A I(DR) 20A 0A –20A I(DF) 15.0A 12.5A 10.0A I(L1) 4.2V 4.1V 0s V(99)
4us 5us DT
10us T
15us Time
FIGURE 10.34 Waveforms of forward converter with snubber circuit across the transformer.
20us
172
Y. S. Lee and M. H. L. Chow VIN = 50 V, DM = MUR460 DM 1
2 VIN
100 R2 C2 T1 69 DR 6
R1 LP
LS
NP
NS
C1
5 M1
M1 = IRF640, R1 = 24 W 9
L1 R3
DF
3 LM
DR = MBR2540, DF = MBR2540
90 C3
99
CL
Vo
C1 = 3000 pF, C2 = 10 nF, C3 = 10 nF
CL = 3500 mF, ESR of CL = 0.05 W RL L = 8 mH, L = 0.576 mH 1 P LM = 0.576 mH, LS = 0.036 mH
0
NP : NM : NS = 4: 4 : 1 Effective winding resistance of LP = 0.1 W
NM
Pulse
R2 = 10 W, R3 = 10 W
Effective winding resistance of LM = 0.4 W Effective winding resistance of LS = 0.01 W Coupling coefficient K = 0.996
0
FIGURE 10.35 Practical forward converter with snubber circuits across the transformer and rectiﬁers.
can be obtained: •
The maximum value of the current in the switch M1 is ID(M 1)max =
•
NP VIN DT NS LP
(10.107)
The output voltage Vo can be found by equating the input energy to the output energy within a switching cycle. VIN ×[Charge taken from VIN in a switching cycle] =
Vo2 RL T
VIN
•
(10.106)
The maximum value of the current in the output rectiﬁer DR is I (DR)max =
•
VIN DT LP
V2 1 DT VIN = o T DT 2 LP RL RL T Vo = DVIN 2LP
NS + Vo NP
• • • •
(10.108)
(10.109)
The maximum reverse voltage of DR , V(6,9) (which is the voltage at node 6 with respect to node 9), is V (DR)max = V (6, 9)max = VIN
damp the ringing voltage across the output rectiﬁer DR , and a resistor–capacitordiode clamping (R1C1DS ) is used to clamp the ringing voltage across the switch M1 . What the diode DS does here is to allow the energy stored by the current in the leakage inductance to be converted to the form of a dc voltage across the clamping capacitor C1 . The energy transferred to C1 is then dissipated slowly in the parallel resistor R1 , without ringing problems. The simulated waveforms of the ﬂyback converter (circuit given in Fig. 10.40) for discontinuousmode operation are shown in Fig. 10.41, where the following assumptions are made:
• •
DR and DS are MUR460 ultrafast diodes. M1 is an IRF640 MOS transistor. Transformer T1 has a practical coupling coefﬁcient of 0.992. The effective winding resistance of LP is 0.025 . The effective winding resistance of LS is 0.1 . The effective series resistance of the output ﬁltering capacitor CL is 0.05 . The switching operation of the converter has reached a steady state.
The waveforms shown in Fig. 10.40 are considered to be acceptable.
(10.110)
10.6.2.2 Practical Circuit When a practical transformer (with leakage inductance) is used in the ﬂyback converter circuit shown in Fig. 10.38, there will be large ringings. In order to reduce these ringings to practically acceptable levels, snubber and clamping circuits have to be added. Figure 10.40 shows a practical ﬂyback converter circuit where a resistor–capacitor snubber (R2 C2 ) is used to
10.6.3 Design Considerations In the design of rectiﬁer circuits, it is necessary for the designer to determine the voltage and current ratings of the diodes. The idealized waveforms and expressions for the maximum diode voltages and currents given under the heading of “Ideal circuit” above (for both forward and ﬂyback converters) are a good starting point. However, when parasitic/stray components are also considered, the simulation results given under
10
173
Diode Rectiﬁers
20V ON 0V V1(VPULSE)
OFF DT
ON
OFF
T
1.0A 0A –1.0A I(DM) 4.0A 0A –4.0A ID(M1) 100V 0V –100V V(100) 200V 0V –200V V(3) 20V 0V –20V V(6) 20V 0V –20V V(9) 20V 0V –20V V(6,9) 20A 0A –20A I(DR) 20A 0A –20A I(DF) 15.0A 12.5A 10.0A I(L1) 4.2V 4.1V 0s V(99)
4us 5us DT
10us T
15us Time
FIGURE 10.36 Waveforms of practical forward converter for continuousmode operation.
20us
174
Y. S. Lee and M. H. L. Chow
20V ON 0V V1(VPULSE)
OFF DT
ON
OFF
T
500mA 0A –500mA I(DM) 2.0A 0A –2.0A ID(M1) 100V 0V –100V V(100) 200V 0V –200V V(3) 20V 0V –20V V(6) 20V 0V –20V V(9) 40 0V –40V V(6,9) 4.0A 0A –4.0A I(DR) 4.0A 0A –4.0A I(DF) 4.0A 0A –4.0A I(L1) 7.6V 7.5V 7.4V 0s V(99)
4us 5us DT
10us T
15us Time
FIGURE 10.37 Waveforms of practical forward converter for discontinuousmode operation.
20us
10
175
Diode Rectiﬁers T1
1
DR
6
9 Vo VIN = 60 V
LP
LSNS
CL
RL
NP
LP = 100 µH
3
VIN
CL = 100 µF LS = 400 µH
0
RL = 400 W
M1 5
NP : NS = 1 : 2
Pulse 0
FIGURE 10.38 Basic circuit of ﬂyback converter.
20V ON 0V V1(VPULSE)
OFF
ON
DT
OFF
T
4.0A 0A –4.0A ID(M1) 200V 0V –200V V(3) 200V 0V –200V V(6) 109.2V 109.1V 109.0V V(9) 400V 0V –400V V(6,9) 2.0A 0A –2.0A 0s I(DR) or I(LS)
4us 5us DT
(D+D2)T
10us T
15us Time
FIGURE 10.39 Idealized steadystate waveforms of ﬂyback converter for discontinuousmode operation.
20us
176
Y. S. Lee and M. H. L. Chow C2
R2
VIN = 60 V, DS = MUR460 T1
1
C1
R1 DS
6
Lp
LS
Np
NS
3
0
VIN 2 5
DR
9
CL
DR = MUR460,M1 = IRF640 Vo RL
R1 = 4.7 kW, R2 = 100 W C1 = 0.1 mF, C2 = 680 pF CL = 100 mF, ESR of CL = 0.05 W LP = 100 mH, LS = 400 mH RL = 400 W
M1
NP : NS = 1 : 2 Effective winding resistance of LP = 0.025 W
Pulse
Effective winding resistance of LS = 0.1 W Coupling coefficient K = 0.992 0
FIGURE 10.40 Practical ﬂyback converter circuit. 20V ON 0V V1(VPULSE)
OFF
ON
DT
OFF
T
4.0A 0A –4.0A ID(M1) 200V 0V –200V V(3) 200V 0V –200V V(6) 98.8V 98.7V 98.6V V(9) 400V 0V –400V V(6,9) 1.0A 0A –1.0A I(DR) 2.0A 0A –2.0A I(DS) 200V 0V –200V 0s V(3,2)
4us 5us DT
(D+D2)T
10us T
15us Time
FIGURE 10.41 Waveforms of practical ﬂyback converter for discontinuousmode operation.
20us
10
177
Diode Rectiﬁers
“Practical circuit” are much more useful for the determination of the voltage and current ratings of the highfrequency rectiﬁer diodes. Assuming that the voltage and current ratings have been determined, proper diodes can be selected to meet the requirements. The following are some general guidelines on the selection of diodes: •
•
•
For lowvoltage applications, Schottky diodes should be used because they have very fast switching speed and low forward voltage drop. If Schottky diodes cannot be used, either because of their low reverse breakdown voltage or because of their large leakage current (when reversely biased), ultrafast diodes should be used. The reverse breakdownvoltage rating of the diode should be reasonably higher (e.g. 10 or 20% higher) than the maximum reverse voltage, the diode is expected to encounter under the worstcase condition. However, an overlyconservative design (using a diode with much higher breakdown voltage than necessary) would result in a lower rectiﬁer efﬁciency, because a diode having a higher reversevoltage rating would normally have a larger voltage drop when it is conducting. The current rating of the diode should be substantially higher than the maximum current the diode is expected to carry during normal operation. Using a diode with a relatively large current rating has the following advantages: •
•
It reduces the possibility of damage due to transients caused by startup, accidental short circuit, or random turning on and off of the converter. It reduces the forward voltage drop because the diode is operated in the lower current region of the V–I characteristic.
In some of the “highefﬁciency” converter circuits, the current rating of the output rectiﬁer can be many times larger than the actual current expected in the rectiﬁer. In this way, a higher efﬁciency is achieved at the expense of a larger silicon area. In the design of R–C snubber circuits for rectiﬁers, it should be understood that a larger C (and a smaller R) will give
better damping. However, a large C (and a small R) will result in a large switching loss (which is equal to 0.5CV 2 f ). As a guideline, a capacitor with ﬁve to ten times the junction capacitance of the rectiﬁer may be used as a starting point for iterations. The value of the resistor should be chosen to provide a slightly underdamped operating condition.
10.6.4 Precautions in Interpreting Simulation Results In using the simulated waveforms as references for design purposes, attention should be paid to the following: •
•
The voltage/current spikes that appear in the practically measured waveforms may not appear in the simulated waveforms. This is due to the lack of a model in the computer simulation to simulate unwanted coupling among the practical components. Most of the computer models of diodes, including those used in the simulations given above, do not take into account the effects of the forward recovery time. (The forward recovery time is not even mentioned in most manufacturers’ data sheets.) However, it is also interesting to note that in most cases the effect of the forward recovery time of a diode is masked by that of the effective inductance in series with the diode (e.g. the leakage inductance of a transformer).
Further Reading 1. Rectiﬁer Applications Handbook, 3rd ed., Phoenix, Ariz.: Motorola, Inc., 1993. 2. M. H. Rashid, Power Electronics: Circuits, Devices, and Applications, 2nd ed., Englewood Cliffs, NJ: Prentice Hall, Inc., 1993. 3. Y.S. Lee, ComputerAided Analysis and Design of SwitchMode Power Supplies, New York: Marcel Dekker, Inc., 1993. 4. J. W. Nilsson, Introduction to PSpice Manual, Electric Circuits Using OrCAD Release 9.1, 4th ed., Upper Saddle River, NJ: Prentice Hall, Inc., 2000. 5. J. Keown, OrCAD PSpice and Circuit Analysis, 4th ed., Upper Saddle River, NJ: Prentice Hall, Inc., 2001.
11 Singlephase Controlled Rectiﬁers José Rodríguez, Ph.D., Pablo Lezana, Samir Kouro, and Alejandro Weinstein Department of Electronics, Universidad Técnica Federico Santa María, Valparaíso, Chile
11.1 Introduction .......................................................................................... 179 11.2 Linecommutated Singlephase Controlled Rectiﬁers ..................................... 179 11.2.1 Singlephase Halfwave Rectiﬁer • 11.2.2 Biphase Halfwave Rectiﬁer • 11.2.3 Singlephase Bridge Rectiﬁer • 11.2.4 Analysis of the Input Current • 11.2.5 Power Factor of the Rectiﬁer • 11.2.6 The Commutation of the Thyristors • 11.2.7 Operation in the Inverting Mode • 11.2.8 Applications
11.3 Unity Power Factor Singlephase Rectiﬁers .................................................. 188 11.3.1 The Problem of Power Factor in Singlephase Linecommutated Rectiﬁers • 11.3.2 Standards for Harmonics in Singlephase Rectiﬁers • 11.3.3 The Singlephase Boost Rectiﬁer • 11.3.4 Voltage Doubler PWM Rectiﬁer • 11.3.5 The PWM Rectiﬁer in Bridge Connection • 11.3.6 Applications of Unity Power Factor Rectiﬁers
References ............................................................................................. 199
11.1 Introduction This chapter is dedicated to singlephase controlled rectiﬁers, which are used in a wide range of applications. As shown in Fig. 11.1, singlephase rectiﬁers can be classiﬁed into two big categories: (i) Topologies working with low switching frequency, also known as line commutated or phase controlled rectiﬁers. (ii) Circuits working with high switching frequency, also known as power factor correctors (PFCs). Linecommutated rectiﬁers with diodes, covered in a previous chapter of this handbook, do not allow the control of power being converted from ac to dc. This control can be achieved with the use of thyristors. These controlled rectiﬁers are addressed in the ﬁrst part of this chapter. In the last years, increasing attention has been paid to the control of current harmonics present at the input side of the rectiﬁers, originating from a very important development in the socalled PFC. These circuits use power transistors working with high switching frequency to improve the waveform quality of the input current, increasing the power factor. High power factor rectiﬁers can be classiﬁed in regenerative and nonregenerative topologies and they are covered in the second part of this chapter.
Copyright © 2007, 2001, Elsevier Inc. All rights reserved.
11.2 Linecommutated Singlephase Controlled Rectiﬁers 11.2.1 Singlephase Halfwave Rectiﬁer The singlephase halfwave rectiﬁer uses a single thyristor to control the load voltage as shown in Fig. 11.2. The thyristor will conduct, onstate, when the voltage vT is positive and a ﬁring current pulse iG is applied to the gate terminal. The control of the load voltage is performed by delaying the ﬁring pulse by an angle α. The ﬁring angle α is measured from the position where a diode would naturally conduct. In case of Fig. 11.2 the angle α is measured from the zerocrossing point of the supply voltage vs . The load in Fig. 11.2 is resistive and therefore the current id has the same waveform of the load voltage. The thyristor goes to the nonconducting condition, offstate, when the load voltage, and consequently the current, reaches a negative value. The load average voltage is given by Vdα =
1 2π
α
π
Vmax sin(ωt )d(ωt ) =
Vmax (1 + cos α) 2π (11.1)
where Vmax is the supply peak voltage. Hence, it can be seen from Eq. (11.1) that changing the ﬁring angle α controls
179
180
J. Rodríguez et al. Single Phase Rectifiers
Power factor Correction (PFC)
Line Commutated
Diode
Thyristor
Nonregenerative
Regenerative (AFE)
Boost
Voltage Doubler
Others
Bridge
FIGURE 11.1 Singlephase rectiﬁer classiﬁcation. vd id
vT
id O
+ iG
+ vs
α
R
vd
id,vd
π
2π
ωt
vs iG
_
ωt
O
FIGURE 11.2 Singlethyristor rectiﬁer with resistive load.
both the load average voltage and the amount of transferred power. Figure 11.3a shows the rectiﬁer waveforms for an R–L load. When the thyristor is turned on, the voltage across the inductance is vL = vs − vR = L
did dt
(11.2)
where vR is the voltage in the resistance R, given by vR = R·id . If vs − vR > 0, from Eq. (11.2) holds that the load current increases its value. On the other hand, id decreases its value when vs − vR < 0. The load current is given by id (ωt ) =
1 ωL
ωt
vL dθ
(11.3)
α
Graphically, Eq. (11.3) means that the load current id is equal to zero when A1 = A2 , maintaining the thyristor in conduction state even when vs < 0. When an inductive–active load is connected to the rectiﬁer, as illustrated in Fig. 11.3b, the thyristor will be turned on if the ﬁring pulse is applied to the gate when vs > E d . Again, the thyristor will remain in the onstate until A1 = A2 . When the thyristor is turned off, the load voltage will be vd = Ed .
11.2.2 Biphase Halfwave Rectiﬁer The biphase halfwave rectiﬁer, shown in Fig. 11.4, uses a centertapped transformer to provide two voltages v1 and v2 . These two voltages are 180◦ out of phase with respect to the midpoint neutral N. In this scheme, the load is fed via thyristors T1 and T2 during each positive cycle of voltages v1 and v2 , respectively, while the load current returns via the neutral N. As illustrated in Fig. 11.4, thyristor T1 can be ﬁred into the onstate at any time while voltage vT 1 > 0. The ﬁring pulses are delayed by an angle α with respect to the instant where diodes would conduct. Also the current paths for each conduction state are presented in Fig. 11.4. Thyristor T1 remains in the onstate until the load current tends to a negative value. Thyristor T2 is ﬁred into the onstate when vT 2 > 0, which corresponds in Fig. 11.4 to the condition when v2 > 0. The mean value of the load voltage with resistive load is determined by Vdiα =
1 π
α
π
Vmax sin(ωt )d(ωt ) =
Vmax (1 + cos α) π (11.4)
The ac supply current is equal to iT 1 (N2 /N1 ) when T1 is in the onstate and −iT 2 (N2 /N1 ) when T2 is in the onstate, where N2 /N1 is the transformer turns ratio.
11
181
Singlephase Controlled Rectiﬁers Area A1 id
vL
+
+
iG
vs
vd
L
π
ωt
2π
R
vd
_
Area A2 vR,vd
0 vR
vd
vR
vd
vs
iG ωt
0
(a) Area A1 vL
+ vs
+
iG
id
vd
L +E d
vd
0
Area A2
id
vd
Ed
ωt
2π
vd vs
_
iG ωt
0
(b) FIGURE 11.3 Singlethyristor rectiﬁer with: (a) resistiveinductive load and (b) active load.
The effect of the load time constant TL = L/R, on the normalized load current id (t)/îR (t) for a ﬁring angle α = 0◦ is shown in Fig. 11.5. The ripple in the load current reduces as the load inductance increases. If the load inductance L → ∞, then the current is perfectly ﬁltered.
(i) they turnoff thyristors T1 and T2 and (ii) after the commutation, they conduct the load current.
11.2.3 Singlephase Bridge Rectiﬁer Figure 11.6a shows a fully controlled bridge rectiﬁer, which uses four thyristors to control the average load voltage. In addition, Fig. 11.6b shows the halfcontrolled bridge rectiﬁer which uses two thyristors and two diodes. The voltage and current waveforms of the fully controlled bridge rectiﬁer for a resistive load are illustrated in Fig 11.7. Thyristors T1 and T2 must be ﬁred on simultaneously during the positive halfwave of the source voltage vs , to allow the conduction of current. Alternatively, thyristors T3 and T4 must be ﬁred simultaneously during the negative halfwave of the source voltage. To ensure simultaneous ﬁring, thyristors T1 and T2 use the same ﬁring signal. The load voltage is similar to the voltage obtained with the biphase halfwave rectiﬁer. The input current is given by iS = iT 1 − iT 4
rectiﬁer behaves like a current source. With continuous load current, thyristors T1 and T2 remain in the onstate beyond the positive halfwave of the source voltage vs . For this reason, the load voltage vd can have a negative instantaneous value. The ﬁring of thyristors T3 and T4 has two effects:
(11.5)
and its waveform is shown in Fig. 11.7. Figure 11.8 presents the behavior of the fully controlled rectiﬁer with resistive–inductive load (with L → ∞). The high load inductance generates a perfectly ﬁltered current and the
This is the main reason why this type of converters are called “naturally commutated” or “line commutated” rectiﬁers. The supply current iS has the square waveform, as shown in Fig. 11.9, for continuous conduction. In this case, the average load voltage is given by Vdiα =
1 π
π+α
Vmax sin(ωt )d(ωt ) =
α
2Vmax cos α (11.6) π
11.2.4 Analysis of the Input Current Considering a very high inductive load, the input current in a bridgecontrolled rectiﬁer is ﬁltered and presents a square waveform. In addition, the input current is is shifted by the ﬁring angle α with respect to the input voltage vs , as shown in Fig. 11.9a. The input current can be expressed as a Fourier series, where the amplitude of the different harmonics are Ismax, n =
4 Id πn
(n = 1, 3, 5, . . . )
(11.7)
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v1
+
vT 1 iT 1 id
vs
N
v2
T2 N1
N2
R
vd
iT 2
vT2 is
is
is = iT1·
N2 N1
is = iT2·
N2 N1
vd
Vmax
ωt
0 vs ig1
−vs
α
0 ig2
ωt
0 iT1
ωt
0
ωt
iT2 ωt
0 is
ωt
0
FIGURE 11.4 Biphase halfwave rectiﬁer.
TL = 0 id(t)/îR
α = 0°
îR = VmaxIR
TL = 1 ms
1.0 0.8
TL = 3.2 ms 2/π
TL = 10 ms
0.6
TL → ∞
0.4 0.2 0
t
FIGURE 11.5 Effect of the load time constant over the current ripple.
11
183
Singlephase Controlled Rectiﬁers iT1 ig1 + vs
id
P T1
ig1
T3 iT 3
is
T4
+ vd
Load
T1
T2
is
vs
vd
D1
T2
Load
D2
N
iT4
id
P
N
(a)
(b)
FIGURE 11.6 Singlephase bridge rectiﬁer: (a) fully controlled and (b) halfcontrolled.
vd
Vmax
Vmax ωt
0 ig1, ig2
ωt
0
−vs
vs α
0 ig3, ig4
ωt
0 iT1, iT2
ωt
0
ωt
vs
id
−vs
Id
0 ig1, ig2 α
ωt
0 ig3, ig4
ωt
0 iT1, iT2
ωt
0 iT3, iT4
ωt
0
ωt
0
ωt
iT3, iT4 ωt
0
is ωt
0
FIGURE 11.7 Waveforms of a fully controlled bridge rectiﬁer with resistive load.
is
FIGURE 11.8 Waveforms of a fully controlled bridge rectiﬁer with resistive–inductive load (L → ∞).
where n is the harmonic order. The root mean square (rms) value of each harmonic can be expressed as
vs
√
Ismax, n 2 2 Id Isn = √ = π n 2
(11.8)
is Id
0
ωt
φ1 = α
Thus, the rms value of the fundamental current is1 is √ 2 2 Id = 0.9Id Is1 = π
is1
(a)
isn /is1 1
(11.9)
1/3
1/5
1/7
1/9
5
7
9
n
It can be observed from Fig. 11.9a that the displacement angle φ1 of the fundamental current is1 corresponds to the ﬁring angle α. Figure 11.9b shows that in the harmonic spectrum of the input current, only odd harmonics are present with
1
3
(b)
FIGURE 11.9 Input current of the singlephase controlled rectiﬁer in bridge connection: (a) waveforms and (b) harmonics spectrum.
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decreasing amplitude while the frequency increases. Finally the rms value of the input current is is Is = Id
(11.10)
The total harmonic distortion (THD) of the input current can be determined by
THD =
2 Is2 − Is1 Is1
100 = 48.4%
The displacement factor of the fundamental current, obtained from Fig. 11.9a is (11.12)
In the case of nonsinusoidal currents, the active power delivered by the sinusoidal singlephase supply is 1 P= T
T
vs (t )is (t )dt = Vs Is1 cos φ1
Until now, the current commutation between thyristors has been considered to be instantaneous. This condition is not valid in real cases due to the presence of the line inductance L, as shown in Fig. 11.10a. During the commutation, the current through the thyristors cannot change instantaneously, and for this reason, during the commutation angle µ, all four thyristors are conducting simultaneously. Therefore, during the commutation, the following relationship for the load voltage holds
(11.11)
11.2.5 Power Factor of the Rectiﬁer
cos φ1 = cos α
11.2.6 The Commutation of the Thyristors
vd = 0
α ≤ ωt ≤ α + µ
(11.17)
The effect of the commutation on the supply current, voltage waveforms, and the thyristor current waveforms can be observed in Fig. 11.10b. During the commutation, the following expression holds L
dis = vs = Vmax sin(ωt ) α ≤ ωt ≤ α + µ dt
(11.18)
Integrating Eq. (11.18) over the commutation interval yields
Id
−Id
dis =
Vmax L
α+µ/ω
sin(ωt )dt
(11.19)
α/ω
(11.13)
0
From Eq. (11.19), the following relationship for the commutation angle µ is obtained
where Vs is the rms value of the singlephase voltage vs . The apparent power is given by S = Vs Is
(11.14)
The power factor (PF) is deﬁned by PF =
P S
(11.15)
Substitution from Eqs. (11.12), (11.13), and (11.14) in Eq. (11.15) yields PF =
Is1 cos α Is
cos(α + µ) = cos α −
(11.20)
Equation (11.20) shows that an increase of the line inductance L or an increase of the load current Id increases the commutation angle µ. In addition, the commutation angle is affected by the ﬁring angle α. In effect, Eq. (11.18) shows that with different values of α, the supply voltage vs has a different instantaneous value, which produces different dis /dt, thereby affecting the duration of the commutation. Equation (11.17) and the waveform of Fig. 11.10b show that the commutation process reduces the average load voltage Vdα . When the commutation is considered, the expression for the average load voltage is given by
(11.16)
This equation shows clearly that due to the nonsinusoidal waveform of the input current, the power factor of the rectiﬁer is negatively affected both by the ﬁring angle α and by the distortion of the input current. In effect, an increase in the distortion of the current produces an increase in the value of Is in Eq. (11.16), which deteriorates the power factor.
2ωL Id Vmax
Vdα =
1 π
π+α
sin(ωt )d(ωt ) =
α+µ
Vmax [cos(α + µ) + cos α] π (11.21)
Substituting Eq. (11.20) into Eq. (11.21) yields Vdα =
2ωL 2 Vmax cos α − Id π π
(11.22)
11
185
Singlephase Controlled Rectiﬁers iT1
T1
vL
is
T3
L
+
iT3
vd
Id
vs
T4
T2
iT4 (a)
α iT3
iT1
wt
0
vs is wt
0
vd
wt
0 m (b)
vs
FIGURE 11.10 The commutation process: (a) circuit and (b) waveforms.
11.2.7 Operation in the Inverting Mode 90◦, it is possible to obtain a negative aver
When the angle α > age load voltage. In this condition, the power is fed back to the singlephase supply from the load. This operating mode is called inverter or inverting mode, because the energy is transferred from the dc to the ac side. In practical cases, this operating mode is obtained when the load conﬁguration is as shown in Fig. 11.11a. It must be noticed that this rectiﬁer allows unidirectional load current ﬂow. Figure 11.11b shows the waveform of the load voltage with the rectiﬁer in the inverting mode, neglecting the source inductance L.
Section 11.2.6 described how supply inductance increases the conduction interval of the thyristors by the angle µ. As shown in Fig. 11.11c, the thyristor voltage vT 1 has a negative value during the extinction angle γ, deﬁned by γ = 180 − (α + µ)
(11.23)
To ensure that the outgoing thyristor will recover its blocking capability after the commutation, the extinction angle should satisfy the following restriction γ > ωtq
(11.24)
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is
T3
T1
Ld
L
+
vd
vs
VL T2
T4 (a) α = 135° vd
vs
0
−vs ωt Vdia
ig1, ig2 0
ωt
ig3, ig4 0
ωt
(b) −vs
vs 0
ωt vd
m
vT1 0 g
ωt
(c)
FIGURE 11.11 Rectiﬁer in the inverting mode: (a) circuit; (b) waveforms neglecting source inductance L; and (c) waveforms considering L.
where ω is the supply frequency and tq is the thyristor turnoff time. Considering Eqs. (11.23) and (11.24) the maximum ﬁring angle is, in practice, αmax = 180 − µ − γ
(11.25)
If the condition of Eq. (11.25) is not satisﬁed, the commutation process will fail, originating destructive currents.
11.2.8 Applications Important application areas of controlled rectiﬁers include uninterruptible power supplies (UPS), for feeding critical loads. Figure 11.12 shows a simpliﬁed diagram of a singlephase UPS conﬁguration, typically rated for 40%, originating severe overloads in conductors and transformers. Figure 11.15a shows a singlephase rectiﬁer with a capacitive ﬁlter, used in much of today’s lowpower equipment. The input current produced by this rectiﬁer is illustrated in Fig. 11.15b, it appears highly distorted due to the presence of the ﬁlter capacitor. This current has a harmonic content shown in Fig. 11.16 and Table 11.1, with a THDi = 197%. The rectiﬁer in Fig. 11.15 has a very low power factor of PF = 0.45, due mainly to its large harmonic content.
TABLE 11.1 Harmonic content of the current of Fig. 11.15 n In /I1 [%]
3
5
7
9
11
13
15
17
19
21
96.8
90.5
81.7
71.0
59.3
47.3
35.7
25.4
16.8
10.6
11
189
Singlephase Controlled Rectiﬁers
11.3.2 Standards for Harmonics in Singlephase Rectiﬁers The relevance of the problems originated by harmonics in singlephase linecommutated rectiﬁers has motivated some agencies to introduce restrictions to these converters. The IEC 6100032 Class D International Standard establishes limits to all lowpower singlephase equipment having an input current with a “special wave shape” and an active input power P ≤ 600 W. Class D equipment has an input current with a special wave shape contained within the envelope given in Fig. 11.15b. This class of equipment must satisfy certain harmonic limits, shown in Fig. 11.16. It is clear that a singlephase linecommutated rectiﬁer with the parameters shown in Fig. 11.15a is not able to comply with the standard IEC 6100032 Class D. The standard can be satisﬁed only by adding huge passive ﬁlters, which increases the size, weight, and cost of the rectiﬁer. This standard has been the motivation for the development of active methods to improve the quality of the input current and, consequently, the power factor.
11.3.3 The Singlephase Boost Rectiﬁer One of the most important high power factor rectiﬁers, from a theoretical and conceptual point of view, is the socalled singlephase boost rectiﬁer, shown in Fig. 11.17a, which is obtained from a classical noncontrolled bridge rectiﬁer, with the addition of transistor T, diode D, and inductor L. 11.3.3.1 Working Principle, Basic Concepts In boost rectiﬁers, the input current is (t) is controlled by changing the conduction state of transistor T. When
L
transistor T is in the onstate, the singlephase power supply is shortcircuited through the inductance L, as shown in Fig. 11.17b; the diode D avoids the discharge of the ﬁlter capacitor C through the transistor. The current of the inductance iL is given by the following equation vs  diL vL = = dt L L
(11.26)
Due to the fact that vs  > 0, the onstate of transistor T always produces an increase in the inductance current iL and consequently an increase in the absolute value of the source current is . When transistor T is turned off, the inductor current iL cannot be interrupted abruptly and ﬂows through diode D, charging capacitor C. This is observed in the equivalent circuit of Fig. 11.17c. In this condition, the behavior of the inductor current is described by vs  − vo diL vL = = dt L L
(11.27)
If vo > vs , which is an important condition for the correct behavior of the rectiﬁer, then vs −vo < 0, and this means that in the offstate the inductor current decreases its instantaneous value. 11.3.3.2 Continuous Conduction Mode (CCM) With an appropriate ﬁring pulse sequence is applied to transistor T, the waveform of the input current is can be controlled to follow a sinusoidal reference, as can be observed in the positive halfwave of is in Fig. 11.18. This ﬁgure shows the reference
D
is + vs
vs
vL
(a)
vL
iL
iL
L
L vs
vo
C
x
C
(b)
vo
Load
vs
C
vo
Load
(c)
FIGURE 11.17 Singlephase boost rectiﬁer: (a) power circuit and equivalent circuit for transistor T in; (b) onstate; and (c) offstate.
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J. Rodríguez et al.
iL iLref Current distortion 0 (a)
x 1
0 (b)
FIGURE 11.18 Behavior of the inductor current iL : (a) waveforms and (b) transistor T gate drive signal x.
inductor current iLref , the inductor current iL and the gate drive signal x for transistor T. Transistor T is on when x = 1 and it is off when x = 0. Figure 11.18 clearly shows that the on (off) state of transistor T produces an increase (decrease) in the inductor current iL . Note that for low values of vs the inductor does not have enough energy to increase the current value, for this reason it presents a distortion in their current waveform as shown in Fig. 11.18a. Figure 11.19 presents a block diagram of the control system for the boost rectiﬁer, which includes a proportionalintegral (PI) controller, to regulate the output voltage vo . The reference value iLref for the inner current control loop is obtained from the multiplication between the output of the voltage controller and the absolute value vs (t ). A hysteresis controller provides a fast control for the inductor current iL , resulting in a practically sinusoidal input current is . Typically, the output voltage vo should be at least 10% higher than the peak value of the source voltage vs (t), in order to assure good dynamic control of the current. The control works with the following strategy: a step increase in the reference voltage voref will produce an increase in the voltage error voref − vo and an increase of the output of the PI controller, which originates an increase in the amplitude of the reference
current iLref . The current controller will follow this new reference and will increase the amplitude of the sinusoidal input current is , which will increase the active power delivered by the singlephase power supply, producing ﬁnally an increase in the output voltage vo . Figure 11.20a shows the waveform of the input current is and the source voltage vs . The ripple of the input current can be reduced by shortening the hysteresis width δ. The tradeoff for this improvement is an increase in the switching frequency, which is proportional to the commutation losses of the transistors. For a given hysteresis width δ, a reduction of inductance L also produces an increase in the switching frequency. As can be seen, the input current presents a thirdharmonic component. This harmonic is generated by the secondharmonic component present in vo , which is fed back through the voltage (PI) controller and multiplied by the sinusoidal waveform, generating a thirdharmonic component on iLref . This harmonic contamination can be avoided by ﬁltering the vo measurement with a lowpass ﬁlter or a bandstop ﬁlter around 2ωs . The input current obtained using the measurement ﬁlter is shown in Fig. 11.20b. Figure 11.20d conﬁrms the reduction of the thirdharmonic component. However, in both cases, a drastic reduction in the harmonic content of the input current is can be observed in the frequency spectrum of Figs. 11.20c and 11.20d. This current fulﬁlls the restrictions established by standard IEC 6100032. The total harmonic distortion of the current in Fig. 11.20a is THD = 7.46%, while the THD of the current of Fig. 11.20b is 4.83%, in both cases a very high power factor, over 0.99, is reached. Figure 11.21 shows the dc voltage control loop dynamic behavior for step changes in the load. An increase in the load, at t = 0.3 [s], produces an initial reduction of the output voltage vo , which is compensated by an increase in the input current is . At t = 0.6 [s] a step decrease in the load is applied. The dc voltage controller again adjusts the supply current in order to balance the active power. 11.3.3.3 Discontinuous Conduction Mode (DCM) This PFC method is based on an active current waveformshaping principle. There are two different approaches considering ﬁxed and variable switching frequency, both operating principles are illustrated in Fig. 11.22.
iLref
voref +
d
+ PI vo vs
t
iL
FIGURE 11.19 Control system of the boost rectiﬁer.
x
11
191
Singlephase Controlled Rectiﬁers
Without Filter
With Filter
vs
vs
is
is
(b) 100
100
% of Fundamental
% of Fundamental
(a) 80 60 40 20 0
t
0 50
250
150
350
80 60 40 20 0
450
0 50
150
Frequency [Hz]
250
350
450
Frequency [Hz]
(c)
(d)
DClink Voltage vo [V]
FIGURE 11.20 Input current and voltage of the singlephase boost rectiﬁer: (a) without a ﬁlter on vo measurement; (b) with a ﬁlter on vo measurement; frequency spectrum; (c) without ﬁlter; and (d) with ﬁlter.
500 450 400 350 300 250 200 150 100 50 0
voref vo
Input Current is [A]
(a) vs
60 40 20 0
is
20 40 60 0.3
0.35
0.4
0.45 (b)
0.5
0.55
0.6 Time [s]
FIGURE 11.21 Response to a change in the load: (a) outputvoltage vo and (b) input current is .
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J. Rodríguez et al. Ts
S ton
~ Ts
S
toff
ton
toff
t is
t is
iL
iL, iD
iL, iD
iL
t Mode 1
Mode 2
t
Mode 3
Mode 1
(a)
Mode 2 (b)
FIGURE 11.22 Boost DCM operating principle: (a) with ﬁxed switching frequency and (b) with variable switching frequency.
a) DCM with Fixed Switching Frequency The current shaping strategy is achieved by combining three different conduction modes, performed over a ﬁxed switching period Ts . At the beginning of each period the power semiconductor is turned on. During the onstate, shown in Fig. 11.23a, the power supply is shortcircuited through the rectiﬁer diodes, the inductor L, and the boost switch T. Hence, the inductor current iL increases at a rate proportional to the instantaneous value of the supply voltage. As a result, during the onstate, the average supply current is is proportional to the supply voltage vs which yields to power factor correction. When the switch is turned off, the current ﬂows to the load trough diode D, as shown in Fig. 11.23b. The instantaneous current value decreases (since the load voltage vo is higher than the supply peak voltage) at a rate proportional to the difference between the supply and load voltage. Finally, the last mode, illustrated in Fig. 11.23c, corresponds to the time in which the current reaches zero value, completing the switching period Ts . Therefore, the supply current is not proportional to the voltage source during the whole control period, introducing distortion and undesirable EMI in comparison to CCM. The duty cycle D = ton /T s is determined by the control loop, in order to obtain the desired output power and to ensure operation in DCM, i.e. to reach zero current before the new switching cycle starts. The control strategy can be implemented with analog circuitry as shown in Fig. 11.24, or digitally with modern computing devices. Generally, the duty cycle is controlled with a slow control loop, maintaining the output voltage and duty cycle constant over a halfsource cycle. A qualitative example of the supply voltage and current obtained using DCM is illustrated in Fig. 11.25. b) DCM with Variable Switching Frequency The operating principle is similar to the one used in the previous case, the main difference is that mode 3 is avoided by switching the transistor again to the onstate, immediately after the inductor current reaches zero value. This reduces
iL
iD=0
D
L
is + vs
EMI Filter
T
iL
(a) L
Load
C
iD
D
is + vs
EMI Filter
T
Load
C
(b) iL=0
iD=0
D
L
is vs
+
EMI Filter
T
C
Load
(c)
FIGURE 11.23 Boost DCM equivalent circuits: (a) mode 1: transistor on, inductor current increasing; (b) mode 2: transistor off, inductor current decreasing; and (c) mode 3: transistor off, inductor current reaches zero.
the current distortion, with the tradeoff of introducing variable switching frequency (Ts is variable) and consequently lowerorder harmonic content. Both CCM and DCM achieve an improvement in the power factor. The DCM is more efﬁcient since reverserecovery losses
11
193
Singlephase Controlled Rectiﬁers iL
iD
D
L
is + vs
EMI Filter
T
C
vo
Ts _ S
Z2
Ramp
+
OP R1 R2
R3
Z1
_ +
R4 + _ vo*
R1
FIGURE 11.24 Boost DCM control circuit with ﬁxed switching frequency.
vs
OFF
t
Voltage CE
ON
OFF
Current
S t is
Conduction losses t Ts
Switching losses
FIGURE 11.25 Boost DCM waveforms: supply voltage, transistor control signal, and supply current.
FIGURE 11.26 Conduction and switching losses on a power switch.
of the boost diode are eliminated, however this mode introduces highcurrent ripple and considerable distortion and usually an important ﬁfthorder harmonic is obtained. Therefore boostDCM applications are limited to 300 W power levels, to meet standards and regulations. The DCM with variable switching frequency reduces this harmonic content, at expends of a wide distributed current spectrum and all related design problems.
However, the switching losses, which are produced while the power semiconductors work in linear state during the transition from on to off state or from off to onstate, can be reduced or even eliminated, if the switch (transition) occurs when: (a) the current across the power semiconductor is zero; (b) the voltage between the power terminals of the power semiconductor is zero. This operation mode is used in the socalled resonant or softswitched converters, which are discussed in detail in a different chapter of this handbook. Resonant operation can also be used with the boost converter topology. In order to produce this condition, topology of Fig. 11.17 needs to be modiﬁed, by including reactive components and additional semiconductors. In Fig. 11.27 a resonant structure for zero current switching (ZCS) [2] is shown. As can be seen, additional resonant inductors (Lr1 , Lr2 ), capacitors (Cr ), diodes (Dr1 , Dr2 ), and power switch (Sr ) have been included.
11.3.3.4 Resonant Structures for the Boost Rectiﬁers An important issue in power electronics is the power losses in power semiconductors. These losses can be classiﬁed in two groups: conduction losses and switching losses, as shown in Fig. 11.26. The conduction losses are produced by the current through the semiconductor juncture, so these losses are unavoidable.
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Lr1 vs
11.3.3.5 Bridgless Boost Rectiﬁer The bridgless boost rectiﬁer [7] is shown in Fig. 11.29a. This rectiﬁer replaces the input diode rectiﬁer by a combination of two boost rectiﬁers which work alternately: (a) when vs is positive, T1 and D1 operate as boost rectiﬁer 1 (Fig. 11.29b); (b) when vs is negative, T2 and D2 operate as boost rectiﬁer 2 (Fig. 11.29c); This topology reduces the conduction losses of the rectiﬁer [8, 9], but requires a slightly more complex control scheme, also EMI and EMC aspects must be considered.
D
L
Dr1 C
Cr
S
Lr2
R
Dr2
Sr
Resonant Components
FIGURE 11.27 Boost rectiﬁer with ZCS.
L
Lr
11.3.4 Voltage Doubler PWM Rectiﬁer
Dr1
Figure 11.30a shows the power circuit of the voltage doubler pulse width modulated (PWM) rectiﬁer, which uses two transistors T1 and T2 and two ﬁlter capacitors C1 and C2 . The transistors are switched complementary to control the waveform of the input current is and the output dc voltage vo . Capacitor voltages VC1 and VC2 must be higher than the peak value of the input voltage vs to ensure the control of the input current. The equivalent circuit of this rectiﬁer with transistor T1 in the onstate is shown in Fig. 11.30b. For this case, the inductor voltage dynamic equation is
Sr Dr2
Cr
vs
C R S
Resonant Components
FIGURE 11.28 Boost rectiﬁer with ZVS.
In a similar way, in Fig. 11.28 a resonant structure for zero voltage switching (ZVS) [3] is shown. Once again, additional inductance (Lr ), capacitor (Cr ), and power switch (Sr ) are added, note however, that diode D has been replaced by two “resonant diodes,” Dr1 and Dr2 . In both cases, the ZVS or ZCS condition is reached through a proper control of Sr . Other resonant topologies are described in the literature [4–6] with similar behavior.
D2
vs
vL = L
D1
L
R
C
vo
T1 (a)
vs
D1
L is
C
D2 R
vo
vs
L is
C
R
vo
T2
T1 (b)
(11.28)
Equation (11.28) means that under this conduction state, current is (t) decreases its value.
is T2
dis = vs (t ) − VC1 < 0 dt
(c)
FIGURE 11.29 (a) Power circuit of bridgless boost rectiﬁer; equivalent circuit when; (b) vs >0; and (c) vs 0 dt
(11.29)
hence, for this condition, the input current is (t) increases. Therefore the waveform of the input current can be controlled by switching appropriately transistors T1 and T2 in a similar way as shown in Fig. 11.18a for the singlephase boost converter. Figure 11.31 shows a block diagram of the control system for the voltage doubler rectiﬁer, which is very similar to the control scheme of the boost rectiﬁer. This topology can present an unbalance in the capacitor voltages VC1 and VC2 , which will affect the quality of the control. This problem is solved by adding to the actual current value is an offset signal proportional to the capacitor’s voltage difference. Figure 11.32 shows the waveform of the input current. The ripple amplitude of this current can be reduced by decreasing the hysteresis width of the controller.
Figure 11.33a shows the power circuit of the fully controlled singlephase PWM rectiﬁer in bridge connection, which uses four transistors with antiparallel diodes to produce a controlled dc voltage vo . Using a bipolar PWM switching strategy, this converter may have two conduction states: (i) Transistors T1 and T4 in the onstate and T2 and T3 in the offstate; (ii) Transistors T2 and T3 in the onstate and T1 and T4 in the offstate. In this topology, the output voltage vo must be higher than the peak value of the ac source voltage vs , to ensure a proper control of the input current. Figure 11.33b shows the equivalent circuit with transistors T1 and T4 on. In this case, the inductor voltage is given by vL = L
dis = vs (t ) − V0 < 0 dt
Therefore, in this condition a reduction of the inductor current is is produced. Figure 11.33c shows the equivalent circuit with transistors T2 and T3 on. Here, the inductor voltage has the following expression vL = L
dis = vs (t ) + V0 > 0 dt
+
+
_
vs
PI
vo 0
+_
Unbalance Control
(11.31)
which means an increase in the instantaneous value of the input current is .
isref
voref
(11.30)
d
_
T1 T2
+
+
is
Vc1_Vc2
FIGURE 11.31 Control system of the voltage doubler rectiﬁer.
196
J. Rodríguez et al. P T3
T1 is
L +
vs
vL T2
L
is
P
vL vs
(b) vs , is
vo
C
Load
T4
N
(a) is
vo
C
vs
L +
vL vo
C
N
(c) vs
is
N
P
vs
L +
P
vL vo
C
(d)
N
is
t
(e)
FIGURE 11.33 Singlephase PWM rectiﬁer in bridge connection: (a) power circuit; (b) equivalent circuit with T1 and T4 on; (c) equivalent circuit with T2 and T3 on; (d) equivalent circuit with T1 and T3 or T2 and T4 on; and (e) waveform of the input current during regeneration.
Finally, Fig. 11.33d shows the equivalent circuit with transistors T1 and T3 or T2 and T4 are in the onstate. In this case, the input voltage source is shortcircuited through inductor L, which yields vL = L
dis = vs (t ) + V0 > 0 dt
(11.32)
Equation (11.32) implies that the current value will depend on the sign of vs . The waveform of the input current is can be controlled by appropriately switching transistors T1 –T4 or T2 –T3 , originating a similar shape to the one shown in Fig. 11.18a for the singlephase boost rectiﬁer. The control strategy for the rectiﬁer is similar to the one illustrated in Fig. 11.31, for the voltage doubler topology. The quality of the input current obtained with this rectiﬁer is the same as presented in Fig. 11.32 for the voltage doubler conﬁguration. The input current waveform can be slightly improved if the state of Fig. 11.33d is used. This can be done by replacing the hysteresis current control with a more complex linear control plus a threelevel PWM modulator. This method reduces
the semiconductor switching frequency and provides a more deﬁned current spectrum. Finally, it must be said that one of the most attractive characteristics of the fully controlled PWM converter in bridge connection and the voltage doubler is their regeneration capability. In effect, these rectiﬁers can deliver power from the load to the singlephase supply, operating with sinusoidal current and a high power factor of PF > 0.99. Figure 11.33e shows that during regeneration, the input current is is 180◦ out of phase with respect to the supply voltage vs , which means operation with power factor PF ≈ −1 (PF is approximately 1 because of the small harmonic content in the input current).
11.3.6 Applications of Unity Power Factor Rectiﬁers 11.3.6.1 Boost Rectiﬁer Applications The singlephase boost rectiﬁer has become the most popular topology for power factor correction (PFC) in general purpose power supplies. To reduce the costs, the complete control system shown in Fig. 11.19 and the gate drive circuit of the power transistor have been included in a single integrated circuit (IC), like the UC3854 [10] or MC33262, shown in Fig. 11.34.
11
197
Singlephase Controlled Rectiﬁers
D
L
Q C
AC LINE
LOAD
RS
CURRENT SENSE
UC 3854 or MC33262
WAVEFORM INPUT
VOLTAGE SENSE
FIGURE 11.34 Simpliﬁed circuit of a power factor corrector with control integrated circuit.
Rectifier
EMI FILTER
Line
Output Stage
PFC
Lamp
+
Dimming Control
FIGURE 11.35 Functional block diagram of electronic ballast with power factor correction.
11.3.6.2 Voltage Doubler PWM Rectiﬁer The development of lowcost compact motor drive systems is a very relevant topic, particularly in the lowpower range. Figure 11.36 shows a lowcost converter for lowpower induction motor drives. In this conﬁguration, a threephase induction motor is fed through the converter from a singlephase power supply. Transistors T1 , T2 and capacitors C1 , C2
Today there is increased interest in developing highfrequency electronic ballasts to replace the classical electromagnetic ballast present in ﬂuorescent lamps. These electronic ballasts require an ac–dc converter. To satisfy the harmonic current injection from electronic equipment and to maintain a high power quality, a high power factor rectiﬁer can be used, as shown in Fig. 11.35 [11].
T1
T3 C1
AC MAINS
T5
+ _
+ M 0 T2
T4 C2
T6
+ _
FIGURE 11.36 Lowcost induction motor drive.
198
J. Rodríguez et al.
constitute the voltage doubler singlephase rectiﬁer, which controls the dc link voltage and generates sinusoidal input current, working with closetounity power factor [12]. On the other hand, transistors T3 , T4 , T5 , and T6 and capacitors C1 and C2 constitute the power circuit of an asymmetric inverter that supplies the motor. An important characteristic of the power circuit shown in Fig. 11.36 is the capability of regenerating power to the singlephase mains.
11.3.6.3 PWM Rectiﬁer in Bridge Connection Distortion of the input current in the linecommutated rectiﬁers with capacitive ﬁltering is particularly critical in the UPS fed from motorgenerator sets. In effect, due to the higher value of the generator impedance, the current distortion can originate an unacceptable distortion on the ac voltage, which affects the behavior of the whole system. For this reason, it is very attractive to use rectiﬁers with low distortion in the input current. Figure 11.37 shows the power circuit of a singlephase UPS, which has a PWM rectiﬁer in bridge connection at the input
side. This rectiﬁer generates a sinusoidal input current and controls the charge of the battery [13]. Perhaps the most typical and widely accepted area of application of high power factor singlephase rectiﬁers is in locomotive drives [14]. An essential prerequisite for proper operation of voltage source threephase inverter drives in modern locomotives is the use of fourquadrant lineside converters, which ensure motoring and braking of the drive, with reduced harmonics in the input current. Figure 11.38 shows a simpliﬁed power circuit of a typical drive for a locomotive connected to a singlephase power supply [14], which includes a high power factor rectiﬁer at the input. Finally, Fig. 11.39 shows the main circuit diagram of the 300 series Shinkansen train [15]. In this application, ac power from the overhead catenary is transmitted through a transformer to singlephase PWM rectiﬁers, which provide the dc voltage for the inverters. The rectiﬁers are capable of controlling the input ac current in an approximate sine waveform and in phase with the voltage, achieving power factor close to unity on powering and on regenerative braking. Regenerative braking produces energy savings and an important operational ﬂexibility.
THY SW THY1 THY2 Output 1f100 V Input 1f100 V
TR1 Inverter
Converter
FIGURE 11.37 Singlephase UPS with PWM rectiﬁer.
Idc
is
Vdc
vs
Line + transformer
4quadrant converter
3
DC  Link
Inverter
Motor
FIGURE 11.38 Typical power circuit of an ac drive for locomotive.
11
199
Singlephase Controlled Rectiﬁers OVERHEAD CATENARY
PWM CONVERTER
SMOOTHING CAPACITOR
INDUCTION MOTORS
TRANSFORMER
PWM INVERTER
GTO THYRISTOR
FIGURE 11.39 Main circuit diagram of 300 series Shinkansen locomotives.
Acknowledgment The authors gratefully acknowledge the valuable contribution of Dr. Rubén Peña, and support provided by the Millennium Science Initiative (ICM) from Mideplan, Chile.
References 1. R. Dwyer and D. Mueller, “Selection of transformers for comercial buildings,” in Proc. of IEEE/IAS 1992 Annual Meeting, U.S.A., Oct 1992, pp. 1335–1342. 2. D. C. Martins, F. J. M. de Seixas, J. A. Brilhante, and I. Barbi, “A family of dctodc PWM converters using a new ZVS commutation cell,” in Proc. IEEE PESC’93, 1993, pp. 524–530.
3. J. Bassett, “New, zero voltage switching, high frequency boost converter topology for power factor correction,” in Proc. INTELEC’95, 1995, pp. 813–820. 4. R. Streit and D. Tollik, “High efﬁciency telecom rectiﬁer using a novel softswitched boostbased input current shaper,” in Proc. INTELEC’91, 1991, pp. 720–726. 5. Y. Jang and M. M. Jovanovic´, “A new, softswitched, highpowerfactor boost converter with IGBTs,” presented at the INTELEC’99, 1999, Paper 83. 6. M. M. Jovanovic´, “A technique for reducing rectiﬁer reverserecoveryrelated losses in highvoltage, highpower boost converters,” in Proc. IEEE APEC’97, 1997, pp. 1000–1007. 7. D. M. Mitchell, “ACDC converter having an improved power factor,” U.S. Patent 4 412 277, Oct 25, 1983.
200 8. A. F. de Souza and I. Barbi, “A new ZVSPWM unity power factor rectiﬁer with reduced conduction losses,” IEEE Trans. Power Electron, Vol. 10, No. 6, Nov 1995, pp. 746–752. 9. A. F. de Souza and I. Barbi, “A new ZVS semiresonant power factor rectiﬁer with reduced conduction losses,” IEEE Trans. Ind. Electron, Vol. 46, No. 1, Feb 1999, pp. 82–90. 10. P. Todd, “UC3854 controlled power factor correction circuit design,” Application Note U134, Unitrode Corp. 11. J. Adams, T. Ribarich, and J. Ribarich, “A new control IC for dimmable highfrequency electronic ballast,” IEEE Applied Power Electronics Conference APEC’99, USA,1999, pp. 713–719. 12. C. Jacobina, M. Beltrao, E. Cabral, and A. Nogueira, “Induction motor drive system for lowpower applications,” IEEE
J. Rodríguez et al. Transactions on Industry Applications, Vol. 35, No. 1. Jan/Feb 1999, pp. 52–60. 13. K. Hirachi, H. Yamamoto, T. Matsui, S. Watanabe, and M. Nakaoka, “Costeffective practical developments of highperformance 1kVA UPS with new system conﬁgurations and their speciﬁc control implementations,” European Conference on Power Electronics EPE 95, Spain 1995, pp. 2035–2040. 14. K. Hückelheim and Ch. Mangold, “Novel 4quadrant converter control method,” European Conference on Power Electronics EPE 89, Germany 1989, pp. 573–576. 15. T. Ohmae and K. Nakamura, “Hitachi’s role in the area of power electronics for transportation,” Proc. of the IECON’93. Hawai, Nov 1993, pp. 714–718.
12 Threephase Controlled Rectiﬁers Juan W. Dixon, Ph.D. Department of Electrical Engineering, Pontiﬁcia Universidad Católica de Chile Vicuña Mackenna 4860, Santiago, Chile
12.1 Introduction .......................................................................................... 201 12.2 Linecommutated Controlled Rectiﬁers....................................................... 201 12.2.1 Threephase Halfwave Rectiﬁer • 12.2.2 Sixpulse or Double Star Rectiﬁer • 12.2.3 Double Star Rectiﬁer with Interphase Connection • 12.2.4 Threephase Fullwave Rectiﬁer or Graetz Bridge • 12.2.5 Half Controlled Bridge Converter • 12.2.6 Commutation • 12.2.7 Power Factor • 12.2.8 Harmonic Distortion • 12.2.9 Special Conﬁgurations for Harmonic Reduction • 12.2.10 Applications of Linecommutated Rectiﬁers in Machine Drives • 12.2.11 Applications in HVDC Power Transmission • 12.2.12 Dual Converters • 12.2.13 Cycloconverters • 12.2.14 Harmonic Standards and Recommended Practices
12.3 Forcecommutated Threephase Controlled Rectiﬁers ................................... 221 12.3.1 Basic Topologies and Characteristics • 12.3.2 Operation of the Voltage Source Rectiﬁer • 12.3.3 PWM Phasetophase and Phasetoneutral Voltages • 12.3.4 Control of the DC Link Voltage • 12.3.5 New Technologies and Applications of Forcecommutated Rectiﬁers
Further Reading ..................................................................................... 242
12.1 Introduction Threephase controlled rectiﬁers have a wide range of applications, from small rectiﬁers to large high voltage direct current (HVDC) transmission systems. They are used for electrochemical processes, many kinds of motor drives, traction equipment, controlled power supplies and many other applications. From the point of view of the commutation process, they can be classiﬁed into two important categories: linecommutated controlled rectiﬁers (thyristor rectiﬁers) and forcecommutated pulse width modulated (PWM) rectiﬁers.
12.2 Linecommutated Controlled Rectiﬁers 12.2.1 Threephase Halfwave Rectiﬁer Figure 12.1 shows the threephase halfwave rectiﬁer topology. To control the load voltage, the halfwave rectiﬁer uses three commoncathode thyristor arrangement. In this ﬁgure, the power supply and the transformer are assumed ideal. The thyristor will conduct (ON state), when the anodetocathode voltage vAK is positive and a ﬁring current pulse iG is applied to the gate terminal. Delaying the ﬁring pulse by an angle α controls the load voltage. As shown in Fig. 12.2, the ﬁring angle α Copyright © 2007, 2001, Elsevier Inc. All rights reserved.
is measured from the crossing point between the phase supply voltages. At that point, the anodetocathode thyristor voltage vAK begins to be positive. Figure 12.3 shows that the possible range for gating delay is between α = 0◦ and α = 180◦ , but because of commutation problems in actual situations, the maximum ﬁring angle is limited to around 160◦ . As shown in Fig. 12.4, when the load is resistive, current id has the same waveform of the load voltage. As the load becomes more and more inductive, the current ﬂattens and ﬁnally becomes constant. The thyristor goes to the nonconducting condition (OFF state) when the following thyristor is switched ON, or the current, tries to reach a negative value. With the help of Fig. 12.2, the load average voltage can be evaluated, and is given by: VMAX VD = 2 3π = VMAX
π/3+α
cos ωt · d (ωt ) −π/3+α
sin π3 π 3
· cos α ≈ 1.17 · Vfrms −N · cos α
(12.1)
where VMAX is the secondary phasetoneutral peak voltage, Vrms f −N its root mean square (rms) value and ω is the angular frequency of the main power supply. It can be seen from Eq. (12.1) that the load average voltage VD is modiﬁed by 201
202
J. W. Dixon vA
iA
vB
iB
vC
iC
ia
va
ib
iD
vb
ic
+
LD
vc
Y
LOAD
VD
vD
Y
_
FIGURE 12.1 Threephase halfwave rectiﬁer.
α
vD
A1=A2 A2
A1 VD
−π/3
π/3
va
vb
VMAX
ωt
vc
FIGURE 12.2 Instantaneous dc voltage vD , average dc voltage VD , and ﬁring angle α.
range of α
0° va
ωt
180° vb
vc
FIGURE 12.3 Possible range for gating delay in angle α.
changing ﬁring angle α. When α < 90◦ , VD is positive and when α > 90◦ , the average dc voltage becomes negative. In such a case, the rectiﬁer begins to work as an inverter and the load needs to be able to generate power reversal by reversing its dc voltage. The ac currents of the halfwave rectiﬁer are shown in Fig. 12.5. This drawing assumes that the dc current is constant (very large LD ). Disregarding commutation overlap, each valve conducts during 120◦ per period. The secondary currents (and thyristor currents) present a dc component that is undesirable, and makes this rectiﬁer not useful for high power applications.
The primary currents show the same waveform, but with the dc component removed. This very distorted waveform requires an input ﬁlter to reduce harmonics contamination. The current waveforms shown in Fig. 12.5 are useful for designing the power transformer. Starting from: rms rms VAprim = 3 · V(prim)f −N · Iprim rms rms VAsec = 3 · V(sec)f −N · Isec
PD = VD · ID
(12.2)
12
203
Threephase Controlled Rectiﬁers vD
iD
(a) R > 0, LD =0
vD
iD
vD
iD
(c) R > 0, LD large
vD
iD
(d) R small, LD very large
(b) R > 0, LD >0
FIGURE 12.4 DC current waveforms.
where VAprim and VAsec are the ratings of the transformer for the primary and secondary side respectively. Here PD is the power transferred to the dc side. The maximum power transfer is with α = 0◦ (or α = 180◦ ). Then, to establish a relation between ac and dc voltages, Eq. (12.1) for α = 0◦ is required: rms VD = 1.17 · V(sec)f −N
(12.3)
and: rms VD = 1.17 · a · V(prim)f −N
(12.4)
where a is the secondary to primary turn relation of the transformer. On the other hand, a relation between the currents is also possible to obtain. With the help of Fig. 12.5: ID rms Isec =√ 3
(12.5)
rms Iprim
√ ID 2 =a· 3
(12.6)
Combining Eqs. (12.2) to (12.6), it yields: VAprim = 1.21 · PD VAsec = 1.48 · PD
(12.7)
Equation (12.7) shows that the power transformer has to be oversized 21% at the primary side, and 48% at the secondary side. Then, a special transformer has to be built for this rectiﬁer. In terms of average VA, the transformer needs to be 35% larger that the rating of the dc load. The larger rating of the secondary with respect to primary is because the secondary carries a dc component inside the windings. Furthermore, the transformer is oversized because the circulation of current harmonics does not generate active power. Core saturation, due to
204
J. W. Dixon
α
vD
VMAX
ID
ωt vc
vb
va
vb
va
ID
ia ib ic
2ID / 3
iA –ID / 3
iB
iC
FIGURE 12.5 AC current waveforms for the halfwave rectiﬁer.
iA∆ vA
iA
vB
iB
vC
ia ib ic
iC
i1
v1
i2
v2
i3
v3
ID
va
LD +
vb
VD
vc
vD
N
_
FIGURE 12.6 Sixpulse rectiﬁer.
the dc components inside the secondary windings, also needs to be taken in account for iron oversizing.
and its average value is given by:
VD =
12.2.2 Sixpulse or Double Star Rectiﬁer The thyristor side windings of the transformer shown in Fig. 12.6 form a sixphase system, resulting in a sixpulse starpoint (midpoint connection). Disregarding commutation overlap, each valve conducts only during 60◦ per period. The direct voltage is higher than that from the halfwave rectiﬁer
VMAX π 3
= VMAX
π/6+α
cos ωt · d (ωt ) −π/6+α
sin π6 π 6
· cos α ≈ 1.35 · Vfrms −N · cos α
(12.8)
The dc voltage ripple is also smaller than the one generated by the halfwave rectiﬁer, due to the absence of the third harmonic with its inherently high amplitude. The smoothing
12
205
Threephase Controlled Rectiﬁers vD
α
VD
ID
wt va
v3
vb
v1
vc
v2
va
v3
ia ib ic 60°
i1 iA∆ iB∆
iA
FIGURE 12.7 AC current waveforms for the sixpulse rectiﬁer.
reactor LD is also considerably smaller than the one needed for a threepulse (halfwave) rectiﬁer. The ac currents of the sixpulse rectiﬁer are shown in Fig. 12.7. The currents in the secondary windings present a dc component, but the magnetic ﬂux is compensated by the double star. As can be observed, only one valve is ﬁred at a time and then this connection in no way corresponds to a parallel connection. The currents inside the delta show a symmetrical waveform with 60◦ conduction. Finally, due to the particular transformer connection shown in Fig. 12.6, the source currents also show a symmetrical waveform, but with 120◦ conduction. Evaluation of the the rating of the transformer is done in similar fashion to the way the halfwave rectiﬁer is evaluated: VAprim = 1.28 · PD VAsec = 1.81 · PD
(12.9)
Thus the transformer must be oversized 28% at the primary side and 81% at the secondary side. In terms of size it has an average apparent power of 1.55 times the power PD (55% oversized). Because of the short conducting period of the valves, the transformer is not particularly well utilized.
12.2.3 Double Star Rectiﬁer with Interphase Connection This topology works as two halfwave rectiﬁers in parallel, and is very useful when high dc current is required. An optimal
way to reach both good balance and elimination of harmonics is through the connection shown in Fig. 12.8. The two rectiﬁers are shifted by 180◦ , and their secondary neutrals are connected through a middlepoint autotransformer called “interphase transformer.” The interphase transformer is connected between the two secondary neutrals and the middle point at the load return. In this way, both groups operate in parallel. Half the direct current ﬂows in each half of the interphase transformer, and then its iron core does not become saturated. The potential of each neutral can oscillate independently, generating an almost triangular voltage waveform (vT ) in the interphase transformer, as shown in Fig. 12.9. As this converter work like two halfwave rectiﬁers connected in parallel, the load average voltage is the same as in Eq. (12.1): VD ≈ 1.17 · Vfrms −N · cos α
(12.10)
where Vrms f −N is the phasetoneutral rms voltage at the valve side of the transformer (secondary). The Fig. 12.9 also shows the two halfwave rectiﬁer voltages, related to their respective neutrals. Voltage vD1 represents the potential between the common cathode connection and the neutral N1. The voltage vD2 is between the common cathode connection and N2. It can be seen that the two instantaneous voltages are shifted, which gives as a result, a voltage vD that is smoother than vD1 and vD2 . Figure 12.10 shows how vD , vD1 , vD2 , and vT change when the ﬁring angle changes from α = 0◦ to 180◦ .
206
J. W. Dixon vD2 vD1
vT
vA
iA
iAD
i1
v1
i2
v2
i3
v3
ia
vB
iB
ib
vC
iC
ic ½ID
½ID
ID
va
LD
vb
+
vc
VD vD
_
N1
N2
FIGURE 12.8 Double star rectiﬁer with interphase transformer.
va ia wt
vD
vD1
vD2
vT
VD
FIGURE 12.9 Operation of the interphase connection for α = 0◦ .
The transformer rating in this case is: VAprim = 1.05 · PD VAsec = 1.48 · PD
(12.11)
And the average rating power will be 1.26 PD , which is better than the previous rectiﬁers (1.35 for the halfwave rectiﬁer and 1.55 for the sixpulse rectiﬁer). Thus the transformer is well utilized. Figure 12.11 shows ac current waveforms for a rectiﬁer with interphase transformer.
12.2.4 Threephase Fullwave Rectiﬁer or Graetz Bridge Parallel connection via interphase transformers permits the implementation of rectiﬁers for high current applications. Series connection for high voltage is also possible, as shown in the fullwave rectiﬁer of Fig. 12.12. With this arrangement, it can be seen that the three common cathode valves generate a positive voltage with respect to the neutral, and the three
common anode valves produce a negative voltage. The result is a dc voltage, twice the value of the halfwave rectiﬁer. Each half of the bridge is a threepulse converter group. This bridge connection is a twoway connection and alternating currents ﬂow in the valveside transformer windings during both half periods, avoiding dc components into the windings, and saturation in the transformer magnetic core. These characteristics make the socalled Graetz bridge the most widely used linecommutated thyristor rectiﬁer. The conﬁguration does not need any special transformer and works as a sixpulse rectiﬁer. The series characteristic of this rectiﬁer produces a dc voltage twice the value of the halfwave rectiﬁer. The load average voltage is given by: 2 · VMAX VD = 2 3π = 2 · VMAX
π/3+α
cos ωt · d (ωt ) −π/3+α
sin π3 π 3
· cos α ≈ 2.34 · Vfrms −N · cos α (12.12)
12
207
Threephase Controlled Rectiﬁers va, ia
α=0°
α=180°
vD
vD1, vD2
vT
FIGURE 12.10 Firing angle variation from α = 0◦ to 180◦ . vD
a
VMAX
ID
wt va
v3
ia
vb
v1
vc
v2
va
v3
vb
ID /2
ib ic i1 i2 i3 iAD iBD iA
FIGURE 12.11 AC current waveforms for the rectiﬁer with interphase transformer.
or VD =
3·
√
2 · Vfsec −f π
cos α ≈ 1.35 · Vfsec −f · cos α
(12.13)
where VMAX is the peak phasetoneutral voltage at the secondary transformer terminals, Vrms f −N its rms value,
and Vsec f −f the rms phasetophase secondary voltage, at the valve terminals of the rectiﬁer. Figure 12.13 shows the voltages of each halfwave bridge of neg pos this topology, v D and vD , the total instantaneous dc voltage vD , and the anodetocathode voltage vAK in√one of the bridge thyristors. The maximum value of vAK is 3 · VMAX ,
208
J. W. Dixon ID vDpos
∆
iA
ia
vA
iA
vB
iB
ib
vC
iC
ic
_ va +
LD
vAK
Vffsec
vD
VD
vb vc vDneg
FIGURE 12.12 Threephase fullwave rectiﬁer or Graetz bridge.
vc
a
va
vb
vc
vDpos
va VMAX
ID vDneg
vD A2 A1
VD
A1 = A2
vAK wt
FIGURE 12.13 Voltage waveforms for the Graetz bridge.
which is the same as that of the halfwave converter and the interphase transformer rectiﬁer. The double star rectiﬁer presents a maximum anodetocathode voltage of two times VMAX . Figure 12.14 shows the currents of the rectiﬁer, which assumes that LD is large enough to keep the dc current smooth. The example is for the same Y transformer connection shown in the topology of Fig. 12.12. It can be noted that the secondary currents do not carry any dc component, thereby avoiding overdesign of the windings and transformer saturation. These two ﬁgures have been drawn for a ﬁring angle, α of approximately 30◦ . The perfect symmetry of the currents in all windings and lines is one of the reasons why this rectiﬁer is the most popular of its type. The transformer rating in this case is VAprim = 1.05 · PD VAsec = 1.05 · PD
(12.14)
As can be noted, the transformer needs to be oversized only 5%, and both primary and secondary windings have the same rating. Again, this value can be compared with the previous rectiﬁer transformers: 1.35PD for the halfwave rectiﬁer, 1.55PD for the sixpulse rectiﬁer, and 1.26PD for the interphase transformer rectiﬁer. The Graetz bridge makes excellent use of the power transformer.
12.2.5 Half Controlled Bridge Converter The fully controlled threephase bridge converter shown in Fig. 12.12 has six thyristors. As already explained here, this circuit operates as a rectiﬁer when each thyristor has a ﬁring angle α < 90◦ and functions as an inverter for α > 90◦ . If inverter operation is not required, the circuit may be simpliﬁed by replacing three controlled rectiﬁers with power diodes, as in Fig. 12.15a. This simpliﬁcation is economically attractive
12
209
Threephase Controlled Rectiﬁers
a
vc
vc
vb
va
vDpos
va VMAX
ID
(a) wt
va
ia1
vDneg
(b)
ia
iAD
(c)
f1
(d)
iBD
iA
(e)
FIGURE 12.14 Current waveforms for the Graetz bridge.
ID LD vA
iA
vB
iB
vC
ID LD
+
vD
vA
iA
vB
iB
vC
iC
vD
VD
iC
VD
_
_
(a)
+
(b)
FIGURE 12.15 Onequadrant bridge converter circuits: (a) halfcontrolled bridge and (b) freewheeling diode bridge.
because diodes are considerably less expensive than thyristors and they do not require ﬁring angle control electronics. The half controlled bridge, or “semiconverter,” is analyzed by considering it as a phasecontrolled halfwave circuit in series with an uncontrolled halfwave rectiﬁer. The average dc voltage is given by the following equation
VD =
3·
√
2 · Vfsec −f 2π
(1 + cos α)
(12.15)
Then, the average voltage VD never reaches negative values. The output voltage waveforms of halfcontrolled bridge are similar to those of a fully controlled bridge with a freewheeling diode. The advantage of the freewheeling diode connection, shown in Fig. 12.15b is that there is always a path for the dc current, independent of the status of the ac line and of the converter. This can be important if the load is inductive– resistive with a large time constant, and there is an interruption in one or more of the line phases. In such a case, the load current could commutate to the freewheeling diode.
210
J. W. Dixon ON
ID
OFF isc vA
LS Vff
vB
T1
iG
LD T3
T2
LS
VD
vD vC
LS
N T4
T6
T5
FIGURE 12.16 Commutation process.
12.2.6 Commutation The description of the converters in the previous sections was based upon assumption that the commutation was instantaneous. In practice this is not possible, because the transfer of current between two consecutive valves in a commutation group takes a ﬁnite time. This time, called overlap time, depends on the phasetophase voltage between the valves participating in the commutation process, and the line inductance LS between the converter and power supply. During the overlap time, two valves conduct, and the phasetophase voltage drops entirely on the inductances LS . Assuming the dc current ID to be smooth and with the help of Fig. 12.16, the following relation is deduced 2LS ·
√ disc = 2 · Vf −f sin ωt = vA − vB dt
(12.16)
where isc is the current in the valve being ﬁred during the commutation process (thyristor T2 in Fig. 12.16). This current can be evaluated, and it yields isc = −
√ cos ωt 2 · Vf −f +C 2LS ω
(12.17)
The constant “C” is evaluated through initial conditions at the instant when T2 is ignited. In terms of angle, when ωt = α when ωt = α,
isc = 0
Vfsec −f ∴C = √ cos α 2 · ωLS
(12.18)
Replacing Eq. (12.18) in (12.17): Vf −f isc = √ · (cos α − cos ωt ) 2 · ωLS
Before commutation, the current ID was carried by thyristor T1 (see Fig. 12.16). During the commutation time, the load current ID remains constant, isc returns through T1, and T1 is automatically switched off when the current isc reaches the value of ID . This happens because thyristors cannot conduct in reverse direction. At this moment, the overlap time lasts and the current ID is then conducted by T2. In terms of angle, when ωt = α + µ, isc = ID , where µ is deﬁned as the “overlap angle.” Replacing this ﬁnal condition in Eq. (12.19) yields Vfsec −f ID = √ · [cos α − cos (α + µ)] 2 · ωLS
To avoid confusion in a real analysis, it has to be remembered that Vf −f corresponds to the secondary voltage in case of transformer utilization. For this reason, the abbreviation “sec” has been added to the phasetophase voltage in Eq. (12.20). During commutation, two valves conduct at a time, which means that there is an instantaneous short circuit between the two voltages participating in the process. As the inductances of each phase are the same, the current isc produces the same voltage drop in each LS , but with opposite sign because this current ﬂows in reverse direction and with opposite slope in each inductance. The phase with the higher instantaneous voltage suffers a voltage drop −v and the phase with the lower voltage suffers a voltage increase +v. This situation affects the dc voltage VC , reducing its value an amount Vmed . Figure 12.17 shows the meanings of v, Vmed , µ, and isc . The area Vmed showed in Fig. 12.17, represents the loss of voltage that affects the average voltage VC , and can be evaluated through the integration of v during the overlap angle µ. The voltage drop v can be expressed as
(12.19)
(12.20)
v =
vA − vB 2
=
√ 2 · Vfsec −f sin ωt 2
(12.21)
12
211
Threephase Controlled Rectiﬁers vD
a
vDpos
DVmed Dv
vc
vb
Dv wt
va
m ib
ia
ic
ID
isc
FIGURE 12.17 Effect of the overlap angle on the voltages and currents.
Integrating Eq. (12.21) into the corresponding period (60◦ ) and interval (µ) and starting at the instant when the commutation begins (α)
Vmed
α+µ
√
3 1 = · π 2
Vmed =
sin ωt · dωt
(12.22)
√
2
[cos α − cos (α + µ)]
(12.23)
Subtracting Vmed in Eq. (12.13) VD = VD =
3·
3·
√
2 · Vfsec −f
cos α − Vmed
(12.24)
[cos α + cos (α + µ)]
(12.25)
2 · Vfsec µ µ −f cos α + cos π 2 2
(12.26)
√
π 2 · Vfsec −f 2π
or VD =
3·
√
VD =
√ 3· 2 3ID ωLS prim · a · Vf −f cos α − π π
(12.29)
α
3 · Vfsec −f π·
2 · Vfsec −f
prim
where a = Vfsec −f /Vf −f . With Eqs. (12.27) and (12.28) one gets
Equation (12.29) allows a very simple equivalent circuit of the converter to be made, as shown in Fig. 12.18. It is important to note that the equivalent resistance of this circuit is not real, because it does not dissipate power. From the equivalent circuit, regulation curves for the rectiﬁer under different ﬁring angles are shown in Fig. 12.19. It should be noted that these curves correspond only to an ideal situation, but helps in understanding the effect of voltage drop v on dc voltage. The commutation process and the overlap angle also affects the voltage va and anodetocathode thyristor voltage, as shown in Fig. 12.20.
3wLS/p
Equations (12.20) and (12.25) can be written as a function of the primary winding of the transformer, if there is any transformer.
(virtual resistance) +
prim
a · Vf −f ID = √ · [cos α − cos (α + µ)] 2 · ωLS √ prim 3 · 2 · a · Vf −f VD = [cos α + cos (α + µ)] 2π
ID
(12.27)
(12.28)
_
(3√2/p)aVff cosa
VD
FIGURE 12.18 Equivalent circuit for the converter.
212
J. W. Dixon
By substituting Eqs. (12.30), (12.31), and (12.32) into Eq. (12.33), the power factor can be expressed as follows
VD (3√2/p)aVff
3wLS /p . IDo
(3√2/p)a Vff cosa1
α = 0°
(3√2/p)a Vff cosa2
α1
PF =
α2>α1
(12.34)
This equation shows clearly that due to the nonsinusoidal waveform of the currents, the power factor of the rectiﬁer is negatively affected by both the ﬁring angle α and the distortion of the input current. In effect, an increase in the distortion of the current produces an increase in the value of Irms in a Eq. (12.34), which deteriorates the power factor.
ID
IDo
rms Ia1 cos α Iarms
FIGURE 12.19 DC voltage regulation curves for rectiﬁer operation.
12.2.7 Power Factor The displacement factor of the fundamental current, obtained from Fig. 12.14 is cos φ1 = cos α
12.2.8 Harmonic Distortion The currents of the linecommutated rectiﬁers are far from being sinusoidal. For example, the currents generated from the Graetz rectiﬁer (see Fig. 12.14b) have the following harmonic content √ 2 3 1 1 iA = ID (cos ωt − cos 5ωt + cos 7ωt π 5 7
(12.30)
In the case of nonsinusoidal current, the active power delivered per phase by the sinusoidal supply is P=
1 T
0
T
rms cos φ1 va (t )ia (t )dt = Varms Ia1
(12.31)
−
rms where Vrms a is the rms value of the voltage va and Ia1 the rms value of ia1 (fundamental component of ia ). Analog relations can be obtained for vb and vc . The apparent power per phase is given by
S = Varms Iarms The power factor is deﬁned by
√ 6 I1 = ID π
(12.33)
ia
a m va
m
(12.35)
Some of the characteristics of the currents, obtained from Eq. (12.35) include: (i) the absence of triple harmonics; (ii) the presence of harmonics of order 6k ± 1 for integer values of k; (iii) those harmonics of orders 6k + 1 are of positive sequence; (iv) those of orders 6k − 1 are of negative sequence; (v) the rms magnitude of the fundamental frequency is
(12.32)
P PF = S
1 cos 11ωt + . . .) 11
vAK
wt
FIGURE 12.20 Effect of the overlap angle on va and on thyristor voltage vAK .
(12.36)
12
213
Threephase Controlled Rectiﬁers
and (vi) the rms magnitude of the nth harmonic is In =
I1 n
(12.37)
If either, the primary or the secondary threephase windings of the rectiﬁer transformer are connected in delta, the ac side current waveforms consist of the instantaneous differences between two rectangular secondary currents 120◦ apart as shown in Fig. 12.14e. The resulting Fourier series for the current in phase “a” on the primary side is √ 1 2 3 1 iA = ID (cos ωt + cos 5ωt − cos 7ωt π 5 7 −
1 cos 11ωt + . . .) 11
(12.38)
5th
iA
Y iaY
D
17th to ∞
√ 1 2 3 1 iA = 2 ID (cos ωt − cos 11ωt + cos 13ωt π 11 13 1 cos 23ωt + . . .) 23
(12.39)
The series only contains harmonics of order 12k ± 1. The harmonic currents of orders 6k ± 1 (with k odd), i.e. 5th, 7th, 17th, 19th, etc. circulate between the two converter transformers but do not penetrate the ac network. The resulting line current for the 12pulse rectiﬁer, shown in Fig. 12.23, is closer to a sinusoidal waveform than previous line currents. The instantaneous dc voltage is also smoother with this connection.
ID
vA
13th
in Fig. 12.22. The resultant ac current is given by the sum of the two Fourier series of the star connection (Eq. (12.35)) and delta connection transformers (Eq. (12.38))
−
A common solution for harmonic reduction is through the connection of passive ﬁlters, which are tuned to trap a particular harmonic frequency. A typical conﬁguration is shown in Fig. 12.21. However, harmonics also can be eliminated using special conﬁgurations of converters. For example, 12pulse conﬁguration consists of two sets of converters connected as shown
11th
FIGURE 12.21 Typical passive ﬁlter for one phase.
This series differs from that of a star connected transformer only by the sequence of rotation of harmonic orders 6k ± 1 for odd values of k, i.e. the 5th, 7th, 17th, 19th, etc.
12.2.9 Special Conﬁgurations for Harmonic Reduction
7th
iaD
iB
ibY
ibD
iC
icY
icD
FIGURE 12.22 12pulse rectiﬁer conﬁguration.
214
J. W. Dixon
iA
wt
FIGURE 12.23 Line current for the 12pulse rectiﬁer.
Y
iA
iC
iB
FIGURE 12.24 DC ripple reinjection technique for 48pulse operation.
Higher pulse conﬁguration using the same principle is also possible. The 12pulse rectiﬁer was obtained with a 30◦ phase shift between the two secondary transformers. The addition of further, appropriately shifted, transformers in parallel provides the basis for increasing pulse conﬁgurations. For instance, 24pulse operation is achieved by means of four transformers with 15◦ phase shift, and 48pulse operation requires eight transformers with 7.5◦ phase shift (transformer connections in zigzag conﬁguration). Although theoretically possible, pulse numbers above 48 are rarely justiﬁed due to the practical levels of distortion found in the supply voltage waveforms. Further, the converter topology becomes more and more complicated. An ingenious and very simple way to reach high pulse operation is shown in Fig. 12.24. This conﬁguration is called dc ripple reinjection. It consists of two parallel converters connected to the load through a multistep reactor. The reactor uses a chain of thyristorcontrolled taps, which are connected to symmetrical points of the reactor. By ﬁring the thyristors located at the reactor at the right time, highpulse operation is reached. The level of pulse operation depends on the number of thyristors connected to the reactor. They multiply the
basic level of operation of the two converters. The example, is Fig. 12.24, shows a 48pulse conﬁguration, obtained by the multiplication of basic 12pulse operation by four reactor thyristors. This technique also can be applied to series connected bridges. Another solution for harmonic reduction is the utilization of active power ﬁlters. Active power ﬁlters are special pulse width modulated (PWM) converters, able to generate the harmonics the converter requires. Figure 12.25 shows a current controlled shunt active power ﬁlter.
12.2.10 Applications of Linecommutated Rectiﬁers in Machine Drives Important applications for linecommutated threephase controlled rectiﬁers, are found in machine drives. Figure 12.26 shows a dc machine control implemented with a sixpulse rectiﬁer. Torque and speed are controlled through the armature current ID , and excitation current Iexc . Current ID is adjusted with VD , which is controlled by the ﬁring angle α through Eq. (12.12). This dc drive can operate in two quadrants: positive and negative dc voltage. This twoquadrant
12
215
Threephase Controlled Rectiﬁers jX
IS
IL
Linecommutated converter
VS
IL
IF IS Reference Current Calculation
IF
Shunt Active Filter
FIGURE 12.25 Current controlled shunt active power ﬁlter.
operation allows regenerative braking when α > 90◦ and Iexc < 0. The converter of Fig. 12.26 can also be used to control synchronous machines, as shown in Fig. 12.27. In this case, a second converter working in the inverting mode operates the machine as selfcontrolled synchronous motor. With this second converter, the synchronous motor behaves like a dc motor but has none of the disadvantages of mechanical commutation. This converter is not line commutated, but machine commutated. The nominal synchronous speed of the motor on a 50 or 60 Hz ac supply is now meaningless and the upper speed limit is determined by the mechanical limitations of the rotor construction. There is disadvantage that the rotational emfs required for load commutation of the machine side converter are not available at standstill and low speeds. In such a case, auxiliary force commutated circuits must be used. The linecommutated rectiﬁer controls the torque of the machine through ﬁring angle α. This approach gives direct torque control of the commutatorless motor and is analogous to the use of armature current control shown in Fig. 12.26 for the converterfed dc motor drive. Linecommutated rectiﬁers are also used for speed control of wound rotor induction motors. Subsynchronous and supersynchronous static converter cascades using a naturally commutated dc link converter, can be implemented. Figure 12.28 shows a supersynchronous cascade for a wound
rotor induction motor, using a naturally commutated dc link converter. In the supersynchronous cascade shown in Fig. 12.28, the right hand bridge operates at slip frequency as a rectiﬁer or inverter, while the other operates at network frequency as an inverter or rectiﬁer. Control is difﬁcult near synchronism when slip frequency emfs are insufﬁcient for natural commutation and special circuit conﬁguration employing forced commutation or devices with a selfturnoff capability are necessary for the passage through synchronism. This kind of supersynchronous cascade works better with cycloconverters.
12.2.11 Applications in HVDC Power Transmission High voltage direct current (HVDC) power transmission is the most powerful application for linecommutated converters that exist today. There are power converters with ratings in excess of 1000 MW. Series operation of hundreds of valves can be found in some HVDC systems. In high power and long distance applications, these systems become more economical than conventional ac systems. They also have some other advantages compared with ac systems: 1. they can link two ac systems operating unsynchronized or with different nominal frequencies, that is 50 ↔ 60 Hz;
ID = I A
vA
iA
vB
iB
vC
iC
LD Iexc. vD
VD a
FIGURE 12.26 DC machine drive with a sixpulse rectiﬁer.
DCM
216
J. W. Dixon ID
LD vA
iA
vB
iB
vC
iC
SPEED REF NREF
ia vD
+
SM ic
FIRING SIGNALS
+
ib
VD
FIRING SIGNALS
–
–
POSITIONTOVELOCITY CONVERTER
Position sensor
FIGURE 12.27 Selfcontrolled synchronous motor drive.
vA vB vC
TRANSFORMER
ID WOUND ROTOR INDUCTION MOTOR
LD
vDR
vDI
FIGURE 12.28 Supersynchronous cascade for a wound rotor induction motor.
2. they can help in stability problems related with subsynchronous resonance in long ac lines; 3. they have very good dynamic behavior and can interrupt shortcircuit problems very quickly; 4. if transmission is by submarine or underground cable, it is not practical to consider ac cable systems exceeding 50 km, but dc cable transmission systems are in service whose length is in hundreds of kilometers and even distances of 600 km or greater have been considered feasible; 5. reversal of power can be controlled electronically by means of the delay ﬁring angles α; and 6. some existing overhead ac transmission lines cannot be increased. If overbuilt with or upgraded to
dc transmission can substantially increase the power transfer capability on the existing rightofway. The use of HVDC systems for interconnections of asynchronous systems is an interesting application. Some continental electric power systems consist of asynchronous networks such as those for the East, West, Texas, and Quebec networks in North America, and islands loads such as that for the Island of Gotland in the Baltic Sea make good use of the HVDC interconnections. Nearly all HVDC power converters with thyristor valves are assembled in a converter bridge of 12pulse conﬁguration, as shown in Fig. 12.29. Consequently, the ac voltages applied to each sixpulse valve group which makes up the 12pulse
12
217
Threephase Controlled Rectiﬁers
ID
POWER SYSTEM 1 Y
POWER SYSTEM 2
D
VDI
VD
D
Y
(a)
Simplified Unilinear Diagram:
POWER SYSTEM 1
ID
PD I∠ϕ Vff prim
PDI
rD VDI
VD
Vff primI
I I∠ϕ
POWER SYSTEM 2 (b)
FIGURE 12.29 Typical HVDC power system: (a) detailed circuit and (b) unilinear diagram.
valve group have a phase difference of 30◦ which is utilized to cancel the ac side, 5th and 7th harmonic currents and dc side, 6th harmonic voltage, thus resulting in a signiﬁcant saving in harmonic ﬁlters. Some useful relations for HVDC systems include: a) Rectiﬁer Side: √ prim rms cos ϕ PD = VD · ID = 3 · Vf −f · Iline
PD
IQ =
√ prim a 2 3 · Vf −f
[sin 2(α + µ) − sin 2α − 2µ] 4π · ωLS √
a 6 cos α + cos (α + µ) IP = ID π 2
√ a 6 I= ID π
(12.40)
IP = I ·
VD
IP =
√ prim a 2 3 · Vf −f 4π · ωLS
[cos 2α − cos 2 (α + µ)]
cos α + cos (α + µ) 2
(12.47)
as IP = I cos ϕ, it yields Fig. 12.30a
IP = I cos ϕ
V D · ID IP = √ prim 3 · Vf −f
(12.46)
Replacing Eq. (12.46) in (12.45)
I∠j
IQ = I sin ϕ √ prim ∴ PD = VD · ID = 3 · Vf −f · IP
(12.45)
Fundamental secondary component of I
ID
prim Vff
(12.44)
(12.41) (12.42)
(12.43)
cos α + cos (α + µ) cos ϕ = 2
(12.48)
b) Inverter Side: The same equations are applied for the inverter side, but the ﬁring angle α is replaced by γ, where γ is γ = 180◦ − (α + µ)
(12.49)
218
J. W. Dixon α (a)
µ
wt
αI
(b)
wIt γ µI
αI
FIGURE 12.30 Deﬁnition of angle γ for inverter side: (a) rectiﬁer side and (b) inverter side.
LD /2
iD+
vA
+ vr –
iA
vB
iB
vC
iC
LD /2 i – D
+
vD
ir vD–
iD
Iexc.
DCM
FIGURE 12.31 Dual converter in a fourquadrant dc drive.
As reactive power always goes in the converter direction, Eq. (12.44) for inverter side becomes (Fig. 12.30b) √ prim aI2 3 · Vf −f I IQI = − [sin 2(γ + µI ) − sin 2γ − 2µI ] 4π · ωI LI (12.50)
12.2.12 Dual Converters In many variablespeed drives, fourquadrant operation is required, and threephase dual converters are extensively used in applications up to 2 MW level. Figure 12.31 shows a threephase dual converter, where two converters are connected backtoback. In the dual converter, one rectiﬁer provides the positive current to the load and the other the negative current. Due to the instantaneous voltage differences between the output
voltages of the converters, a circulating current ﬂows through the bridges. The circulating current is normally limited by circulating reactor, LD , as shown in Fig. 12.31. The two converters are controlled in such a way that if α+ is the delay angle of the positive current converter, the delay angle of the negative current converter is α− = 180◦ − α+ . Figure 12.32 shows the instantaneous dc voltages of each − converter, v+ D and vD . Despite the average voltage VD is the same in both the converters, their instantaneous voltage differences shown as voltage vr , are producing the circulating current ir , which is superimposed with the load currents i + D and i − D. To avoid the circulating current ir , it is possible to implement a “circulating current free” converter if a dead time of a few milliseconds is acceptable. The converter section, not required to supply current, remains fully blocked. When a current reversal is required, a logic switchover system determines
12
219
Threephase Controlled Rectiﬁers vD+
Firing angle: α+ VD
(a)
vD–
Firing angle: α– =180° – α+ VD
(b)
vD + – vD – = vr
vr ir
(c)
wt
FIGURE 12.32 Waveform of circulating current: (a) instantaneous dc voltage from positive converter: (b) instantaneous dc voltage from negative − converter; and (c) voltage difference between v+ D and vD , vr , and circulating current ir .
at ﬁrst the instant at which the conducting converter’s current becomes zero. This converter section is then blocked and the further supply of gating pulses to it is prevented. After a short safety interval (dead time), the gating pulses for the other converter section are released.
of threephase cycloconverters. Figure 12.34 is a diagram for this application. They are also used to control slip frequency in wound rotor induction machines, for supersynchronous cascade (Scherbius system).
12.2.13 Cycloconverters
12.2.14 Harmonic Standards and Recommended Practices
A different principle of frequency conversion is derived from the fact that a dual converter is able to supply an ac load with a lower frequency than the system frequency. If the control signal of the dual converter is a function of time, the output voltage will follow this signal. If this control signal value alters sinusoidally with the desired frequency, then the waveform depicted in Fig. 12.33a consists of a singlephase voltage with a large harmonic current. As shown in Fig. 12.33b, if the load is inductive, the current will present less distortion than voltage. The cycloconverter operates in all four quadrants during a period. A pause (dead time) at least as small as the time required by the switchover logic occurs after the current reaches zero, that is, between the transfer to operation in the quadrant corresponding to the other direction of current ﬂow. Three singlephase cycloconverters may be combined to build a threephase cycloconverter. The threephase cycloconverters ﬁnd an application in lowfrequency, highpower requirements. Control speed of large synchronous motors in the lowspeed range is one of the most common applications
In view of the proliferation of the power converter equipment connected to the utility system, various national and international agencies have been considering limits on harmonic current injection to maintain good power quality. As a consequence, various standards and guidelines have been established that specify limits on the magnitudes of harmonic currents and harmonic voltages. The Comité Européen de Normalisation Electrotechnique (CENELEC), International Electrical Commission (IEC), and West German Standards (VDE) specify the limits on the voltages (as a percentage of the nominal voltage) at various harmonics frequencies of the utility frequency, when the equipmentgenerated harmonic currents are injected into a network whose impedances are speciﬁed. According with Institute of Electrical and Electronic Engineers519 standards (IEEE), Table 12.1 lists the limits on the harmonic currents that a user of power electronics equipment and other nonlinear loads is allowed to inject into the
220
J. W. Dixon
vL
dead time vD–
vD+
(a)
iL (b)
FIGURE 12.33 Cycloconverter operation: (a) voltage waveform and (b) current waveform for inductive load.
POWER TRANSFORMERS
EXCITATION
ib
ia iexc
SM
FIGURE 12.34 Synchronous machine drive with a cycloconverter.
ic
12
221
Threephase Controlled Rectiﬁers TABLE 12.1
Harmonic current limits in percent of fundamental
Short circuit current (pu)
h < 11
11 < h < 17
17 < h < 23
23 < h < 35
35 < h
THD
1000
4.0 7.0 10.0 12.0 15.0
2.0 3.5 4.5 5.5 7.0
1.5 2.5 4.0 5.0 6.0
0.6 1.0 1.5 2.0 2.5
0.3 0.5 0.7 1.0 1.4
5.0 8.0 12.0 15.0 20.0
TABLE 12.2
Harmonic voltage limits in percent of fundamental
Voltage level
2.3–69 kV
69–138 kV
>138 kV
Maximum for individual harmonic Total harmonic distortion (THD)
3.0 5.0
1.5 2.5
1.0 1.5
utility system. Table 12.2 lists the quality of voltage that the utility can furnish the user. In Table 12.1, the values are given at the point of connection of nonlinear loads. The THD is the total harmonic distortion given by Eq. (12.51) and h is the number of the harmonic. THD =
∞
h=2
I1
it can be made leading; and (c) they can be built as voltage source or current source rectiﬁers; (d) the reversal of power in thyristor rectiﬁers is by reversal of voltage at the dc link. Instead, forcecommutated rectiﬁers can be implemented for both, reversal of voltage or reversal of current. There are two ways to implement forcecommutated threephase rectiﬁers: (a) as a current source rectiﬁer, where power reversal is by dc voltage reversal; and (b) as a voltage source rectiﬁer, where power reversal is by current reversal at the dc link. Figure 12.35 shows the basic circuits for these two topologies.
12.3.2 Operation of the Voltage Source Rectiﬁer
Ih2 (12.51)
The total current harmonic distortion allowed in Table 12.1 increases with the value of short circuit current. The total harmonic distortion in the voltage can be calculated in a manner similar to that given by Eq. (12.51). Table 12.2 speciﬁes the individual harmonics and the THD limits on the voltage that the utility supplies to the user at the connection point.
12.3 Forcecommutated Threephase Controlled Rectiﬁers 12.3.1 Basic Topologies and Characteristics Forcecommutated rectiﬁers are built with semiconductors with gateturnoff capability. The gateturnoff capability allows full control of the converter, because valves can be switched ON and OFF whenever is required. This allows the commutation of the valves, hundreds of times in one period which is not possible with linecommutated rectiﬁers, where thyristors are switched ON and OFF only once a cycle. This feature has the following advantages: (a) the current or voltage can be modulated (PWM), generating less harmonic contamination; (b) power factor can be controlled and even
The voltage source rectiﬁer is by far the most widely used, and because of the duality of the two topologies showed in Fig. 12.35, only this type of forcecommutated rectiﬁer will be explained in detail. The voltage source rectiﬁer operates by keeping the dc link voltage at a desired reference value, using a feedback control loop as shown in Fig. 12.36. To accomplish this task, the dc link voltage is measured and compared with a reference VREF . The error signal generated from this comparison is used to switch the six valves of the rectiﬁer ON and OFF. In this way, power can come or return to the ac source according with the dc link voltage requirements. The voltage VD is measured at the capacitor CD . When the current ID is positive (rectiﬁer operation), the capacitor CD is discharged, and the error signal ask the control block for more power from the ac supply. The control block takes the power from the supply by generating the appropriate PWM signals for the six valves. In this way, more current ﬂows from the ac to the dc side and the capacitor voltage is recovered. Inversely, when ID becomes negative (inverter operation), the capacitor CD is overcharged and the error signal ask the control to discharge the capacitor and return power to the ac mains. The PWM control can manage not only the active power, but also the reactive power, allowing this type of rectiﬁer to correct power factor. In addition, the ac current waveforms can be maintained as almost sinusoidal, which reduces harmonic contamination to the mains supply.
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J. W. Dixon
ID
LD
Power Source
+ vD
VD
dc load
(a)
CS
ref PWM SIGNALS
Power Source
idc
ID
LS
+ dc load
CD
VD
(b)
ref PWM SIGNALS
FIGURE 12.35 Basic topologies for forcecommutated PWM rectiﬁers: (a) current source rectiﬁer and (b) voltage source rectiﬁer.
ID
idc
LS
+ VD
CD
dc load
_ Control Block
error
+ VREF
FIGURE 12.36 Operation principle of the voltage source rectiﬁer.
The PWM consists of switching the valves ON and OFF, following a preestablished template. This template could be a sinusoidal waveform of voltage or current. For example, the modulation of one phase could be as the one shown in Fig. 12.37. This PWM pattern is a periodical waveform whose fundamental is a voltage with the same frequency of the template. The amplitude of this fundamental, called VMOD in Fig. 12.37, is also proportional to the amplitude of the template. To make the rectiﬁer work properly, the PWM pattern must generate a fundamental VMOD with the same frequency as the power source. Changing the amplitude of this fundamental and its phase shift with respect to the mains, the rectiﬁer can
be controlled to operate in the four quadrants: leading power factor rectiﬁer, lagging power factor rectiﬁer, leading power factor inverter, and lagging power factor inverter. Changing the pattern of modulation, as shown in Fig. 12.38, modiﬁes the magnitude of VMOD . Displacing the PWM pattern changes the phase shift. The interaction between VMOD and V (source voltage) can be seen through a phasor diagram. This interaction permits understanding of the fourquadrant capability of this rectiﬁer. In Fig. 12.39, the following operations are displayed: (a) rectiﬁer at unity power factor; (b) inverter at unity power factor; (c) capacitor (zero power factor); and (d) inductor (zero power factor).
12
223
Threephase Controlled Rectiﬁers
VD /2
PWM
VMOD
–VD /2
FIGURE 12.37 A PWM pattern and its fundamental VMOD . VMOD
PWM
VD /2
–VD /2
FIGURE 12.38 Changing VMOD through the PWM pattern.
In Fig. 12.39, IS is the rms value of the source current is . This current ﬂows through the semiconductors in the way shown in Fig. 12.40. During the positive half cycle, the transistor TN , connected at the negative side of the dc link is switched ON, and the current is begins to ﬂow through TN (iTn ). The current returns to the mains and comes back to the valves, closing a loop with another phase, and passing through a diode connected at the same negative terminal of the dc link. The current can also go to the dc load (inversion) and return through another transistor located at the positive terminal of the dc link. When the transistor TN is switched OFF, the current path is interrupted and the current begins to ﬂow through the diode DP , connected at the positive terminal of the dc link. This current, called iDp in Fig. 12.39, goes directly to the dc link, helping in the generation of the current idc . The current idc charges the capacitor CD and permits the rectiﬁer to produce dc power. The inductances LS are very important in this process, because they generate an induced voltage which allows the conduction of the diode DP . Similar operation occurs during the negative half cycle, but with TP and DN (see Fig. 12.40). Under inverter operation, the current paths are different because the currents ﬂowing through the transistors come mainly from the dc capacitor, CD . Under rectiﬁer operation,
the circuit works like a boost converter and under inverter, it works as a buck converter. To have full control of the operation of the rectiﬁer, their six diodes must be polarized negatively at all values of instantaneous ac voltage supply. Otherwise diodes will conduct, and the PWM rectiﬁer will behave like a common diode rectiﬁer bridge. The way to keep the diodes blocked is to ensure a dc link voltage higher than the peak dc voltage generated by the diodes alone, as shown in Fig. 12.41. In this way, the diodes remain polarized negatively, and they will conduct only when at least one transistor is switched ON, and favorable instantaneous ac voltage conditions are given. In the Fig. 12.41, VD represents the capacitor dc voltage, which is kept higher than the normal diodebridge rectiﬁcation value vBRIDGE . To maintain this condition, the rectiﬁer must have a control loop like the one displayed in Fig. 12.36.
12.3.3 PWM Phasetophase and Phasetoneutral Voltages The PWM waveforms shown in the preceding ﬁgures are voltages measured between the middle point of the dc voltage and the corresponding phase. The phasetophase PWM voltages
224
J. W. Dixon
V
ID
idc LS
IS
+ VMOD
VD
CD
dc load
_
(a) + VREF
error Control Block
V
IS
IS
V δ
j w LS IS
VMOD V
(b)
IS
VMOD j w LS IS
δ V
IS V
(c)
IS IS
V
j wLS IS VMOD (d)
V
IS
IS
VMOD
V j wLS IS (e)
FIGURE 12.39 Fourquadrant operation of the forcecommutated rectiﬁer: (a) the PWM forcecommutated rectiﬁer; (b) rectiﬁer operation at unity power factor; (c) inverter operation at unity power factor; (d) capacitor operation at zero power factor; and (e) inductor operation at zero power factor.
can be obtained with the help of Eq. (12.52), where the voltage VAB PWM is evaluated. AB A B VPWM = VPWM − VPWM
(12.52)
where VAPWM and VBPWM are the voltages measured between the middle point of the dc voltage, and the phases a and b respectively. In a less straightforward fashion, the phasetoneutral voltage can be evaluated with the help of Eq. (12.53). 1 AB AN CA VPWM = (VPWM − VPWM ) 3
(12.53)
where VAN PWM is the phasetoneutral voltage for phase a, and jk
VPWM is the phasetophase voltage between phase j and phase k. Figure 12.42 shows the PWM patterns for the phasetophase and phasetoneutral voltages.
12.3.4 Control of the DC Link Voltage Control of the dc link voltage requires a feedback control loop. As already explained in Section 12.3.2, the dc voltage VD is compared with a reference VREF , and the error signal “e” obtained from this comparison is used to generate a template waveform. The template should be a sinusoidal waveform with the same frequency of the mains supply. This template is used to produce the PWM pattern and allows controlling
12
225
Threephase Controlled Rectiﬁers is
iTn
t
iDp
idc
DP TP
LS
iTp
idc
is
v
ID
iDp VD
+
+ CD
dc load
DN TN
iTn
–
iDn
FIGURE 12.40 Current waveforms through the mains, the valves, and the dc link.
VD
dc link voltage VD must remain higher than the diode rectification voltage vBRIDGE (feedback control loop required).
vBRIDGE
FIGURE 12.41 The DC link voltage condition for the operation of the PWM rectiﬁer.
the rectiﬁer in two different ways: (1) as a voltagesource currentcontrolled PWM rectiﬁer or (2) as a voltagesource voltagecontrolled PWM rectiﬁer. The ﬁrst method controls the input current, and the second controls the magnitude and phase of the voltage VMOD . The currentcontrolled method is simpler and more stable than the voltagecontrolled method, and for these reasons it will be explained ﬁrst. 12.3.4.1 Voltagesource Currentcontrolled PWM Rectiﬁer This method of control is shown in the rectiﬁer in Fig. 12.43. Control is achieved by measuring the instantaneous phase
currents and forcing them to follow a sinusoidal current reference template, I_ref. The amplitude of the current reference template, IMAX is evaluated using the following equation IMAX = GC · e = GC · (VREF − vD )
(12.54)
where GC is shown in Fig. 12.43 and represents a controller such as PI, P, Fuzzy, or other. The sinusoidal waveform of the template is obtained by multiplying IMAX with a sine function, with the same frequency of the mains, and with the desired phaseshift angle ϕ, as shown in Fig. 12.43. Further, the template must be synchronized with the power supply. After that,
226
J. W. Dixon VPWMA
VMODAN
(a)
VPWMAB
(b)
VPWMAN
VMODAN
(c)
FIGURE 12.42 PWM phase voltages: (a) PWM phase modulation; (b) PWM phasetophase voltage; and (c) PWM phasetoneutral voltage.
v A = VM sin wt
LS
isA
R + vD
B
vB
is
vC
isC
I_line(a) I_line(b) I_line(c)
ia,b,c
PWM generation A
I_ref Synchr.
sin(wt + j)
sin(wt + j −120°)
LOAD
B
_
C IMAX
X
GC
e
+
VREF
X
sin(wt + j −240°)
X
FIGURE 12.43 Voltagesource currentcontrolled PWM rectiﬁer.
the template has been created and is ready to produce the PWM pattern. However, one problem arises with the rectiﬁer because the feedback control loop on the voltage VC can produce instability. Then it becomes necessary to analyze this problem during rectiﬁer design. Upon introducing the voltage feedback and the GC controller, the control of the rectiﬁer can be represented in a block diagram in Laplace dominion, as shown in Fig. 12.44. This block diagram represents a linearization of the system around an operating point, given by the rms value of the input current, IS .
The blocks G1 (s) and G2 (s) in Fig. 12.44 represent the transfer function of the rectiﬁer (around the operating point) and the transfer function of the dc link capacitor CD respectively. G1 (s) =
P1 (s) = 3 · (V cos ϕ − 2RIS − LS IS s) IS (s)
(12.55)
VD (s) 1 = P1 (s) − P2 (s) VD · CD · s
(12.56)
G2 (s) =
where P1 (s) and P2 (s) represent the input and output power of the rectiﬁer in Laplace dominion, V the rms value of
12
227
Threephase Controlled Rectiﬁers DP2 DVREF
+
DE –
GC
DIS
G1(s)
DP1
+
–
DVD
G2(s)
FIGURE 12.44 Closedloop rectiﬁer transfer function.
the mains voltage supply (phasetoneutral), IS the input current being controlled by the template, LS the input inductance, and R the resistance between the converter and power supply. According to stability criteria, and assuming a PI controller, the following relations are obtained CD · VD 3KP · LS
(12.57)
KP · V · cos ϕ 2R · KP + LS · KI
(12.58)
IS ≤ IS ≤
I_line (a)
+
I_ref
D Q flipflop CLK
–
sampling clock
hysteresis band adjust I_line
These two relations are useful for the design of the currentcontrolled rectiﬁer. They relate the values of dc link capacitor, dc link voltage, rms voltage supply, input resistance and inductance, and input power factor, with the rms value of the input current, IS . With these relations the proportional and integral gains KP and KI can be calculated to ensure the stability of the rectiﬁer. These relations only establish limitations for rectiﬁer operation, because negative currents always satisfy the inequalities. With these two stability limits satisﬁed, the rectiﬁer will keep the dc capacitor voltage at the value of VREF (PI controller), for all load conditions, by moving power from the ac to the dc side. Under inverter operation, the power will move in the opposite direction. Once the stability problems have been solved and the sinusoidal current template has been generated, a modulation method will be required to produce the PWM pattern for the power valves. The PWM pattern will switch the power valves to force the input currents I_line to follow the desired current template I_ref. There are many modulation methods in the literature, but three methods for voltagesource currentcontrolled rectiﬁers are the most widely used ones: periodical sampling (PS), hysteresis band (HB), and triangular carrier (TC). The PS method switches the power transistors of the rectiﬁer during the transitions of a square wave clock of ﬁxed frequency: the periodical sampling frequency. In each transition, a comparison between I_ref and I_line is made, and corrections take place. As shown in Fig. 12.45a, this type of control is very simple to implement: only a comparator and a Dtype ﬂipﬂop are needed per phase. The main advantage of this method is that the minimum time between switching
PWM
(b)
+
I_ref
I_line
I_err + –
(c)
PWM
–
kp + ki/s
+
PWM
–
I_ref V_tri
FIGURE 12.45 Modulation control methods: (a) periodical sampling; (b) hysteresis band; and (c) triangular carrier.
transitions is limited to the period of the sampling clock. This characteristic determines the maximum switching frequency of the converter. However, the average switching frequency is not clearly deﬁned. The HB method switches the transistors when the error between I_ref and I_line exceeds a ﬁxed magnitude: the hysteresis band. As it can be seen in Fig. 12.45b, this type of control needs a single comparator with hysteresis per phase. In this case the switching frequency is not determined, but its maximum value can be evaluated through the following equation fSmax =
VD 4h · LS
(12.59)
where h is the magnitude of the hysteresis band. The TC method, shown in Fig. 12.45c, compares the error between I_ref and I_line with a triangular wave. This triangular wave has ﬁxed amplitude and frequency and is called the triangular carrier. The error is processed through a
228
J. W. Dixon
proportionalintegral (PI) gain stage before comparison with the TC takes place. As can be seen, this control scheme is more complex than PS and HB. The values for kp and ki determine the transient response and steadystate error of the TC method. It has been found empirically that the values for kp and ki shown in Eqs. (12.60) and (12.61) give a good dynamic performance under several operating conditions. Ls · ωc 2 · VD
(12.60)
ki = ωc · KP
(12.61)
kp =
where LS is the total series inductance seen by the rectiﬁer, ωc is the TC frequency, and VD is the dc link voltage of the rectiﬁer. In order to measure the level of distortion (or undesired harmonic generation) introduced by these three control methods, Eq. (12.62) is deﬁned
(a) (b) (c) (d)
FIGURE 12.46 Waveforms obtained using 1.5 kHz switching frequency and LS = 13 mH: (a) PS method; (b) HB method; (c) TC method (KP + KI ); and (d) TC method (KP only).
(12.62)
with PI control are quite similar, and the TC with only proportional control gives a current with a small phase shift. However, Fig. 12.47 shows that the higher the switching frequency, the closer the results obtained with the different modulation methods. Over 6 kHz of switching frequency, the distortion is very small for all methods.
In Eq. (12.62), the term Irms is the effective value of the desired current. The term inside the square root gives the rms value of the error current, which is undesired. This formula measures the percentage of error (or distortion) of the generated waveform. This deﬁnition considers the ripple, amplitude, and phase errors of the measured waveform, as opposed to the THD, which does not take into account offsets, scalings, and phase shifts. Figure 12.46 shows the current waveforms generated by the three aforementioned methods. The example uses an average switching frequency of 1.5 kHz. The PS is the worst, but its digital implementation is simpler. The HB method and TC
12.3.4.2 Voltagesource Voltagecontrolled PWM Rectiﬁer Figure 12.48 shows a onephase diagram from which the control system for a voltagesource voltagecontrolled rectiﬁer is derived. This diagram represents an equivalent circuit of the fundamentals, that is, pure sinusoidal at the mains side and pure dc at the dc link side. The control is achieved by creating a sinusoidal voltage template VMOD , which is modiﬁed in amplitude and angle to interact with the mains voltage V. In this way the input currents are controlled without measuring them. The template VMOD is generated using the differential equations that govern the rectiﬁer.
100 1 %Distortion = (I _line − I _ref )2 dt Irms T T
14 Periodical Sampling
% Distortion
12 Hysteresis Band
10 8
Triangular Carrier (KP*+KI*)
6
Triangular Carrier (only KP*)
4 2 0 1000
2000
3000
4000
5000
6000
Switching Frequency (Hz) FIGURE 12.47 Distortion comparison for a sinusoidal current reference.
7000
12
229
Threephase Controlled Rectiﬁers idc v(t)
ID
vMOD(t) is(t) VD LS
R
SOURCE
+
CD LOAD
acdc conversion
RECTIFIER
LOAD
FIGURE 12.48 Onephase fundamental diagram of the voltage source rectiﬁer.
The following differential equation can be derived from Fig. 12.48 dis (12.63) + Ris + vMOD (t ) dt √ Assuming that v(t ) = V 2 sin ωt , then the solution for is (t ), to acquire a template VMOD able to make the rectiﬁer work at constant power factor, should be of the form v(t ) = LS
is (t ) = Imax (t ) sin(ωt + ϕ)
(12.64)
Equations (12.63), (12.64), and v(t) allows a function of time able to modify VMOD in amplitude and phase that will make the rectiﬁer work at a ﬁxed power factor. Combining these equations with v(t) yields
√ dImax vMOD (t ) = V 2 + XS Imax sin ϕ − RImax + LS cos ϕ sin ωt dt
dImax sin ϕ cos ωt − XS Imax cos ϕ + RImax + LS dt
(12.65) Equation (12.65) provides a template for VMOD , which is controlled through variations of the input current amplitude Imax . Substituting the derivatives of Imax into Eq. (12.65) make sense, because Imax changes every time the dc load is modiﬁed. The term XS in Eq. (12.65) is ωLS . This equation can also be written for unity power factor operation. In such a case, cos ϕ = 1 and sin ϕ = 0. √ dImax vMOD (t ) = V 2 − RImax − LS sin ωt dt − XS Imax cos ωt
(12.66)
With this last equation, a unity power factor, voltage source, voltagecontrolled PWM rectiﬁer can be implemented as shown in Fig. 12.49. It can be observed that Eqs. (12.65) and (12.66) have an inphase term with the mains supply (sin ωt ) and an inquadrature term (cos ωt ). These two terms allow
the template VMOD to change in magnitude and phase so as to have full unity power factor control of the rectiﬁer. Compared with the control block of Fig. 12.43, in the voltagesource voltagecontrolled rectiﬁer of Fig. 12.49, there is no need to sense the input currents. However, to ensure stability limits as good as the limits of the currentcontrolled rectiﬁer, the blocks “–R–sLS ” and “–XS ” in Fig. 12.49, have to emulate and reproduce exactly the real values of R, XS , and LS of the power circuit. However, these parameters do not remain constant, and this fact affects the stability of this system, making it less stable than the system showed in Fig. 12.43. In theory, if the impedance parameters are reproduced exactly, the stability limits of this rectiﬁer are given by the same equations as used for the currentcontrolled rectiﬁer seen in Fig. 12.43 (Eqs. (12.57) and (12.58)). Under steadystate, Imax is constant, and Eq. (12.66) can be written in terms of phasor diagram, resulting in Eq. (12.67). As shown in Fig. 12.50, different operating conditions for the unity power factor rectiﬁer can be displayed with this equation VMOD = V − R IS − jXS IS
(12.67)
With the sinusoidal template VMOD already created, a modulation method to commutate the transistors will be required. As in the case of currentcontrolled rectiﬁer, there are many methods to modulate the template, with the most well known the socalled sinusoidal pulse width modulation (SPWM), which uses a TC to generate the PWM as shown in Fig. 12.51. Only this method will be described in this chapter. In this method, there are two important parameters to deﬁne: the amplitude modulation ratio or modulation index m, and the frequency modulation ratio p. Deﬁnitions are given by m=
max VMOD max VTRIANG
(12.68)
fT fS
(12.69)
p=
max where Vmax MOD and VTRIANG are the amplitudes of VMOD and VTRIANG respectively. On the other hand, fS is the frequency of
230
J. W. Dixon
v A = VM sin ωt L S
idc isA isB
vB
ID
R VD+
LOAD
C
is
vC
PWM generation vMODA vMODB vMODC
+ _
VM sin(wt)
Synchr.
sin(wt) cos(wt)
Imax
–R–sLs
X X
e
GC
+
VREF
–Xs
FIGURE 12.49 Implementation of the voltagecontrolled rectiﬁer for unity power factor operation. V
IS
IS
V δ jwLSIS VMOD RIS
IS
V δ
jwLSIS
VMOD
RIS
VMOD IS = 0
V
VMOD
jwLSIS
δ IS
V
RIS
VMOD
jwLSIS
δ IS
V
RIS
FIGURE 12.50 Steadystate operation of the unity power factor rectiﬁer under different load conditions.
12
231
Threephase Controlled Rectiﬁers COMPARATOR VMODA VTRIANG VTRIANG
+
VPWMA
–
VMODA
VPWMA
VPWMAN
FIGURE 12.51 Sinusoidal modulation method based on TC.
the mains supply and fT the frequency of the TC. In Fig. 12.51, m = 0.8 and p = 21. When m > 1 overmodulation is deﬁned. The modulation method described in Fig. 12.51 has a harmonic content that changes with p and m. When p < 21, it is recommended that synchronous PWM be used, which means that the TC and the template should be synchronized. Furthermore, to avoid subharmonics, it is also desired that p be an
Vff
rms
integer. If p is an odd number, even harmonics will be eliminated. If p is a multiple of 3, then the PWM modulation of the three phases will be identical. When m increases, the amplitude of the fundamental voltage increases proportionally, but some harmonics decrease. Under overmodulation (m > 1), the fundamental voltage does not increase linearly, and more harmonics appear. Figure 12.52 shows the harmonic spectrum
/VD
0.6 m=1 0.5 m = 0.8 0.4 m = 0.6 0.3 m = 0.4 0.2
0.1
1
p−4 p−2 p
p+2 p+4
2p − 5 2p − 1 2p 2p + 1
2p + 5 3p − 4 3p − 2 3p
FIGURE 12.52 Harmonic spectrum for SPWM modulation.
3p + 2 3p + 4
232
J. W. Dixon
P =9 P =15 P = 21 P = 27 P = 39 P =81
FIGURE 12.53 Current waveforms for different values of p.
of the threephase PWM voltage waveforms for different values of m, and p = 3k where k is an odd number. Due to the presence of the input inductance LS , the harmonic currents that result are proportionally attenuated with the harmonic number. This characteristic is shown in the current waveforms of Fig. 12.53, where larger p numbers generate cleaner currents. The rectiﬁer that originated the currents of Fig. 12.53 has the following characteristics: VD = 450 Vdc , Vrms f −f = 220 Vac , LS = 2 mH, and input current IS = 80 Arms . It can be observed that with p > 21 the current distortion is quite small. The value of p = 81 in Fig. 12.53 produces an almost pure sinusoidal waveform, and it means 4860 Hz
of switching frequency at 60 Hz or only 4.050 Hz in a rectiﬁer operating in a 50 Hz supply. This switching frequency can be managed by MOSFETs, IGBTs, and even Power Darlingtons. Then a number p = 81, is feasible for today’s low and medium power rectiﬁers. 12.3.4.3 Voltagesource Loadcontrolled PWM Rectiﬁer A simple method of control for small PWM rectiﬁers (up to 10–20 kW) is based on direct control of the dc current. Figure 12.54 shows the schematic of this control system. The fundamental voltage VMOD modulated by the rectiﬁer is produced by a ﬁxed and unique PWM pattern, which can be carefully selected to eliminate most undesirable harmonics. As the PWM does not change, it can be stored in a permanent digital memory (ROM). The control is based on changing the power angle δ between the mains voltage V and fundamental PWM voltage VMOD . When δ changes, the amount of power ﬂow transferred from the ac to the dc side also changes. When the power angle is negative (VMOD lags V), the power ﬂow goes from the ac to the dc side. When the power angle is positive, the power ﬂows in the opposite direction. Then, the power angle can be controlled through the current ID . The voltage VD does not need to be sensed, because this control establishes a stable dc voltage operation for each dc current and power angle. With these characteristics, it is possible to ﬁnd a relation between ID and δ so as to obtain constant dc voltage for all load conditions.
idc
v A = VM sin wt L S
isA
vB
isB
vC
isC
+ VD
Synchr.
IS
V d
ID
R
DIGITAL CONTROL WITH FIXED PWM PATTERN jwLSIS
_
+
δOFFSET
VMOD
LOAD
d=f(Id) d
ID RIS
FIGURE 12.54 Voltagesource loadcontrolled PWM rectiﬁer.
12
233
Threephase Controlled Rectiﬁers
This relation is given by S V cos δ − ωL R sin δ − 1
ID = f (δ) = 2 S R 1 + ωL R
(12.70)
From Eq. (12.70) a plot and a reciprocal function δ = f(ID ) is obtained to control the rectiﬁer. The relation between ID and δ allows for leading power factor operation and null regulation. The leading power factor operation is shown in the phasor diagram of Fig. 12.54. The control scheme of the voltagesource loadcontrolled rectiﬁer is characterized by the following: (i) there are neither input current sensors nor dc voltage sensor; (ii) it works with a ﬁxed and predeﬁned PWM pattern; (iii) it presents very good stability; (iv) its stability does not depend on the size of the dc capacitor; (v) it can work at leading power factor for all load conditions; and (vi) it can be adjusted with Eq. (12.70) to work at zero regulation. The drawback appears when R in Eq. (12.70) becomes negligible, because in such a case the control system is unable to ﬁnd an equilibrium point for the dc link voltage. That is why this control method is not applicable to large systems.
12.3.5 New Technologies and Applications of Forcecommutated Rectiﬁers The additional advantages of forcecommutated rectiﬁers with respect to linecommutated rectiﬁers, make them better candidates for industrial requirements. They permit new applications such as rectiﬁers with harmonic elimination capability (active ﬁlters), power factor compensators, machine drives with fourquadrant operation, frequency links to connect 50 Hz with 60 Hz systems, and regenerative converters for traction power supplies. Modulation with very fast valves such as IGBTs permit almost sinusoidal currents to be obtained. The dynamics of these rectiﬁers is so fast that they can reverse power almost instantaneously. In machine drives, current source PWM rectiﬁers, like the one shown in Fig. 12.35a, can be used to drive dc machines from the threephase supply. Fourquadrant applications using voltagesource PWM rectiﬁers, are extended for induction machines, synchronous machines with starting control, and special machines such as brushlessdc motors. Backtoback systems are being used in Japan to link power systems with different frequencies. 12.3.5.1 Active Power Filter Forcecommutated PWM rectiﬁers can work as active power ﬁlters. The voltagesource currentcontrolled rectiﬁer has the capability to eliminate harmonics produced by other polluting loads. It only needs to be connected as shown in Fig. 12.55.
The current sensors are located at the input terminals of the power source and these currents (instead of the rectiﬁer currents) are forced to be sinusoidal. As there are polluting loads in the system, the rectiﬁer is forced to deliver the harmonics that loads need, because the current sensors do not allow the harmonics going to the mains. As a result, the rectiﬁer currents become distorted, but an adequate dc capacitor CD can keep the dc link voltage in good shape. In this way the rectiﬁer can do its duty, and also eliminate harmonics to the source. In addition, it also can compensate power factor and unbalanced load problems. 12.3.5.2 Frequency Link Systems Frequency link systems permit power to be transferred form one frequency to another one. They are also useful for linking unsynchronized networks. Linecommutated converters are widely used for this application, but they have some drawbacks that forcecommutated converters can eliminate. For example, the harmonic ﬁlters requirement, the poor power factor, and the necessity to count with a synchronous compensator when generating machines at the load side are absent. Figure 12.56 shows a typical linecommutated system in which a 60 Hz load is fed by a 50 Hz supply. As the 60 Hz side needs excitation to commutate the valves, a synchronous compensator has been required. In contrast, an equivalent system with forcecommutated converters is simpler, cleaner, and more reliable. It is implemented with a dc voltagecontrolled rectiﬁer, and another identical converter working in the inversion mode. The power factor can be adjusted independently at the two ac terminals, and ﬁlters or synchronous compensators are not required. Figure 12.57 shows a frequency link system with forcecommutated converters. 12.3.5.3 Special Topologies for High Power Applications High power applications require series and/or parallelconnected rectiﬁers. Series and parallel operation with forcecommutated rectiﬁers allow improving the power quality because harmonic cancellation can be applied to these topologies. Figure 12.58 shows a series connection of forcecommutated rectiﬁers, where the modulating carriers of the valves in each bridge are shifted to cancel harmonics. The example uses sinusoidal PWM that are with TC shifted. The waveforms of the input currents for the series connection system are shown in Fig. 12.59. The frequency modulation ratio shown in this ﬁgure is for p = 9. The carriers are shifted by 90◦ each, to obtain harmonics cancellation. Shifting of the carriers δT depends on the number of converters in series (or in parallel), and is given by δT =
2π n
(12.71)
234
J. W. Dixon I_line(a)
iLA
I_line(b)
iLB
POLLUTING LOADS
iLC
Lf
ifA
ifB ifC + VD
CD
LOAD
ia,b,c
I_line(a) I_line(b) I_line(c)
PWM generation A
I_ref Synchr.
sin(wt + j)
B
IMAX
X
sin(wt + j−120°)
_
C GC
+
e
VREF
X
sin(wt + j−240°)
X
FIGURE 12.55 Voltagesource rectiﬁer with harmonic elimination capability.
ID
50 Hz
∆
LD
∆
Y
∆
∆
Y
α control Passive Filter
synchr.
60 Hz
Excitation Voltage Egg
γ control
Synchronous Compensator Master Control
FIGURE 12.56 Frequency link systems with linecommutated converters.
Passive Filter
12
235
Threephase Controlled Rectiﬁers
50 Hz
50 Hz
60 Hz VD
+
PWM
PWM
−
CONVERTER
CONVERTER
PWM DC LINK VOLTAGE CONTROL
60 Hz
PWM
−
+
VD
REF
POWER CONTROL
FIGURE 12.57 Frequency link systems with forcecommutated converters. MAINS SUPPLY
ID
VD(1)
SPWM generation
VT(1)
C vMODA v vMODB MOD
VD(2)
SPWM generation
VT(2)
C vMODA v vMODB MOD
VD
VD(3)
SPWM generation
VT(3)
C vMODA v vMODB MOD
VD(M)
SPWM generation
vMODA vMODB vMODC
VT(4)
MONITOR
VD −
VM sin(ωt) sin(ωt)
RsLs
cos(ωt)
Xs
IMAX
GC
VREF +
FIGURE 12.58 Series connection system with forcecommutated rectiﬁers.
236
J. W. Dixon
Current in one of the four converters in series
Total current
FIGURE 12.59 Input currents and carriers of the series connection system of Fig. 12.58.
Total current with four converters in series and p = 9
Current with one converter and p = 36
FIGURE 12.60 Four converters in series and p = 9 compared with one converter and p = 36.
where n is the number of converters in series or in parallel. It can be observed that despite the low value of p, the total current becomes quite clean and clear, better than the current of one of the converters in the chain. The harmonic cancellation with series or parallelconnected rectiﬁers, using the same modulation but the carriers shifted, is quite effective. The resultant current is better with n converters and frequency modulation p = p1 than with one converter and p = n · p1 . This attribute is veriﬁed in Fig. 12.60, where the total current of four converters in series with p = 9 and carriers shifted, is compared with the current of only one converter and p = 36. This technique also allows for the use of valves with slow commutation times, such as high power GTOs. Generally, high power valves have low commutation times and hence the parallel and/or series options remain very attractive. Another special topology for high power was implemented for Asea Brown Boveri (ABB) in Bremen. A 100 MW power 2 converter supplies energy to the railways at 16 /3 Hz. It uses
basic “H” bridges like the one shown in Fig. 12.61, connected to the load through power transformers. These transformers are connected in parallel at the converter side, and in series at the load side. The system uses SPWM with TCs shifted, and depending on the number of converters connected in the chain of bridges, the voltage waveform becomes more and more sinusoidal. Figure 12.62 shows a backtoback system using a chain of 12 “H” converters connected as showed in Fig. 12.61b. The ac voltage waveform obtained with the topology of Fig. 12.62 is displayed in Fig. 12.63. It can be observed that the voltage is formed by small steps that depend on the number of converters in the chain (12 in this case). The current is almost perfectly sinusoidal. Figure 12.64 shows the voltage waveforms for different number of converters connected in the bridge. It is clear that the larger the number of converters, the better the voltage. Another interesting result with this converter is that the ac voltages become modulated by both PWM and amplitude
12
237
Threephase Controlled Rectiﬁers
Vinv
+
(a) GTO
load
Vinv
Vinv
+
Vinv
(b)
load FIGURE 12.61 The “H” modulator: (a) one bridge and (b) bridges connected in series at load side through isolation transformers.
ID1
50 Hz
phase "b" phase "c"
Neutral
"H" "H" "H" "H" "H" "H" "H" "H" "H" "H" "H" "H"
ID2 "H" "H" "H" "H" "H" "H" "H" "H" "H" "H" "H" "H"
VD
PWM
60 Hz phase "b" phase "c"
Neutral
PWM
DC LINK VOLTAGE CONTROL
POWER CONTROL
POWER CONVERTERS Phase “a” FIGURE 12.62 Frequency link with forcecommutated converters and sinusoidal voltage modulation.
modulation (AM). This is because when the pulse modulation changes, the steps of the amplitude change. The maximum number of steps of the resultant voltage is equal to the number of converters. When the voltage decreases, some steps disappear, and then the AM becomes a discrete function. Figure 12.65 shows the AM of the voltage.
12.3.5.4 Machine Drives Applications One of the most important applications of forcecommutated rectiﬁers is in machine drives. Linecommutated thyristor converters have limited applications because they need excitation to extinguish the valves. This limitation do not allow the use of linecommutated converters in induction machine drives.
238
J. W. Dixon
V
IS
FIGURE 12.63 Voltage and current waveforms with 12 converters.
H
2H
4H
8H
12H
16H
FIGURE 12.64 Voltage waveforms with different numbers of “H” bridges in series.
On the other hand, with forcecommutated converters fourquadrant operation is achievable. Figure 12.66 shows a typical frequency converter with a forcecommutated rectiﬁer– inverter link. The rectiﬁer side controls the dc link, and the inverter side controls the machine. The machine can be a synchronous, brushless dc, or induction machine. The reversal of
both speed and power are possible with this topology. At the rectiﬁer side, the power factor can be controlled, and even with an inductive load such as an induction machine, the source can “see” the load as capacitive or resistive. Changing the frequency of the inverter controls the machine speed, and the torque is controlled through the stator currents and
12
239
Threephase Controlled Rectiﬁers
0,5 Vnom 0,7 Vnom 0,9 Vnom
FIGURE 12.65 Amplitude modulation of the “H” bridges of Fig. 12.62.
a + vD
b
c −
CONTROL
e
+ VREF
CONTROL
FIGURE 12.66 Frequency converter with forcecommutated converters.
TRACTION MOTOR
SOFTSTART DRIVING  CHARGING ELECTRONIC SWITCH SELECTOR
a
b
c
+ BATTERY PACK
FILTERS AND SENSORS
−
CONTROL
POWER SOURCE
POWER CONVERTER (INVERTER  RECTIFIER)
FIGURE 12.67 Electric bus system with regenerative braking and battery charger.
torque angle. The inverter will become a rectiﬁer during regenerative braking, which is possible by making slip negative in an induction machine, or by making the torque angle negative in synchronous and brushless dc machines. A variation of the drive of Fig. 12.66 is found in electric traction applications. Battery powered vehicles use the inverter as a rectiﬁer during regenerative braking, and sometimes the inverter is also used as a battery charger. In this case, the rectiﬁer can be fed by a singlephase or threephase system.
Figure 12.67 shows a batterypowered electric bus system. This system uses the power inverter of the traction motor as rectiﬁer for two purposes: regenerative braking and as a battery charger fed by a threephase power source. 12.3.5.5 Variable Speed Power Generation Power generation at 50 or 60 Hz requires constant speed machines. In addition, induction machines are not currently
240
J. W. Dixon
a
+ VD
c
MAINS
b SLIP CONTROL
WIND GENERATOR
VREF
− +
e
VD CONTROL
FIGURE 12.68 Variablespeed constantfrequency wind generator.
ID
idc C LS
+ VD
dc load
C
FIGURE 12.69 Voltagesource rectiﬁer using threelevel converter.
used in power plants because of magnetization problems. With the use of frequencylink forcecommutated converters, variablespeed constantfrequency generation becomes possible even with induction generators. The power plant in Fig. 12.68 shows a wind generator implemented with an induction machine, and a rectiﬁer–inverter frequency link connected to the utility. The dc link voltage is kept constant with the converter located at the mains side. The converter connected at the machine side controls the slip of the generator and adjusts it according to the speed of wind or power requirements. The utility is not affected by the power factor of the generator, because the two converters keep the cos ϕ of the machine independent of the mains supply. The converter at the mains side can even be adjusted to operate at leading power factor. Variblespeed constantfrequency generation also can be used in either hydraulic or thermal plants. This allows for optimal adjustment of the efﬁciencyspeed characteristics of the machines. In many places, wound rotor induction generators working as variable speed synchronous machines are being used as constant frequency generators. They operate in hydraulic plants that are able to store water during low demand periods. A power converter is connected at the slip rings of the generator. The rotor is then fed with variable frequency
excitation. This allows the generator to generate at different speeds around the synchronous rotating ﬂux. 12.3.5.6 Power Rectiﬁers Using Multilevel Topologies Almost all voltage source rectiﬁers already described are twolevel conﬁgurations. Today, multilevel topologies are becoming very popular, mainly threelevel converters. The most popular threelevel conﬁguration is called diode clamped converter, which is shown in Fig. 12.69. This topology is today the standard solution for high power steel rolling mills, which uses backtoback threephase rectiﬁer–inverter link conﬁguration. In addition, this solution has been recently introduced in high power downhill conveyor belts which operate almost permanently in the regeneration mode or rectiﬁer operation. The more important advantage of threelevel rectiﬁers is that voltage and current harmonics are reduced due to the increased number of levels. Higher number of levels can be obtained using the same diode clamped strategy, as shown in Fig. 12.70, where only one phase of a general approach is displayed. However, this topology becomes more and more complex with the increase of number of levels. For this reason, new topologies are being
12
241
Threephase Controlled Rectiﬁers
+ AC
dc load
VD −
FIGURE 12.70 Multilevel rectiﬁer using diode clamped topology.
R + jωLS
iSa
a b H Bridges
H Bridges
H Bridges
A2
A2
A2
A1
A1
A1
M
M
M
c AC Source
iSb iSc
iDC +
e CONTROL BLOCK
vDC
C
−
+ VREF = 750 V
Phase reference
FIGURE 12.71 27Level rectiﬁer for railways, using Hbridges scaled in power of three.
studied to get a large number of levels with less power transistors. One example of such of these topologies is the multistage, 27level converter shown in Fig. 12.71. This special 27level, fourquadrant rectiﬁer, uses only three Hbridges per phase with independent input transformers for each Hbridge. The transformers allow galvanic isolation and power escalation to get high quality voltage waveforms, with THD of less than 1%.
The power scalation consists on increasing the voltage rates of each transformer making use of the “threelevel” characteristics of Hbridges. Then, the number of levels is optimized when transformers are scaled in power of three. Some advantages of this 27level topology are: (a) only one of the three Hbridges, called “main converter,” manages more than 80% of the total active power in each phase and (b) this main
242
J. W. Dixon
νRECT
20 [V/div] 50 [Hz]
FIGURE 12.72 AC voltage waveform generated by the 27level rectiﬁer.
converter switches at fundamental frequency reducing the switching losses at a minimum value. The rectiﬁer of Fig. 12.71 is a currentcontrolled voltage source type, with a conventional feedback control loop, which is being used as a rectiﬁer in a subway substation. It includes fast reversal of power and the ability to produce clean ac and dc waveforms with negligible ripple. This rectiﬁer can also compensate power factor and eliminate harmonics produced by other loads in the ac line. Figure 12.72 shows the ac voltage waveform obtained with this rectiﬁer from an experimental prototype. If one more Hbridge is added, 81 levels are obtained, because the number of levels increases according with N = 3k , where N is the number of levels or voltage steps and k the number of Hbridges used per phase. Many other highlevel topologies are under study but this matter is beyond the main topic of this chapter.
Further Reading 1. G. Möltgen, “Line Commutated Thyristor Converters,” Siemens Aktiengesellschaft, BerlinMunich, Pitman Publishing, London, 1972. 2. G. Möltgen, “Converter Engineering, and Introduction to Operation and Theory,” John Wiley and Sons, New York, 1984. 3. K. Thorborg, “Power Electronics,” PrenticeHall International (UK) Ltd., London, 1988. 4. M. H. Rashid, “Power Electronics, Circuits Devices and Applications,” PrenticeHall International Editions, London, 1992. 5. N. Mohan, T. M. Undeland, and W. P. Robbins, “Power Electronics: Converters, Applications, and Design,” John Wiley and Sons, New York 1989. 6. J. Arrillaga, D. A. Bradley, and P. S. Bodger, “Power System Harmonics,” John Wiley and Sons, New York, 1989. 7. J. M. D. Murphy and F. G. Turnbull, “Power Electronic Control of AC Motors,” Pergamon Press, 1988.
8. M. E. Villablanca and J. Arrillaga, “Pulse Multiplication in Parallel Convertors by Multitap Control of Interphase Reactor,” IEE ProceedingsB, Vol. 139, No 1; January 1992, pp. 13–20. 9. D. A. Woodford, “HVDC Transmission,” Professional Report from Manitoba HVDC Research Center, Winnipeg, Manitoba, March 1998. 10. D. R. Veas, J. W. Dixon, and B. T. Ooi, “A Novel Load Current Control Method for a Leading Power Factor Voltage Source PEM Rectiﬁer,” IEEE Transactions on Power Electronics, Vol. 9, No 2, March 1994, pp. 153–159. 11. L. Morán, E. Mora, R. Wallace, and J. Dixon, “Performance Analysis of a Power Factor Compensator which Simultaneously Eliminates Line Current Harmonics,” IEEE Power Electronics Specialists Conference, PESC’92, Toledo, España, June 29 to July 3, 1992. 12. P. D. Ziogas, L. Morán, G. Joos, and D. Vincenti, “A Reﬁned PWM Scheme for Voltage and Current Source Converters,” IEEEIAS Annual Meeting, 1990, pp. 977–983. 13. W. McMurray, “Modulation of the Chopping Frequency in DC Choppers and PWM Inverters Having Current Hysteresis Controllers,” IEEE Transaction on Ind. Appl., Vol. IA20, July/August 1984, pp. 763–768. 14. J. W. Dixon and B. T. Ooi, “Indirect Current Control of a Unity Power Factor Sinusoidal Current Boost Type ThreePhase Rectiﬁer,” IEEE Transactions on Industrial Electronics, Vol. 35, No 4, November 1988, pp. 508–515. 15. L. Morán, J. Dixon, and R. Wallace “A ThreePhase Active Power Filter Operating with Fixed Switching Frequency for Reactive Power and Current Harmonic Compensation,” IEEE Transactions on Industrial Electronics, Vol. 42, No 4, August 1995, pp. 402–408. 16. M. A. Boost and P. Ziogas, “StateoftheArt PWM Techniques, a Critical Evaluation,” IEEE Transactions on Industry Applications, Vol. 24, No 2, March/April 1988, pp. 271–280. 17. J. W. Dixon and B. T. Ooi, “Series and Parallel Operation of Hysteresis CurrentControlled PWM Rectiﬁers,” IEEE Transactions on Industry Applications, Vol. 25, No 4, July/August 1989, pp. 644–651.
12
Threephase Controlled Rectiﬁers
18. B. T. Ooi, J. W. Dixon, A. B. Kulkarni, and M. Nishimoto, “An integrated AC Drive System Using a ControlledCurrent PWM Rectiﬁer/Inverter Link,” IEEE Transactions on Power Electronics, Vol. 3, No 1, January 1988, pp. 64–71. 19. M. Koyama, Y. Shimomura, H. Yamaguchi, M. Mukunoki, H. Okayama, and S. Mizoguchi, “Large Capacity High Efﬁciency ThreeLevel GCT Inverter System for Steel Rolling Mill Drivers,” Proceedings of the 9th European Conference on Power Electronics, EPE 2001, Austria, CDROM.
243 20. J. Rodríguez, J. Dixon, J. Espinoza, and P. Lezana, “PWM Regenerative Rectiﬁers: State of the Art,” IEEE Transactions on Industrial Electronics, Vol. 52, No 4, January/February 2005, pp. 5–22. 21. J. Dixon and L. Morán, “A Clean FourQuadrant Sinusoidal Power Rectiﬁer, Using Multistage Converters for Subway Applications,” IEEE Transactions on Industrial Electronics, Vol. 52, No 5, May–June 2005, pp. 653–661.
13 DC–DC Converters Dariusz Czarkowski Department of Electrical and Computer Engineering, Polytechnic University, Brooklyn, New York, USA
13.1 Introduction......................................................................................... 245 13.2 DC Choppers ....................................................................................... 246 13.3 Stepdown (Buck) Converter................................................................... 247 13.3.1 Basic Converter • 13.3.2 Transformer Versions of Buck Converter
13.4 Stepup (Boost) Converter ...................................................................... 250 13.5 Buck–Boost Converter ........................................................................... 251 13.5.1 Basic Converter • 13.5.2 Flyback Converter
13.6 13.7 13.8 13.9 13.10
` Converter ...................................................................................... 252 Cuk Effects of Parasitics ................................................................................ 253 Synchronous and Bidirectional Converters................................................. 254 Control Principles ................................................................................. 255 Applications of DC–DC Converters .......................................................... 258 Further Reading .................................................................................... 259
13.1 Introduction Modern electronic systems require high quality, small, lightweight, reliable, and efﬁcient power supplies. Linear power regulators, whose principle of operation is based on a voltage or current divider, are inefﬁcient. They are limited to output voltages smaller than the input voltage. Also, their power density is low because they require lowfrequency (50 or 60 Hz) line transformers and ﬁlters. Linear regulators can, however, provide a very high quality output voltage. Their main area of application is at low power levels as low dropout voltage (LDO) regulators. Electronic devices in linear regulators operate in their active (linear) modes. At higher power levels, switching regulators are used. Switching regulators use power electronic semiconductor switches in on and off states. Since there is a small power loss in those states (low voltage across a switch in the on state, zero current through a switch in the off state), switching regulators can achieve high energy conversion efﬁciencies. Modern power electronic switches can operate at high frequencies. The higher the operating frequency, the smaller and lighter the transformers, ﬁlter inductors, and capacitors. In addition, dynamic characteristics of converters improve with increasing operating frequencies. The bandwidth of a control loop is usually determined by the
Copyright © 2007, 2001, Elsevier Inc. All rights reserved.
corner frequency of the output ﬁlter. Therefore, high operating frequencies allow for achieving a faster dynamic response to rapid changes in the load current and/or the input voltage. Highfrequency electronic power processors are used in dc–dc power conversion. The functions of dc–dc converters are: • • • • • •
to convert a dc input voltage VS into a dc output voltage VO ; to regulate the dc output voltage against load and line variations; to reduce the ac voltage ripple on the dc output voltage below the required level; to provide isolation between the input source and the load (isolation is not always required); to protect the supplied system and the input source from electromagnetic interference (EMI); to satisfy various international and national safety standards.
The dc–dc converters can be divided into two main types: hardswitching pulse width modulated (PWM) converters, and resonant and softswitching converters. This chapter deals with the former type of dc–dc converters. The PWM converters have been very popular for the last three decades. They are
245
246
D. Czarkowski
widely used at all power levels. Topologies and properties of PWM converters are well understood and described in literature. Advantages of PWM converters include low component count, high efﬁciency, constant frequency operation, relatively simple control and commercial availability of integrated circuit controllers, and ability to achieve high conversion ratios for both stepdown and stepup application. A disadvantage of PWM dc–dc converters is that PWM rectangular voltage and current waveforms cause turnon and turnoff losses in semiconductor devices which limit practical operating frequencies to a megahertz range. Rectangular waveforms also inherently generate EMI. This chapter starts from a section on dc choppers which are used primarily in dc drives. The output voltage of dc choppers is controlled by adjusting the on time of a switch which in turn adjusts the width of a voltage pulse at the output. This is so called pulsewidth modulation (PWM) control. The dc choppers with additional ﬁltering components form PWM dc–dc converters. Four basic dc–dc converter topologies are presented in Sections 13.3–13.6: buck, boost, buck–boost, and ` Cuk converters. Popular isolated versions of these converters are also discussed. Operation of converters is explained under ideal component and semiconductor device assumptions. Section 13.7 discusses effects of nonidealities in PWM converters. Section 13.8 presents topologies for increased efﬁciency at low output voltage and for bidirectional power ﬂow. Section 13.9 reviews control principles of PWM dc–dc converters. Two main control schemes, voltagemode control and currentmode control, are described. Summary of application areas of PWM dc–dc converters is given in Section 13.10. Finally, a list of modern textbooks on power electronics is provided. These books are excellent resources for deeper exploration of the area of dc–dc power conversion.
A stepdown dc chopper with a resistive load is shown in Fig. 13.1a. It is a series connection of a dc input voltage source VS , controllable switch S, and load resistance R. In most cases, switch S has a unidirectional voltage blocking capabilities and unidirectional current conduction capabilities. Power electronic switches are usually implemented with power MOSFETs, IGBTs, MCTs, power BJTs, or GTOs. If an antiparallel diode is used or embedded in a switch, a switch exhibits a bidirectional current conduction property. Figure 13.1b depicts waveforms in a stepdown chopper. The switch is being operated with a duty ratio D deﬁned as a ratio of the switch on time to the sum of the on the off times. For a constant frequency operation, ton ton = ton + toff T
+ Vs
vo –
(a)
vo
VS
S closed 0
S open DT
T


(13.1)
t
(1–D)T (b)
FIGURE 13.1 DC chopper with resistive load: (a) circuit diagram and (b) output voltage waveform.
where T = 1/f is the period of the switching frequency f. The average value of the output voltage is VO = DVS
13.2 DC Choppers
D≡
S
(13.2)
and can be regulated by adjusting duty ratio D. The average output voltage is always smaller than the input voltage, hence, the name of the converter. The dc stepdown choppers are commonly used in dc drives. In such a case, the load is presented as a series combination of inductance L, resistance R, and back emf E as shown in Fig. 13.2a. To provide a path for a continuous inductor current ﬂow when the switch is in the off state, an antiparallel diode D must be connected across the load. Since the chopper of Fig. 13.2a provides a positive voltage and a positive current to the load, it is called a ﬁrstquadrant chopper. The load voltage and current are graphed in Fig. 13.2b under assumptions that the load current never reaches zero and the load time constant τ = L/R is much greater than the period T. Average values of the output voltage and current can be adjusted by changing the duty ratio D.
13
247
DC–DC Converters S R
VS
D
L
E
+
vO
vO VS
t
iO
0
DT
T
t
(b)
FIGURE 13.2 DC chopper with RLE load: (a) circuit diagram and (b) waveforms.
The stepdown dc–dc converter, commonly known as a buck converter, is shown in Fig. 13.4a. It consists of dc input voltage source VS , controlled switch S, diode D, ﬁlter inductor L, ﬁlter capacitor C, and load resistance R. Typical waveforms in the converter are shown in Fig. 13.4b under assumption that the inductor current is always positive. The state of the converter in which the inductor current is never zero for any period of time is called the continuous conduction mode (CCM). It can be seen from the circuit that when the switch S is commanded to the on state, the diode D is reverse biased. When the switch S is off, the diode conducts to support an uninterrupted current in the inductor. The relationship among the input voltage, output voltage, and the switch duty ratio D can be derived, for instance, from the inductor voltage vL waveform (see Fig. 13.4b). According to Faraday’s law, the inductor volt–second product over a period of steadystate operation is zero. For the buck converter (VS − VO )DT = −VO (1 − D)T
(13.3)
Hence, the dc voltage transfer function, deﬁned as the ratio of the output voltage to the input voltage, is
D
L
13.3 Stepdown (Buck) Converter 13.3.1 Basic Converter
–
(a)
0
the load. This results in a topology of a boost dc–dc converter that is described in Section 13.4.
+
VS
S
Load
MV ≡
VO =D VS
(13.4)
vO
–
FIGURE 13.3 The dc stepup chopper.
The dc choppers can also provide peak output voltages higher than the input voltage. Such a stepup conﬁguration is presented in Fig. 13.3. It consists of dc input source VS , inductor L connected in series with the source, switch S connecting the inductor to ground, and a series combination of diode D and load. If the switch operates with a duty ratio D, the output voltage is a series of pulses of duration (1−D)T and amplitude VS /(1 − D). Neglecting losses, the average value of the output voltage is VS . To obtain an average value of the output voltage greater than VS , a capacitor must be connected in parallel with
It can be seen from Eq. (13.4) that the output voltage is always smaller than the input voltage. The dc–dc converters can operate in two distinct modes with respect to the inductor current iL . Figure 13.4b depicts the CCM in which the inductor current is always greater than zero. When the average value of the input current is low (high R) and/or the switching frequency f is low, the converter may enter the discontinuous conduction mode (DCM). In the DCM, the inductor current is zero during a portion of the switching period. The CCM is preferred for high efﬁciency and good utilization of semiconductor switches and passive components. The DCM may be used in applications with special control requirements, since the dynamic order of the converter is reduced (the energy stored in the inductor is zero at the beginning and at the end of each switching period). It is uncommon to mix these two operating modes because of different control algorithms. For the buck converter, the value
248
D. Czarkowski iL
S
+
+ vL –
iS VS
IO
L
iC D
R VO
C
Almost all of this ac component ﬂows through the ﬁlter capacitor as a current ic . Current ic causes a small voltage ripple across the dc output voltage VO . To limit the peaktopeak value of the ripple voltage below certain value Vr , the ﬁlter capacitance C must be greater than Cmin =
–
vL VS–VO t
iL
0
t
iC
0
(13.6)
At D = 0.5, Vr /VO = 1%, L = 25 µH, and f = 100 kHz, the minimum capacitance is Cmin = 25 µF. Equations (13.5) and (13.6) are the key design equations for the buck converter. The input and output dc voltages (hence, the duty ratio D), and the range of load resistance R are usually determined by preliminary speciﬁcations. The designer needs to determine values of passive components L and C, and of the switching frequency f. The value of the ﬁlter inductor L is calculated from the CCM/DCM condition using Eq. (13.5). The value of the ﬁlter capacitor C is obtained from the voltage ripple condition Eq. (13.6). For the compactness and low conduction losses of a converter, it is desirable to use small passive components. Equations (13.5) and (13.6) show that it can be accomplished by using a high switching frequency f. The switching frequency is limited, however, by the type of semiconductor switches used and by switching losses. It should be also noted that values of L and C may be altered by effects of parasitic components in the converter, especially by the equivalent series resistance of the capacitor. The issue of parasitic components in dc–dc converters is discussed in Section 13.7.
(a)
0 –VO
(1 − D) VO 8Vr Lf 2
t
13.3.2 Transformer Versions of Buck Converter iS
0
DT
T
2T
t
(b)
FIGURE 13.4 Buck converter: (a) circuit diagram and (b) waveforms.
of the ﬁlter inductance that determines the boundary between CCM and DCM is given by Lb =
(1 − D)R 2f
(13.5)
For typical values of D = 0.5, R = 10 , and f = 100 kHz, the boundary is Lb = 25 µH. For L > Lb , the converter operates in the CCM. The ﬁlter inductor current iL in the CCM consists of a dc component IO with a superimposed triangular ac component.
In many dc power supplies, a galvanic isolation between the dc or ac input and the dc output is required for safety and reliability. An economical mean of achieving such an isolation is to employ a transformer version of a dc–dc converter. Highfrequency transformers are of a small size and weight and provide high efﬁciency. Their turns ratio can be used to additionally adjust the output voltage level. Among buckderived dc–dc converters, the most popular are: forward converter, push–pull converter, halfbridge converter, and fullbridge converter. A. Forward Converter The circuit diagram of a forward converter is depicted in Fig. 13.5. When the switch S is on, diode D1 conducts and diode D2 is off. The energy is transferred from the input, through the transformer, to the output ﬁlter. When the switch is off, the state of diodes D1 and D2 is reversed. The dc voltage transfer function of the forward converter is MV = where n = N1 /N2 .
D n
(13.7)
13
249
DC–DC Converters S
D1
D1
L
L +
+
· · N1
D3 VS
S1
N2
C
D2
R
·
VS /2 VO
N3
N1
VS
–
FIGURE 13.5 Forward converter.
VS /2
In the forward converter, the energytransfer current ﬂows through the transformer in one direction. Hence, an additional winding with diode D3 is needed to bring the magnetizing current of the transformer to zero. This prevents transformer saturation. The turns ratio N1 /N3 should be selected in such a way that the magnetizing current decreases to zero during a fraction of the time interval when the switch is off. Equations (13.5) and (13.6) can be used to design the ﬁlter components. The forward converter is very popular for low power applications. For medium power levels, converters with bidirectional transformer excitation (push–pull, halfbridge, and fullbridge) are preferred due to better utilization of magnetic components. B. Push–Pull Converter The PWM dc–dc push–pull converter is shown in Fig. 13.6. The switches S1 and S2 operate shifted in phase by T/2 with the same duty ratio D. The duty ratio must be smaller than 0.5. When switch S1 is on, diode D1 conducts and diode D2 is off. Diode states are reversed when switch S2 is on. When both controllable switches are off, the diodes are on and share equally the ﬁlter inductor current. The dc voltage transfer function of the push–pull converter is 2D MV = n
(13.8)
where n = N1 /N2 . The boundary value of the ﬁlter inductor is Lb =
(1 − 2D)R 4f
D1
(13.9)
C
· · ·
R
N2
– D2
S2
FIGURE 13.7 Halfbridge converter.
The ﬁlter capacitor can be obtained from Cmin =
(1 − 2D)VO 32Vr Lf 2
(13.10)
C. Halfbridge Converter Figure 13.7 shows the dc–dc halfbridge converter. The operation of the PWM halfbridge converter is similar to that of the push–pull converter. In comparison to the push– pull converter, the primary of the transformer is simpliﬁed at the expense of two voltagesharing input capacitors. The halfbridge converter dc voltage transfer function is MV ≡
VD D = VS n
(13.11)
where D ≤ 0.5. Equations (13.9) and (13.10) apply to the ﬁlter components. D. Fullbridge Converter Comparing the PWM dc–dc fullbridge converter of Fig. 13.8 to the halfbridge converter, it can be seen that the input capacitors have been replaced by two controllable switches. The controllable switches are operated in pairs. When S1 and S4 are on, voltage VS is applied to the primary of the transformer and diode D1 conducts, With S2 and S3 on, there is voltage −VS across the primary transformer and diode D2 D1
L
L +
+
· · · ·
N1
VS
C
N2
S1 R
S2
· · ·
VO –
N1
VS
D2
S1 S2
FIGURE 13.6 Push–pull converter.
VO
S3
C
N2
R
VO –
D2
S4
FIGURE 13.8 Fullbridge converter.
250
D. Czarkowski
is on. With all controllable switches off, both diodes conduct, similarly as in the push–pull and halfbridge converters. The dc voltage transfer function of the fullbridge converter is
MV ≡
VO 2D = VS n
(13.12)
where D ≤ 0.5. Values of ﬁlter components can be obtained from Eqs. (13.9) and (13.10). It should be stressed that the fullbridge topology is a very versatile one. With different control algorithms, it is very popular in dc–ac conversion (squarewave and PWM singlephase inverters). It is also used in fourquadrant dc drives.
L
D
iL
IO +
+ vL –
VS
iC
iS S
R VO
C
– (a) vL VS 0 VS–VO
t
13.4 Stepup (Boost) Converter Figure 13.9a depicts a stepup or a PWM boost converter. It is comprised of dc input voltage source VS , boost inductor L, controlled switch S, diode D, ﬁlter capacitor C, and load resistance R. The converter waveforms in the CCM are presented in Fig. 13.9b. When the switch S is in the on state, the current in the boost inductor increases linearly. The diode D is off at the time. When the switch S is turned off, the energy stored in the inductor is released through the diode to the input RC circuit. Using the Faraday’s law for the boost inductor VS DT = (VO − VS )(1 − D)T
(13.13)
iL
0
t
iS
0
t
iC
from which the dc voltage transfer function turns out to be
MV ≡
VO 1 = VS 1−D
(13.14)
0 –IO
t DT
T
2T (b)
As the name of the converter suggests, the output voltage is always greater than the input voltage. The boost converter operates in the CCM for L > Lb where
Lb =
(1 − D)2 DR 2f
(13.15)
For D = 0.5, R = 10 , and f = 100 kHz, the boundary value of the inductance is Lb = 6.25 µH. As shown in Fig. 13.9b, the current supplied to the output RC circuit is discontinuous. Thus, a larger ﬁlter capacitor is required in comparison to that in the buckderived converters to limit the output voltage ripple. The ﬁlter capacitor must provide the output dc current to the load when the diode D
FIGURE 13.9 Boost converter: (a) circuit diagram and (b) waveforms.
is off. The minimum value of the ﬁlter capacitance that results in the voltage ripple Vr is given by
Cmin =
DVO Vr Rf
(13.16)
At D = 0.5, Vr /VO = 1%, R = 10 , and f = 100 kHz, the minimum capacitance for the boost converter is Cmin = 50 µF. The boost converter does not have a popular transformer (isolated) version.
13
251
DC–DC Converters
13.5 Buck–Boost Converter 13.5.1 Basic Converter A nonisolated (transformerless) topology of the buck–boost converter is shown in Fig. 13.10a. The converter consists of dc input voltage source VS , controlled switch S, inductor L, diode D, ﬁlter capacitor C, and load resistance R. With the switch on, the inductor current increases while the diode is
maintained off. When the switch is turned off, the diode provides a path for the inductor current. Note the polarity of the diode which results in its current being drawn from the output. The buck–boost converter waveforms are depicted in Fig. 13.10b. The condition of a zero volt–second product for the inductor in steady state yields VS DT = −VO (1 − D)T
(13.17)
Hence, the dc voltage transfer function of the buck–boost converter is S
D
VO D =− VS 1−D
(13.18)
+
iS VS
MV ≡
IO
iL L
+ vL –
iC R
C
VO
– (a)
The output voltage VO is negative with respect to the ground. Its magnitude can be either greater or smaller (equal at D = 0.5) than the input voltage as the converter’s name implies. The value of the inductor that determines the boundary between the CCM and DCM is Lb =
vL VS 0 VO
t
(1 − D)2 R 2f
(13.19)
The structure of the output part of the converter is similar to that of the boost converter (reversed polarities being the only difference). Thus, the value of the ﬁlter capacitor can be obtained from Eq. (13.16).
13.5.2 Flyback Converter iL
0
t
iS
0
t
iC
0 –IO
t DT
T
2T (b)
FIGURE 13.10 Buck–boost converter: (a) circuit diagram and (b) waveforms.
A PWM ﬂyback converter is a very practical isolated version of the buck–boost converter. The circuit of the ﬂyback converter is presented in Fig. 13.11a. The inductor of the buck–boost converter has been replaced by a ﬂyback transformer. The input dc source VS and switch S are connected in series with the primary transformer. The diode D and the RC output circuit are connected in series with the secondary of the ﬂyback transformer. Figure 13.11b shows the converter with a simple ﬂyback transformer model. The model includes a magnetizing inductance Lm and an ideal transformer with a turns ratio n = N1 /N2 . The ﬂyback transformer leakage inductances and losses are neglected in the model. It should be noted that leakage inductances, although not important from the principle of operation point of view, affect adversely switch and diode transitions. Snubbers are usually required in ﬂyback converters. Refer to Fig. 13.11b for the converter operation. When the switch S is on, the current in the magnetizing inductance increases linearly. The diode D is off and there is no current in the ideal transformer windings. When the switch is turned off, the magnetizing inductance current is diverted into the ideal transformer, the diode turns on, and the transformed
252
D. Czarkowski D
S
L1
iC1
IL1
C1
L2
IL2
+
·
VS
N2
N1
VS
R
C
·
S
VO
–
Lm
R
C
VO –
iC1 +
N2
N1
D
(a)
D
S
·
+ vS –
iS
(a)
VS
+
+ vC1–
C
·
R
VO
IL1 0 –IL2
t
vC1 –
(b)
FIGURE 13.11 Flyback converter: (a) circuit diagram and (b) circuit with a transformer model showing the magnetizing inductance Lm .
0
t
vS VS
magnetizing inductance current is supplied to the RC load. The dc voltage transfer function of the ﬂyback converter is MV ≡
VO D = VS n(1 − D)
(13.20)
It differs from the buck–boost converter voltage transfer function by the turns ratio factor n. A positive sign has been obtained by an appropriate coupling of the transformer windings. Unlike in transformer buckderived converters, the magnetizing inductance Lm of the ﬂyback transformer is an important design parameter. The value of the magnetizing inductance that determines the boundary between the CCM and DCM is given by Lmb =
n 2 (1 − D)2 R 2f
(13.21)
The value of the ﬁlter capacitance can be calculated using Eq. (13.16).
` 13.6 Cuk Converter ` The circuit of the Cuk converter is It consists of dc input voltage source controllable switch S, energy transfer ﬁlter inductor L2 , ﬁlter capacitor C,
0
t
iS
shown in Fig. 13.12a. VS , input inductor L1 , capacitor C1 , diode D, and load resistance R.
IL1 + IL2
0
DT
T (b)
2T t
` converter: (a) circuit diagram and (b) waveforms. FIGURE 13.12 Cuk
An important advantage of this topology is a continuous current at both the input and the output of the converter. ` converter include a high number of Disadvantages of the Cuk reactive components and high current stresses on the switch, the diode, and the capacitor C1 . Main waveforms in the converter are presented in Fig. 13.12b. When the switch is on, the diode is off and the capacitor C1 is discharged by the inductor L2 current. With the switch in the off state, the diode conducts currents of the inductors L1 and L2 whereas capacitor C1 is charged by the inductor L1 current. To obtain the dc voltage transfer function of the converter, we shall use the principle that the average current through a capacitor is zero for steadystate operation. Let us assume that inductors L1 and L2 are large enough that their ripple current can be neglected. Capacitor C1 is in steady state if IL2 DT = IL1 (1 − D)T
(13.22)
13
253
DC–DC Converters
For a lossless converter PS = VS IL1 = −VO IL2 = PO
(13.23)
Combining these two equations, the dc voltage transfer ` converter is function of the Cuk MV ≡
VO D =− VS 1−D
(13.24)
This voltage transfer function is the same as that for the buck–boost converter. The boundaries between the CCM and DCM are determined by Lb1 =
(1 − D)R 2Df
(13.25)
losses in the dielectric and physical resistance of leads and connections. Recall Eq. (13.6) which provided a value of the ﬁlter capacitance in a buck converter that limits the peaktopeak output voltage ripple to Vr . The equation was derived under an assumption that the entire triangular ac component of the inductor current ﬂows through a capacitance C. It is, however, closer to reality to maintain that this triangular component ﬂows through a series connection of capacitance C and resistance rC . The peaktopeak ripple voltage is independent of the voltage across the ﬁlter capacitor and is determined only by the ripple voltage of the ESR if the following condition is satisﬁed, 1 − Dmin Dmax C ≥ Cmin = max , (13.29) 2rC f 2rC f If condition (13.29) is satisﬁed, the peaktopeak ripple voltage of the buck and forward converters is
for L1 and Lb2 =
(1 − D)R 2f
(13.26)
for L2 . ` The output part of the Cuk converter is similar to that of the buck converter. Hence, the expression for the ﬁlter capacitor C is Cmin =
(1 − D)VO 8Vr L2 f 2
(13.27)
The peaktopeak ripple voltage in the capacitor C1 can be estimated as Vr1 =
DVO C1 Rf
(13.28)
` A transformer (isolated) version of the Cuk converter can be obtained by splitting capacitor C1 and inserting a highfrequency transformer between the split capacitors.
13.7 Effects of Parasitics The analysis of converters in Sections 13.2 through 13.6 has been performed under ideal switch, diode, and passive component assumptions. Nonidealities or parasitics of practical devices and components may, however, greatly affect some performance parameters of dc–dc converters. In this section, effects of parasitics on output voltage ripple, efﬁciency, and voltage transfer function of converters will be illustrated. A more realistic model of a capacitor than just a capacitance C, consists of a series connection of capacitance C and resistance rC . The resistance rC is called an equivalent series resistance (ESR) of the capacitor and is due to
Vr = rC iLmax =
rC VO (1 − Dmin ) fL
(13.30)
For push–pull, halfbridge, and fullbridge converters,
C ≥ Cmin
0.5 − Dmin Dmax , = max 2rC f 2rC f
(13.31)
where Dmax ≤ 0.5. If condition (13.31) is met, the peaktopeak ripple voltage Vr of these converters is given by Vr = rC iLmax =
rC VO (0.5 − Dmin ) fL
(13.32)
Waveforms of voltage across the ESR VrC , voltage across the capacitance VC , and total ripple voltage Vr are depicted in Fig. 13.13 for three values of the ﬁlter capacitances. For the case of the top graph in Fig. 13.13, the peaktopeak value of Vr is higher than the peaktopeak value of VrC because C < Cmin . Middle and bottom graphs in Fig. 13.13 show the waveforms for C = Cmin and C > Cmin , respectively. For both these cases, the peaktopeak voltages of Vr and VrC equal to each other. Note that when the resistance rC sets the ripple voltage Vr , the minimum value of inductance L is determined either by the boundary between the CCM and DCM according to Eq. (13.5) (buck and forward converters) or Eq. (13.9) (push–pull, halfbridge, and fullbridge converters), or by the voltage ripple condition (13.30) or (13.32). In buck–boost and boost converters, the peaktopeak capacitor current ICpp is equal to the peaktopeak diode current and is given by ICpp =
IO 1−D
(13.33)
254
D. Czarkowski
Finally, by analogy to Eq. (13.16), when the ESR of the ﬁlter capacitor is taken into account in the boosttype output ﬁlter, the ﬁlter capacitance should be greater than
0.08 ripple voltage (V)
Vr 0.04
VC
VrC
Cmin =
0 –0.04 –0.08 0
0.2
0.4
0.6
0.8
1
ripple voltage (V)
η≡
Vr VC
VrC
PO VO IO = PS V S IS
(13.37)
Efﬁciencies are usually speciﬁed in percent. Let us consider the boot converter as an example. Under low ripple assumption, the boost converter efﬁciency can be estimated as
0 –0.04
η=
–0.08 0
0.2
0.4
0.6
0.8
VC
V rC 0 –0.04 –0.08 0
0.2
0.4
0.6
0.8
1
t/T
FIGURE 13.13 Voltage ripple waveforms VrC , VC , and Vr for a buck converter at VO = 12 V, f = 100 kHz, L = 40 µH, rC = 0.05 , and various values of C: C = 33 µF (top graph), C = Cmin = 65 µF (middle graph), and C = 100 µF (bottom graph).
under condition that the inductor current ripple is much lower than the average value of the inductor current. The peaktopeak voltage across the ESR is VrC = rC ICpp =
rC IO 1−D
(13.34)
Assuming that the total ripple voltage Vr is approximately equal to the sum of the ripple voltages across the ESR and the capacitance, the maximum value of the peaktopeak ripple voltage across the capacitance is VCmax ≈ Vr − VrC
(13.38) where VD is the forward conduction voltage drop of the diode, Co is the output capacitance of the switch, rL is the ESR of the inductor, and rD is the forward on resistance of the diode. The term fCo R in Eq. (13.38) represents switching losses in the converter. Other terms account for conduction losses. Losses in a dc–dc converter also contribute to a decrease in the dc voltage transfer function. The nonideal dc voltage transfer function MVn is a product of the ideal one and the efﬁciency
Vr
0.04
R(1−D)2 R(1−D)2 (1+(VD /VO )+fCo R)+rL +DrS +(1−D)rD +D(1−D)rC
1
0.08 ripple voltage (V)
(13.36)
Parasitic resistances, capacitances, and voltage sources affect also an energy conversion efﬁciency of dc–dc converters. The efﬁciency η is deﬁned as a ratio of output power to the input power
0.08 0.04
DVO VCmax Rf
(13.35)
MVn = ηMV
(13.39)
Sample graphs for the boost converter that correspond to Eqs. (13.38) and (13.39) are presented in Fig. 13.14.
13.8 Synchronous and Bidirectional Converters It can be observed in Eq. (13.38) that the forward voltage of a diode VD contributes to a decrease in efﬁciency. This contribution is especially signiﬁcant in low output voltage power supplies, e.g. 3.3 V power supplies for microprocessors or power supplies for portable telecommunication equipment. Even with a Schottky diode, which has VD in the range of 0.4 V, the power loss in the diode can easily exceed 10% of the total power delivered to the load. To reduce conduction losses in the diode, a low onresistance switch can be added in parallel as shown in Fig. 13.15 for a buck converter. The input switch and the switch parallel to the diode must be
13
255
DC–DC Converters S1
100 Ideal
L +
80
Efficiency (%)
VS
D
S2
R
C
VO
60 −
Nonideal 40
FIGURE 13.15 Synchronous buck converter.
20 +
0
0.2
0.4
0.6
0.8
1.0
D (a)
·
N1
VS S1
N2
·
C
R
VO
S2 −
D1
10
D2
FIGURE 13.16 Bidirectional ﬂyback converter.
MV, MVn
8
Ideal
6
4
2 Nonideal
0
0.2
0.4
0.6
0.8
1.0
D (b)
FIGURE 13.14 Effects of parasitics on characteristics of a boost converter: (a) efﬁciency and (b) dc voltage transfer function.
turned on and off alternately. The arrangement of Fig. 13.15 is called a synchronous converter or a synchronous rectiﬁer. Modern lowvoltage MOSFETs have on resistances of only several milliohms. Hence, a synchronous converter may exhibit higher efﬁciency than a conventional one at output currents as large as tens of amperes. The efﬁciency is increased at an expense of more complicated driving circuitry for the switches. In particular, a special can must be exercised to avoid having both switches on at the same time as this would short the input voltage source. Since power semiconductor devices
usually have longer turnoff times than turnon times, a dead time (sometimes called a blanking time) must be introduced in PWM driving signals. The parallel combination of a controllable switch and a diode is also used in converters which allow for a current ﬂow in both directions: from the input source to the load and from the load back to the input source. Such converters are called bidirectional power ﬂow or simply bidirectional converters. As an example, a ﬂyback bidirectional converter is shown in Fig. 13.16. It contains unipolar voltage and bidirectional current switch–diode combinations at both primary and secondary of the ﬂyback transformer. When the primary switch and secondary diode operate, the current ﬂows from the input source to the load. The converter current can also ﬂow from the output to the input through the secondary switch and primary diode. Bidirectional arrangements can be made for buck and boost converters. A bidirectional buck converter operates as a boost converter when the current ﬂow is from the output to the input. A bidirectional boost converter operates as a buck converter with a reversed current ﬂow. If for any reason (for instance to avoid the DCM) the controllable switches are driven at the same time, they must be driven alternately with a sufﬁcient dead time to avoid a shotthrough current.
13.9 Control Principles A dc–dc converter must provide a regulated dc output voltage under varying load and input voltage conditions.
256
D. Czarkowski
The converter component values are also changing with time, temperature, pressure, etc. Hence, the control of the output voltage should be performed in a closedloop manner using principles of negative feedback. Two most common closedloop control methods for PWM dc–dc converters, namely, the voltagemode control and the currentmode control, are presented schematically in Fig. 13.17. In the voltagemode control scheme shown in Fig. 13.17a, the converter output voltage is sensed and subtracted from an external reference voltage in an error ampliﬁer. The error ampliﬁer produces a control voltage that is compared to a constantamplitude sawtooth waveform. The comparator produces a PWM signal which is fed to drivers of controllable switches in the dc–dc converter. The duty ratio of the PWM signal depends on the value of the control voltage. The frequency of the PWM signal is the same as the frequency of the sawtooth waveform. An important advantage of the voltagemode control is its simple hardware implementation and ﬂexibility.
The error ampliﬁer in Fig. 13.17a reacts fast to changes in the converter output voltage. Thus, the voltagemode control provides good load regulation, that is, regulation against variations in the load. Line regulation (regulation against variations in the input voltage) is, however, delayed because changes in the input voltage must ﬁrst manifest themselves in the converter output before they can be corrected. To alleviate this problem, the voltagemode control scheme is sometimes augmented by socalled voltage feedforward path. The feedforward path affects directly the PWM duty ratio according to variations in the input voltage. As will be explained below, the input voltage feedforward is an inherent feature of currentmode control schemes. The currentmode control scheme is presented in Fig. 13.17b. An additional inner control loop feeds back an inductor current signal. This current signal, converted into its voltage analog, is compared to the control voltage. This modiﬁcation of replacing the sawtooth wavefrom of the voltagemode control scheme by a converter current signal
Voltage reference
Error Amplifier
Control voltage
Comparator
PWM signal
dcdc Converter
Sawtooth waveform Output voltage (a)
Voltage reference
Error Amplifier
Control voltage
Comparator PWM signal And Latch
dcdc Converter
Switch or inductor current
Output voltage (b)
FIGURE 13.17 Main control schemes for dc–dc converters: (a) voltagemode control and (b) currentmode control.
13
257
DC–DC Converters
signiﬁcantly alters the dynamic behavior of the converter. The converter takes on some characteristics of a current source. The output current in PWM dc–dc converters is either equal to the average value of the output inductor current ` (buckderived and Cuk converters) or is a product of an average inductor current and a function of the duty ratio. In practical implementations of the currentmode control, it is feasible to sense the peak inductor current instead of the average value. Since the peak inductor current is equal to the peak switch current, the latter can be used in the inner loop which often simpliﬁes the current sensor. Note that the peak inductor (switch) current is proportional to the input voltage. Hence, the inner loop of the currentmode control naturally accomplishes the input voltage feedforward technique. Among several currentmode control versions, the most popular is the constantfrequency one which requires a clock signal. Advantages of the currentmode control include: input voltage feedforward, limit on the peak switch current, equal current sharing in modular converters, and reduction in the converter dynamic order. The main disadvantage of the currentmode control is its complicated hardware which includes a need to compensate the control voltage by ramp signals (to avoid converter instability). Among other control methods of dc–dc converters, a hysteretic (or bangbang) control is very simple for hardware implementation. The hysteretic control results, however, in variable frequency operation of semiconductor switches. Generally, a constant switching frequency is preferred in power electronic circuits for easier elimination of electromagnetic interference and better utilization of magnetic components. Application speciﬁc integrated circuits (ASICs) are commercially available that contain main elements of voltageor currentmode control schemes. On a single 14 or 16pin chip, there is error ampliﬁer, comparator, sawtooth generator or sensed current input, latch, and PWM drivers. The switching frequency is usually set by an external RC network and can be varied from tens of kilohertz to a few megahertz. The controller has an oscillator output for synchronization with other converters in modular power supply systems. A constant voltage reference is generated on the chip as well. Additionally, the ASIC controller may be equipped in various diagnostic and protection features: current limiting, overvoltage and undervoltage protection, soft start, dead time in case of multiple PWM outputs, and duty ratio limiting. In several dc–dc converter topologies, e.g. buck and buck–boost, neither control terminal of semiconductor switches is grounded (socalled highside switches). The ASIC controllers are usually designed for a particular topology and their PWM drivers may be able to drive highside switches in low voltage applications. In high voltage applications, external PWM drivers must be used. External PWM drivers are also used for switches with high input capacitances. To take a full advantage of the input– output isolation in transformer versions of dc–dc converters,
such an isolation must be also provided in the control loop. Signal transformers or optocouplers are used for isolating feedback signals. Dynamic characteristic of closedloop dc–dc converters must fulﬁll certain requirements. To simply analysis, these requirements are usually translated into desired properties of the open loop. The open loop should provide a sufﬁcient (typically, at least 45◦ ) phase margin for stability, high bandwidth (about onetenth of the switching frequency) for good transient response, and high gain (several tens of decibels) at low frequencies for small steadystate error. The open loop dynamic characteristics are shaped by compensating networks of passive components around the error ampliﬁer. Second or third order RC networks are commonly used. Since the converter itself is a part of the control loop, the design of compensating networks requires a knowledge of smallsignal characteristics of the converter. There are several methods of smallsignal characterization of PWM dc–dc converters. The most popular methods provide average models of converters under high switching frequency assumption. The averaged models are then linearized at an operating point to obtain smallsignal transfer functions. Among analytical averaging methods, statespace averaging has been popular since late 1970s. Circuitbased averaging is usually performed using PWM switch or direct replacement of semiconductor switches by controlled current and voltage sources. All these methods can take into account converter parasitics. The most important smallsignal characteristic is the controltooutput transfer function Tp . Other converter characteristics that are investigated include the inputtooutput (or linetooutput) voltage transfer function, also called the openloop dynamic line regulation or the audio susceptibility, which describes the input–output disturbance transmission; the openloop input impedance; and the openloop dynamic load regulation. Buckderived, boost, and buck–boost con` verters are second order dynamic systems; the Cuk converter is a fourthorder system. Characteristics of buck and buckderived converters are similar to each other. Another group of converters with similar smallsignal characteristics is formed by boost, buck–boost, and ﬂyback converters. Among parasitic components, the ESR of the ﬁlter capacitor rC introduces additional dynamic terms into transfer functions. Other parasitic resistances usually modify slightly the effective value of the load resistance. Sample characteristics below are given for nonzero rC , neglecting other parasitics. The controltooutput transfer function of the forward converter is Tp (s) ≡
vo (s) VI RrC vs (s)=0 = d(s) nL(R + rC ) ×
s2
s + (1/CrC ) + s(CRrC + L/LC(R + rC )) + R/(LC(R + rC )) (13.40)
258
D. Czarkowski
It can be seen that this transfer function has two poles and one zero. The zero is due to the ﬁlter capacitor ESR. Buckderived converters can be easily compensated for stability with secondorder controllers. The controltooutput transfer function of the boost converter is given by V O rC (1−D)(R +rC ) s +(1/CrC ) s −((1−D)2 R)/L × 2 s +s ((1−D)2 CRrC +L)/(LC(R +rC )) + ((1−D)2 R)/(LC(R +rC ))
Tp (s) = −
(13.41) The zero − (1 − D)2 R/L is located in the right half of the splane. Therefore, the boost converter (as well as buck–boost and ﬂyback converters) is a nonminimum phase system. Nonminimum phase dc–dc converters are typically compensated with thirdorder controllers. Stepbystep procedures for a design of compensating networks are usually given by manufacturers of ASIC controllers in application notes. The ﬁnal word of this section is on the behavior of dc–dc converters in distributed power supply systems. An important feature of closedloop regulated dc–dc converters is that they exhibit a negative input resistance. As the load voltage is kept constant by the controller, the output power changes with the load. With slow load changes, an increase (decrease) in the input voltage results in a decrease (increase) in the input power. This negative resistance property must be carefully examined during the system design to avoid resonances.
13.10 Applications of DC–DC Converters Stepdown choppers ﬁnd most of their applications in highperformance dc drive systems, e.g. electric traction, electric vehicles, and machine tools. The dc motors with their winding inductances and mechanical inertia act as ﬁlters resulting in highquality armature currents. The average output voltage of stepdown choppers is a linear function of the switch duty ratio. Stepup choppers are used primarily in radar and ignition systems. The dc choppers can be modiﬁed for twoquadrant and fourquadrant operation. Twoquadrant choppers may be a part of autonomous power supply system that contain battery packs and such renewable dc sources as photovoltaic arrays, fuel cells, or wind turbines. Fourquadrant choppers are applied in drives in which regenerative breaking of dc motors is desired, e.g. transportation systems with frequent stops. The dc choppers with inductive outputs serve as inputs to currentdriven inverters. An addition of ﬁltering reactive components to dc choppers results in PWM dc–dc converters. The dc–dc converters can be viewed as dc transformers that deliver to the load as
dc voltage or current at a different level than the input source. This dc transformation is performed by electronic switching means, not by electromagnetic means like in conventional transformers. Output voltages of dc–dc converters range from a volt for special VLSI circuits to tens of kilovolts in Xray lamps. The most common output voltages are: 3.3 V for modern microprocessors, 5 and 12 V for logic circuits, 48 V for telecommunication equipment, and 270 V for main dc bus on airplanes. Typical input voltages include 48 V, 170 V (the peak value of a 120 V rms line), and 270 V. Selection of a topology of dc–dc converters is determined not only by input/output voltages, which can be additionally adjusted with the turns ratio in isolated converters, but also by power levels, voltage and current stresses of semiconductor switches, and utilization of magnetic components. The low partcount ﬂyback converter is popular in low power applications (up to 200 W). Its main deﬁciencies are the large size of the ﬂyback transformer core and high voltage stress on the semiconductor switch. The forward converter is also a single switch converter. Since its core size requirements are smaller, it is popular in low/medium (up to several hundreds of watts) power applications. Disadvantages of the forward converter are in a need for demagnetizing winding and in a high voltage stress on the semiconductor switch. The push–pull converter is also used at medium power levels. Due to bidirectional excitation, the transformer size is small. An advantage of the push–pull converter is also a possibility to refer driving terminals of both switches to the ground which greatly simpliﬁes the control circuitry. A disadvantage of the push–pull converter is a potential core saturation in a case of asymmetry. The halfbridge converter has similar range of applications as the push–pull converter. There is no danger of transformer saturation in the halfbridge converter. It requires, however, two additional input capacitors to split in half the input dc source. The fullbridge converter is used at high (several kilowatts) power and voltage levels. The voltage stress on power switches is limited to the input voltage source value. A disadvantage of the fullbridge converter is a high number of semiconductor devices. The dc–dc converters are building blocks of distributed power supply systems in which a common dc bus voltage is converted to various other voltage according to requirements of particular loads. Such distributed dc systems are common in space stations, ships and airplanes, as well as in computer and telecommunication equipment. It is expected that modern portable wireless communication and signal processing systems will use variable supply voltages to minimize power consumption and extend battery life. Low output voltage converters in these applications utilize the synchronous rectiﬁcation arrangement. Another big area of dc–dc converter applications is related to the utility ac grid. For critical loads, if the utility grid fails, there must be a backup source of energy, e.g. a battery pack. This need for continuous power delivery gave rise to various
13
259
DC–DC Converters
types of uninterruptible power supplies (UPSs). The dc–dc converters are used in UPSs to adjust the level of a rectiﬁed grid voltage to that of the backup source. Since during normal operation, the energy ﬂows from the grid to the backup source and during emergency conditions the backup source must supply the load, bidirectional dc–dc converters are often used. The dc–dc converters are also used in dedicated battery chargers. Power electronic loads, especially those with frontend rectiﬁers, pollute the ac grid with odd harmonics. The dc–dc converters are used as intermediate stages, just after a rectiﬁer and before the loadsupplying dc–dc converter, for shaping the input ac current to improve power factor and decrease the harmonic content. The boost converter is especially popular in such power factor correction (PFC) applications. Another utility grid related application of dc–dc converters is in interfaces between ac networks and dc renewable energy sources such as fuel cells and photovoltaic arrays. In isolated dc–dc converters, multiple outputs are possible with additional secondary windings of transformers. Only one output is regulated with a feedback loop. Other outputs depend on the duty ratio of the regulated one and on their loads. A multipleoutput dc–dc converter is a convenient solution in application where there is a need for one closely
regulated output voltage and for one or more noncritical other output voltage levels.
Further Reading 1. R. P. Severns and G. Bloom, Modern DCtoDC Switchmode Power Converter Circuits, New York: Van Nostrand Reinhold Company, 1985. 2. D. W. Hart, Introduction to Power Electronics, Englewood Cliffs, NJ: Prentice Hall, 1997. 3. P. T. Krein, Elements of Power Electronics, New York: Oxford University Press, 1998. 4. A. I. Pressman, Switching Power Supply Design, 2nd Ed., New York: McGrawHill, 1998. 5. A. M. Trzynadlowski, Introduction to Modern Power Electronics, New York: Wiley Interscience, 1998. 6. R. Erickson and D. Maksimovic, Fundamentals of Power Electronics, 2nd Ed., Norwell, MA: Kluwer Academic, 2001. 7. M. H. Rashid, Power Electronics Circuits, Devices, and Applications 3rd Ed., Upper Saddle River, NJ: Pearson Prentice Hall, 2003. 8. N. Mohan, T. M. Undeland, and W. P. Robbins, Power Electronics: Converters, Applications and Design, 3rd Ed., New York: John Wiley & Sons, 2003.
14 DC/DC Conversion Technique and Twelve Series Luoconverters Fang Lin Luo, Ph.D. School of EEE, Block S1, Nanyang Technological University, Nanyang Avenue, Singapore
Hong Ye, Ph.D. School of Biological Sciences, Block SBS, Nanyang Technological University, Nanyang Avenue, Singapore
14.1 Introduction...................................................................................................... 262 14.2 Fundamental, Developed, Transformertype, and Selflift Converters........................... 263 14.2.1 Fundamental Topologies • 14.2.2 Developed Topologies • 14.2.3 Transformertype Topologies • 14.2.4 Seven (7) Selflift DC/DC Converters • 14.2.5 Tapped Inductor (Watkins–Johnson) Converters
14.3 Voltagelift Luoconverters................................................................................... 271 14.3.1 Positive Output Luoconverters • 14.3.2 Simpliﬁed Positive Output (S P/O) Luoconverters • 14.3.3 Negative Output Luoconverters
14.4 Double Output Luoconverters ............................................................................. 284 14.5 Superlift Luoconverters ..................................................................................... 288 14.5.1 P/O Superlift Luoconverters • 14.5.2 N/O Superlift Luoconverters • 14.5.3 P/O Cascade Boostconverters • 14.5.4 N/O Cascade Boostconverters
14.6 Ultralift Luoconverters...................................................................................... 299 14.6.1 Continuous Conduction Mode • 14.6.2 Discontinuous Conduction Mode
14.7 Multiplequadrant Operating Luoconverters .......................................................... 301 14.7.1 Forward Twoquadrant DC/DC Luoconverter • 14.7.2 Twoquadrant DC/DC Luoconverter in Reverse Operation • 14.7.3 Fourquadrant DC/DC Luoconverter
14.8 Switchedcapacitor Multiquadrant Luoconverters .................................................. 306 14.8.1 Twoquadrant Switchedcapacitor DC/DC Luoconverter • 14.8.2 Fourquadrant Switchedcapacitor DC/DC Luoconverter
14.9 Multiplelift Push–Pull Switchedcapacitor Luoconverters. ....................................... 315 14.9.1 P/O Multiplelift Push–Pull Switchedcapacitor DC/DC Luoconverter • 14.9.2 N/O Multiplelift Push–Pull Switchedcapacitor DC/DC Luoconverter
14.10 Switchedinductor Multiquadrant Operation Luoconverters .................................... 318 14.10.1 Twoquadrant Switchedinductor DC/DC Luoconverter in Forward Operation • 14.10.2 Twoquadrant Switchedinductor DC/DC Luoconverter in Reverse Operation • 14.10.3 Fourquadrant Switchedinductor DC/DC Luoconverter
14.11 Multiquadrant ZCS Quasiresonant Luoconverters ................................................ 323 14.11.1 Twoquadrant ZCS Quasiresonant Luoconverter in Forward Operation • 14.11.2 Twoquadrant ZCS Quasiresonant LuoConverter in Reverse Operation • 14.11.3 Fourquadrant ZCS Quasiresonant Luoconverter
14.12 Multiquadrant ZVS Quasiresonant Luoconverters ................................................ 327 14.12.1 Twoquadrant ZVS Quasiresonant DC/DC Luoconverter in Forward Operation • 14.12.2 Twoquadrant ZVS Quasiresonant DC/DC Luoconverter in Reverse Operation • 14.12.3 Fourquadrant ZVS Quasiresonant DC/DC Luoconverter
14.13 Synchronousrectiﬁer DC/DC Luoconverters ......................................................... 331 14.13.1 Flat Transformer Synchronousrectiﬁer DC/DC Luoconverter • 14.13.2 Double Current SR DC/DC Luoconverter with Active Clamp Circuit • 14.13.3 Zerocurrentswitching Synchronousrectiﬁer DC/DC Luoconverter • 14.13.4 Zerovoltageswitching Synchronousrectiﬁer DC/DC Luoconverter
14.14 Multipleelement Resonant Power Converters ......................................................... 335 14.14.1 Two Energystorage Elements Resonant Power Converters • 14.14.2 Three Energystorage Elements Resonant Power Converters • 14.14.3 Four Energystorage Elements Resonant Power Converters • 14.14.4 Bipolar Current and Voltage Sources
14.15 Gate Control Luoresonator ................................................................................. 342 14.16 Applications ...................................................................................................... 343 14.16.1 5000 V Insulation Test Bench • 14.16.2 MIT 42/14 V–3 KW DC/DC Converter • 14.16.3 IBM 1.8 V/200 A Power Supply
14.17 Energy Factor and Mathematical Modeling for Power DC/DC Converters .................... 345 14.17.1 Pumping Energy (PE) • 14.17.2 Stored Energy (SE) • 14.17.3 Energy Factor (EF ) • 14.17.4 Time Constant τ and Damping Time Constant τd • 14.17.5 Mathematical Modeling for Power DC/DC Converters • 14.17.6 Buck Converter with Small Energy Losses (rL = 1.5 ) • 14.17.7 A Superlift Luoconverter in CCM
Further Reading ................................................................................................. 350
Copyright © 2007, 2001, Elsevier Inc. All rights reserved.
261
262
14.1 Introduction DC/DC converters are widely used in industrial applications and computer hardware circuits. DC/DC conversion technique has been developed very quickly. Since 1920s there have been more than 500 DC/DC converters’ topologies developed. Professor Luo and Dr. Ye have systematically sorted them in six generations in 2001. They are the ﬁrstgeneration (classical) converters, secondgeneration (multiquadrant) converters, thirdgeneration (switchedcomponent) converters, fourthgeneration (softswitching) converters, ﬁfthgeneration (synchronousrectiﬁer) converters and sixthgeneration (multielement resonant power) converters. The ﬁrstgeneration converters perform in a single quadrant mode with low power range (up to around 100 W), such as buck converter, boost converter and buck–boost converter. Because of the effects of parasitic elements, the output voltage and power transfer efﬁciency of all these converters are restricted. The voltagelift (VL) technique is a popular method that is widely applied in electronic circuit design. Applying this technique effectively overcomes the effects of parasitic elements and greatly increases the output voltage. Therefore, these DC/DC converters can convert the source voltage into a higher output voltage with high power efﬁciency, high power density, and a simple structure. The VL converters have high voltage transfer gains, which increase in arithmetical series stagebystage. Superlift (SL) technique is more powerful to increase the converters voltage transfer gains in geometric series stagebystage. Even higher, ultralift (UL) technique is most powerful to increase the converters voltage transfer gain. The secondgeneration converters perform in two or fourquadrant operation with medium output power range (say hundreds watts or higher). Because of high power conversion, these converters are usually applied in industrial applications with high power transmission. For example, DC motor drives with multiquadrant operation. Since most of secondgeneration converters are still made of capacitors and inductors, they are large. The thirdgeneration converters are called switchedcomponent DC/DC converters, and made of either inductor or capacitors, which are socalled switchedinductor and switchedcapacitors. They usually perform in two or fourquadrant operation with high output power range (say thousands watts). Since they are made of only inductor or capacitors, they are small. Switchedcapacitor (SC) DC/DC converters are made of only switchedcapacitors. Since switchedcapacitors can be integrated into power semiconductor integrated circuits (IC) chips, they have limited size and work in high switching frequency. They have been successfully employed in the inductorless DC/DC converters and opened the way to build the converters with high power density. Therefore, they have
F. L. Luo and H. Ye
drawn much attention from the research workers and manufacturers. However, most of these converters in the literature perform singlequadrant operation. Some of them work in the push–pull status. In addition, their control circuit and topologies are very complex, especially, for the large difference between input and output voltages. Switchedinductor (SI) DC/DC converters are made of only inductor, and have been derived from fourquadrant choppers. They usually perform multiquadrant operation with very simple structure. The signiﬁcant advantage of these converters is its simplicity and high power density. No matter how large the difference between the input and output voltages, only one inductor is required for each SI DC/DC converter. Therefore, they are widely required for industrial applications. The fourthgeneration converters are called softswitching converters. Softswitching technique involves many methods implementing resonance characteristics. Popular method is resonantswitching. There are three main groups: zerocurrentswitching (ZCS), zerovoltageswitching (ZVS), and zerotransition (ZT) converters. They usually perform in single quadrant operation in the literature. We have developed this technique in two and fourquadrant operation with high output power range (say thousands watts). Multiquadrant ZCS/ZVS/ZT converters implement ZCS/ ZVS technique in fourquadrant operation. Since switches turn on and off at the moment that the current/voltage is equal to zero, the power losses during switching on and off become zero. Consequently, these converters have high power density and transfer efﬁciency. Usually, the repeating frequency is not very high and the converters work in a monoresonance frequency, the components of higher order harmonics is very low. Using fast fourier transform (FFT) analysis, we obtain that the total harmonic distortion (THD) is very small. Therefore, the electromagnetic interference (EMI) is weaker, electromagnetic sensitivity (EMS) and electromagnetic compatibility (EMC) are reasonable. The ﬁfthgeneration converters are called synchronous rectiﬁer (SR) DC/DC Converters. Corresponding to the development of the microelectronics and computer science, the power supplies with low output voltage (5 V, 3.3 V, and 1.8 ∼ 1.5 V) and strong output current (30 A, 50 A, 100 A up to 200 A) are widely required in industrial applications and computer peripheral equipment. Traditional diode bridge rectiﬁers are not available for this requirement. Many prototypes of SR DC/DC converters with softswitching technique have been developed. The SR DC/DC converters possess the technical feathers with very low voltage and strong current and high power transfer efﬁciency η (90%, 92% up to 95%) and high power density (22–25 W/in3 ). The sixthgeneration converters are called multielement resonant power converters (RPCs). There are eight topologies of 2E RPC, 38 topologies of 3E RPC, and 98 topologies of 4E RPC. The RPCs have very high current transfer gain, purely harmonic waveform, low power losses and EMI since
14
263
DC/DC Conversion Technique and 12 Series Luoconverters
they are working in resonant operation. Usually, the sixthgeneration RPCs used in large power industrial applications with high output power range (say thousands watts). The DC/DC converter family tree is shown in Fig. 14.1. Professor F. L. Luo and Dr. H. Ye have devoted in the subject area of DC/DC conversion technique for a long time and harvested outstanding achievements. They have created twelve (12) series converters namely Luoconverters and more knowledge which are listed below: Positive output Luoconverters; Negative output Luoconverters; Double output Luoconverters; Positive/Negative output superlift Luoconverters; Ultralift Luoconverter; Multiplequadrant Luoconverters; Switched capacitor multiquadrant Luoconverters; Multiplelift pushpull switchedcapacitor Luoconverters; Switchedinductor multiquadrant Luoconverters; Multiquadrant ZCS quasiresonant Luoconverters; Multiquadrant ZVS quasiresonant Luoconverters; Synchronousrectiﬁer DC/DC Luoconverters; Multielement resonant power converters; Energy factor and mathematical modeling for power DC/DC converters.
All of their research achievements have been published in the international topjournals and conferences. Many experts, including Prof. Rashid of West Florida University, Prof. Kassakian of MIT, and Prof. Rahman of Memorial University of Newfoundland are very interested in their work, and acknowledged their outstanding achievements. In this handbook, we only show the circuit diagram and list a few parameters of each converter for readers, such as the output voltage and current, voltage transfer gain and output voltage variation ratio, and the discontinuous condition and output voltage. After a well discussion of steadystate operation, we prepare one section to investigate the dynamic transient process of DC/DC converters. Energy storage in DC/DC converters have been paid attention long time ago, but it was not well investigated and deﬁned. Professor Fang Lin Luo and Dr. Hong Ye have theoretically deﬁned it and introduced new parameters: energy factor (EF) and other variables. They have also fundamentally established the mathematical modeling and discussed the characteristics of all power DC/DC converters. They have successfully solved the traditional problems. In this chapter, the input voltage is VI or V1 and load voltage is VO or V2 . Pulse width modulated (PWM) pulse train has repeating frequency f, the repeating period is T = 1/f . Conduction duty is k, the switchingon period is kT, and switchingoff period is (1 − k)T. All average values are in capital letter, and instantaneous values in small letter, e.g. V1 and v1 (t) or v1 . The variation ratio of the freewheeling diode’s
current is ζ. Voltage transfer gain is M and power transfer efﬁciency is η.
14.2 Fundamental, Developed, Transformertype, and Selflift Converters The ﬁrstgeneration converters are called classical converters which perform in a singlequadrant mode and in low. Historically, the development of the ﬁrst generation converters covers very long time. Many prototypes of these converters have been created. We can sort them in six categories: • •
•
•
•
•
Fundamental topologies: buck converter, boost converter, and buck–boost converter. Developed topologies: positive output Luoconverter, negative output Luoconverter, double output Luoconverter, Cúkconverter, and singleended primary inductance converter (SEPIC). Transformertype topologies: forward converter, push– pull converter, ﬂyback converter, halfbridge converter, bridge converter, and ZETA. Voltagelift topologies: selflift converters, positive output Luoconverters, negative output Luoconverters, double output Luoconverters. Superlift topologies: positive/negative output superlift Luoconverters, positive/negative output cascade boostconverters. Ultralift topologies: ultralift Luoconverter.
14.2.1 Fundamental Topologies Buck converter is a stepdown converter, which is shown in Fig. 14.2a, the equivalent circuits during switchon and off periods are shown in Figs. 14.2b and c. Its output voltage and output current are V2 = kV1
(14.1)
1 I1 k
(14.2)
and I2 =
This converter may work in discontinuous mode if the frequency f is small, conduction duty k is small, inductance L is small, and load current is high. Boost converter is a stepup converter, which is shown in Fig. 14.3a, the equivalent circuits during switchon and off periods are shown in Figs. 14.3b and c. Its output voltage and current are V2 =
1 V1 1−k
(14.3)
264
F. L. Luo and H. Ye Buck Converter Boost Converter
Fundamental Circuits
BuckBoost Converter
Positive Output LuoConverter Negative Output LuoConverter
Developed
Double Output LuoConverter
1G Forward Converter
Classical Converters
FlyBack Converter
′ CukConverter SEPIC TappedInductor Converters
PushPull Converter Transformer
HalfBridge Converter
7 SelfLift Converter
Bridge Converter
Positive Output LuoConverter
ZETA Converter
Negative Output LuoConverter Modified P/O LuoConverter
Voltage Lift
Double Output LuoConverter Positive Output SuperLift LuoConverter Negative Output SuperLift LuoConverter
SuperLift
Positive Output Cascade Boost Converter Negative Output Cascade Boost Converter UltraLift LuoConverter
DC/DC Converters
2G MultiQuadrant Converters
Transformertype Converters Developed
MultiQuadrant LuoConverter Two Quadrants SC LuoConverter
SwitchedCapacitor Converter 3G SwitchedComponent Converters
Four Quadrants SC LuoConverter
MultiLift
P/O MultiLift PushPull LuoConverter
N/O MultiLift PushPull LuoConverter Transformertype Converters SwitchedInductor Converter Four Quadrants SI LuoConverter
4G SoftSwitching Converters
5G Synchronous Rectifier Converters 6G MultiElements Resonant Power Converters
ZCSQRC  Four Quadrants ZeroCurrent Switching LuoConverter ZVSQRC  Four Quadrants ZeroVoltage Switching LuoConverter ZTC  Four Quadrants ZeroTransition LuoConverter FlatTransformer Synchronous Rectifier Converter Synchronous Rectifier Converter with Active Clamp Circuit Double Current Synchronous Rectifier Converter ZCS Synchronous Rectifier Converter ZVS Synchronous Rectifier Converter 2Elements 3Elements 4Elements
PCLL Current Source Resonant Inverter Double GammaCL Current Source Resonant Inverter Reverse Double GammaCL Resonant Power Converter
FIGURE 14.1 DC/DC converter family tree.
14
265
DC/DC Conversion Technique and 12 Series Luoconverters i1
+ V1
i2
L
S − D
−
iL
VD +
+
+ VC
− C
R iC
V2 −
(a) i1 + V1
+ VC − C
iL
−
i2
L
i2
L
+
iL
V2 −
R iC
+
+ VC
R
− C
(b)
iC
V2 −
(c)
FIGURE 14.2 Buck converter: (a) circuit diagram; (b) switchon equivalent circuit; and (c) switchoff equivalent circuit.
i1
L
VD
+
+ VC − C
iL
V1
i2
D
S
−
+ V2
R
−
iC
(a) i1 + V1
i2
L + VC − C
iL
−
i1 + R
iC
V2 −
+ V1 −
i2
L
iL
+
+ VC − C
R iC
V2 −
(c)
(b)
FIGURE 14.3 Boost converter: (a) circuit diagram; (b) switchon equivalent circuit; and (c) switchoff equivalent circuit.
and
voltage and current are I2 = (1 − k)I1
(14.4)
The output voltage is higher than the input voltage. This converter may work in discontinuous mode if the frequency f is small, conduction duty k is small, inductance L is small, and load current is high. Buck–boost converter is a step–down/up converter, which is shown in Fig. 14.4a, the equivalent circuits during switchon and off periods are shown in Figs. 14.4b and c. Its output
V2 =
k V1 1−k
(14.5)
I2 =
1−k I1 k
(14.6)
and
When k is greater than 0.5, the output voltage can be higher than the input voltage. This converter may work in
266
F. L. Luo and H. Ye i1
VD
+ V1
i2
D
S
− VC +
L
−
−
C
iL
V2
R
+
iC
(a)
−
−
+ V1
i2
i2
i1
−
iL
L
VC
+ C
R iC
iL
−
− VC
V2
L
+
R
+
iC
C
(b)
V2
+
(c)
FIGURE 14.4 Buckboost converter: (a) circuit diagram; (b) switchon equivalent circuit; and (c) switchoff equivalent circuit.
discontinuous mode if the frequency f is small, conduction duty k is small, inductance L is small, and load current is high.
iI +
14.2.2 Developed Topologies
k V1 1−k
I2 =
1−k I1 k
(14.8)
Positive output (P/O) Luoconverter is a stepdown/up converter, and is shown in Fig. 14.5. This converter may work in discontinuous mode if the frequency f is small, k is small, and inductance L is small.
− VC +
i1 S
LO
+
L
D
CO
FIGURE 14.5 Positive output Luoconverter.
V2 R
−
−
LO R
vC L
+
v2 CO
C
+
Negative output (N/O) Luoconverter is shown in Fig. 14.6. This converter may work in discontinuous mode if the frequency f is small, k is small, inductance L is small, and load current is high. Double output Luoconverter is a double output stepdown/up converter, which is derived from P/O Luoconverter and N/O Luoconverter. It has two conversion paths and two output voltages VO+ and VO− . It is shown in Fig. 14.7. If the components are carefully selected the output voltages and currents (concentrate the absolute value) obtained are V2+ = V2−  =
iL
−
−
i2
FIGURE 14.6 Negative output Luoconverter.
i2
C
+ V1
iLo
iL
−
(14.7)
and
D
S
VI
For convenient applications, all developed converters have output voltage and current as V2 =
iLO
and I2+ =
1−k + I k 1
and
k V1 1−k
I2− =
1−k − I k 1
(14.9)
(14.10)
When k is greater than 0.5, the output voltage can be higher than the input voltage. This converter may work in discontinuous mode if the frequency f is small, k is small, inductance L is small, and load current is high.
14
267
DC/DC Conversion Technique and 12 Series Luoconverters i2+
i1 Di
S
+
C1
LO
+
V1 L1
−
D1
V2+
CO
RO
−
− V2− L11
C11
C1O
R1O + i2−
Di1
D11
L1O
FIGURE 14.7 Double output Luoconverter.
i1
+ L
+
VC
iLO
−
i2
R
V1
S
D
−
D2
CO
+ V1
L
vC
+
−
C S
iL1
T1
ratio N, the positive or negative polarity by changing the winding direction, and multiple output voltages by setting multiple secondary windings. Forward converter is a stepup/down converter, which is shown in Fig. 14.10. The transformer turns ratio is N (usually N > 1). If the transformer has never been saturated during operation, it works as a buck converter. The output voltage and current are VO = kNVI
(14.11)
1 II kN
(14.12)
and
R CO
V2 −
−
Control
+
D
L1
Vo −
FIGURE 14.10 Forward converter.
i2
−
C
R
Vin
V2
Cúkconverter is a negative output stepdown/up converter, which is derived from boost and buck converters. It is shown in Fig. 14.8. Singleended primary inductance converter is a positive output stepdown/up converter, which is derived from boost converters. It is shown in Fig. 14.9.
+
+
−
FIGURE 14.8 Cúk converter.
i1
L
D1
+
LO
C
1:N
FIGURE 14.9 SEPIC.
14.2.3 Transformertype Topologies All transformertype converters have transformer(s) to isolate the input and output voltages. Therefore, it is easy to obtain the high or low output voltage by changing the turns
IO =
This converter may work in discontinuous mode if the frequency f is small, conduction duty k is small, inductance L is small, and load current is high. To avoid the saturation of transformer applied in forward converters, a tertiary winding is applied. The corresponding circuit diagram is shown in Fig. 14.11. To obtain multiple output voltages we can set multiple secondary windings. The corresponding circuit diagram is shown in Fig. 14.12.
268
F. L. Luo and H. Ye 1:1:N
D1
C
D2
C
Vo
R
T1 −
D3
1:1:N1 O/P 1 N2 Vin
− Control
T1
FIGURE 14.14 Flyback converter.
FIGURE 14.11 Forward converter with tertiary winding.
+
in ﬂyback operation to obtain high surge voltage induced, then get high output voltage. It works likely in buck–boost operation as a buck–boost converter. Its output voltage and current are
O/P 2
T1
N3
−
VO
R
VI
−
−
+
+
+
+ Vin
D1
1:N
L
VO =
kN VI 1−k
(14.15)
IO =
1−k II kN
(14.16)
O/P 3
and FIGURE 14.12 Forward converter with multiple secondary windings.
1:N + VI
D1
L + V'
T1
+ C
−
−
VO
R −
T2 D2
Halfbridge converter is a stepup converter, which is shown in Fig. 14.15. There are two switches and one double secondary coils transformer required. The transformer turns ratio is N. It works as a halfbridge rectiﬁer (half of V1 inputs to primary winding) plus a buck converter circuit in secondary side. The conduction duty cycle k is set in 0.1 < k < 0.5. Its output voltage and current are
FIGURE 14.13 Push–pull converter.
VO = 2kN
Push–pull converter is a stepup/down converter, which is shown in Fig. 14.13. It is not necessary to set the tertiary winding. The transformer turns ratio is N (usually N > 1). If the transformer has never been saturated during operation, it works as a buck converter with the conduction duty cycle k < 0.5. The output voltage and current are VO = 2kNVI
(14.13)
VI = kNVI 2
(14.17)
1 II kN
(14.18)
and IO =
This converter may work in discontinuous mode if the frequency f is small, conduction duty k is small, inductance L is small, and load current is high.
and 1 IO = II 2kN
1:N
(14.14)
This converter may work in discontinuous mode if the frequency f is small, conduction duty k is small, inductance L is small, and load current is high. Flyback converter is a high stepup converter, which is shown in Fig. 14.14. The transformer turns ratio is N (usually N > 1). It effectively uses the transformer leakage inductance
+
C1
D1
L +
T1 C3
VO −
Vin
−
R
C2
T2
D2
FIGURE 14.15 Halfbridge converter.
14
269
DC/DC Conversion Technique and 12 Series Luoconverters D1
1:N T1
+
L +
T2 C1
VO
R
−
Vin
C
Voltagelift technique is a popular method used in electronic circuit design. Applying this technique can effectively overcome the effect of the parasitic elements, and largely increase the voltage transfer gain. In this section, we introduce seven selflift converters which are working in continuous mode. •
−
T3
•
D2
T4
• •
FIGURE 14.16 Bridge converter.
• •
Bridge converter is a stepup converter, which is shown in Fig. 14.16. There are four switches and one double secondary coils transformer required. The transformer turns ratio is N. It works as a fullbridge rectiﬁer (full V1 inputs to primary winding) plus a buckconverter circuit in secondary side. The conduction duty cycle k is set in 0.1 < k < 0.5. Its output voltage and current are VO = 2kNVI
(14.19)
1 II 2kN
(14.20)
and IO =
IO =
L1 1:N + Vin −
1−k II kN
C1
D
All selflift converters (except enhanced selflift circuit) have the output voltage and current to be 1 VI 1−k
(14.23)
IO = (1 − k)II
(14.24)
VO = and
The voltage transfer gain in continuous mode is
ZETA (zeta) converter is a stepup converter, which is shown in Fig. 14.17. The transformer turns ratio is N. The transformer functions as a inductor (L1 ) plus a buck–boost converter plus a lowpass ﬁlter (L2 –C2 ). Its output voltage and current are k VO = NVI (14.21) 1−k and
•
Positive output (P/O) selflift Luoconverter; Reverse P/O selflift Luoconverter; Negative output (N/O) selflift Luoconverter; Reverse N/O selflift Luoconverter; Selflift Cúkconverter; Selflift SEPIC; Enhanced selflift Luoconverter.
MS =
VO II 1 = = VI IO 1−k
(14.25)
P/O selflift Luoconverter is shown in Fig. 14.18. The variation ratio of the output voltage vO in continuous conduction mode (CCM) is vO /2 1 k = VO 8MS f 2 CO L2
ε=
(14.22)
(14.26)
Reverse P/O selflift Luoconverter is shown in Fig. 14.19. The variation ratio of the output voltage vO in CCM is
L2
C2
R
+ VO −
ε=
vO /2 1 k = 2 VO 16MS f CO L2
(14.27)
S iI
FIGURE 14.17 ZETA (zeta) converter.
−
+
S
Because of the effect of the parasitic elements, the voltage conversion gain is limited. Especially, when the conduction duty k is towards unity, the output voltage is sharply reduced.
iO
LO D R
D1 iL
−
iLO
+
C
VI
14.2.4 Seven (7) Selflift DC/DC Converters
vC
L
+ vC1 −
+ VO
C1
CO
FIGURE 14.18 P/O selflift Luoconverter.
−
270
F. L. Luo and H. Ye iI
+
vC1
S
+
iLO
−
iO
LO
C1
L
−
−
R CO
+ VI
−
D
iO
LO
−
+
R
+ L
vC
−
−
vC1
CO
C1
+
iLO
+
S
−
iO
LO
D
C
VI
−
CO
C
+
+
iL1
D1 −
L1
+
R
vC2
VO C2
CO
−
FIGURE 14.23 Selflift SEPIC.
Selflift SEPIC is shown in Fig. 14.23. The variation ratio of the output voltage vO in CCM is
FIGURE 14.20 N/O selflift Luoconverter.
N/O selflift Luoconverter is shown in Fig. 14.20. The variation ratio of the output voltage vO in CCM is vO /2 k 1 ε= = VO 128 f 3 LO C1 CO R
(14.28a)
Reverse N/O selflift Luoconverter is shown in Fig. 14.21. The variation ratio of the output voltage vO in CCM is ε=
VO
+
D
VO +
D1
L
−
R
vC1 S
iI
vC iL
LO −
FIGURE 14.22 Selflift Cúkconverter.
iLO
C1
D1
iO
+
C
+ vC1 − S
iLO
−
C
−
FIGURE 14.19 Reverse P/O selflift Luoconverter.
iI
vC
L
VI
VO
− vC +
iL
+ +
D1
D
VI
iI
vO /2 1 k = VO 128 f 3 LO C1 CO R
ε=
vO /2 k 1 = VO 128 f 3 LO C1 CO R
(14.28d)
Enhanced selflift Luoconverter is shown in Fig. 14.24. Its output voltage and current are VO =
2−k VI 1−k
(14.29)
IO =
1−k II 2−k
(14.30)
and
(14.28b)
The voltage transfer gain in continuous mode is Selflift Cúkconverter is shown in Fig. 14.22. The variation ratio of the output voltage vO in CCM is ε=
VI −
(14.28c)
− S
vC
iLO
+ D1
C iL
L D
vC1 −
iLO
C1
LO
L
R CO
FIGURE 14.21 Reverse N/O selflift Luoconverter.
(14.31)
iO
D1 +
VI
−
S −
+ R
D +
VO C1
− vC1 +
iO
LO
+
2−k VO II 1 +1= = = VI IO 1−k 1−k
iI
+
iI
+
vO /2 1 k = VO 128 f 3 LO C1 CO R
MS =
vC −
CO C
FIGURE 14.24 Enhanced selflift Luoconverter.
VO −
14
271
DC/DC Conversion Technique and 12 Series Luoconverters
TABLE 14.1
The circuit diagrams of the tapped inductor fundamental converters Standard converter
Buck
S
Switch tap
Diode to tap S
L
S
Rail to tap N2
S
N1
N2 N1 VIN
C
D
VIN
VO
D
N1 C
VIN
VO
D
C
VO
C VO
VIN D
Boost
L VIN
N1
D C
S
VIN
VO
N2
N1 N2
D C
S
VO
D
N2
N2 C
VIN
VO
VIN
D C VO
N1
S S
Buck–Boost
S
S
D
D L
VIN
C
C
VO
VIN
S
N1
S N2
N2 VO
VIN
N1
N1 D C
VO
VIN
N2
C VO D
The variation ratio of the output voltage vO in CCM is as in Eq. (14.26) ε=
a number of uptodate converters. There are three series of Luoconverters introduced in this section: •
vO /2 k 1 = 2 VO 8MS f CO L2
• •
14.2.5 Tapped Inductor (Watkins–Johnson) Converters Tapped inductor (Watkins–Johnson) converters have been derived from fundamental converters, which circuit diagrams are shown in Table 14.1. The voltage transfer gains are shown in Table 14.2. Here the tapped inductor ratio is n = n1/ (n1 + n2).
14.3.1 Positive Output Luoconverters Positive output (P/O) Luoconverters perform the voltage conversion from positive to positive voltages using the voltage lift technique. They work in the ﬁrstquadrant with large voltage ampliﬁcation. Their voltage transfer gains are high. Five circuits are introduced in the literature. They are: • • •
14.3 Voltagelift Luoconverters
•
Voltagelift (VL) technique is very popular for electronic circuit design. Professor Luo and Dr. Ye have successfully applied this technique in the design of DC/DC converters, and created TABLE 14.2 The voltage transfer gains of the tapped inductor fundamental converters Converter
No tap
Switched to tap
Diode to tap
Rail to tap
Buck
k
k n + k(1 − n)
nk 1 + k(n − 1)
k −n k(1 − n)
Boost
1 1−k
n + k(1 − n) n(1 − k)
1 + k(n − 1) 1−k
n−k n(1 − k)
Buck–Boost
k 1−k
k n(1 − k)
nk 1−k
k 1−k
Positive output Luoconverters; Simpliﬁed positive output Luoconverters; Negative output Luoconverters.
•
Elementary circuit; Selflift circuit; Relift circuit; Triplelift circuit; Quadruplelift circuit.
Further lift circuits can be derived from the above circuits. In all P/O LuoConverters, we deﬁne normalized inductance L = L1 L2 /(L1 + L2 ) and normalized impedance zN = R/fL. P/O Luoconverter elementary circuit is shown in Fig. 14.25a. The equivalent circuits during switchon and off periods are shown in Figs. 14.25b and c. Its output voltage and current are VO =
k VI 1−k
IO =
1−k II k
and
272
F. L. Luo and H. Ye iIN
iC iL1
+ Vs − + VL1
VIN
− VC +
C
+ VL2 −
+
L1
L2
iD
Io
iL2
Co R
D
VD
+
iCo
Vo
−
−
− (a)
iIN
iC
VO
iL1
+
+ VL1 −
VIN
+
VL2 L2
+
L1
−
−
VL2
+
−
L2
iL1
iL2
VD
VO
iC
−
iL2 Vo
iD
(b)
(c)
FIGURE 14.25 P/O Luoconverter elementary circuit; (a) circuit diagram; (b) switch on; and (c) switch off.
The voltage transfer gain in continuous mode is ME =
VO II k = = VI IO 1−k
The voltage transfer gain in continuous mode is (14.32)
The variation ratio of the output voltage vO in CCM is ε=
vO /2 1 k = VO 16ME f 2 CO L2
MS =
ε=
vO /2 1 k = 2 VO 16MS f CO L2
with
1 R ≥ 2fL 1−k
√ MS ≤ k
1 VI 1−k
zN 2
R 2 VO = 1 + k (1 − k) VI 2fL
with
√
k
R 1 ≥ 2fL 1−k (14.39)
P/O Luoconverter relift circuit is shown in Fig. 14.27a. The equivalent circuits during switchon and off periods are shown in Figs. 14.27b and c. Its output voltage and current are
and IO = (1 − k)II
(14.38)
The output voltage in DCM is (14.35)
P/O Luoconverter selflift circuit is shown in Fig. 14.26a. The equivalent circuits during switchon and off periods are shown in Figs. 14.26b and c. Its output voltage and current are VO =
(14.37)
This converter may work in discontinuous conduction mode if the frequency f is small, conduction duty k is small, inductance L is small, and load current is high. The condition for DCM is
The output voltage in DCM is R VO = k(1 − k) VI 2fL
(14.36)
The variation ratio of the output voltage vO in CCM is
(14.33)
This converter may work in discontinuous conduction mode if the frequency f is small, conduction duty k is small, inductance L is small, and load current is high. The condition for discontinuous conduction mode (DCM) is zN ME ≤ k (14.34) 2
VO II 1 = = VI IO 1−k
VO =
2 VI 1−k
14
273
DC/DC Conversion Technique and 12 Series Luoconverters iC
+ VL2 −
S + iIN
Vs
−
L2
c D
iD1
iO iCO
iL2
iD +
VIN
R
D1
VO −
CO
iL1
iC1
L1 C1
(a)
iIN
iC
VO
+
VL2
i C − VO +
−
− VD +
+ VIN
iL2
L2
C
L2
C
VL2 −
+
VL1 L1 −
L1
− VD +
VIN
iC1
VIN C1 (b)
(c)
FIGURE 14.26 P/O Luoconverter selflift circuit: (a) circuit diagram; (b) switch on; and (c) switch off.
S iIN
+
V − C +
Vs −
+ VL2 −
iC
L2
c D iD1
iL1
L1
iCO
iD
D2
D1 VIN
iL2
iC1 L3
C1
C2
S1
iL2
+ VO −
R
CO
+ VS1 −
(a) − VO
iIN
VIN
C
+ VL1 −
+
VD
iL1
− VO
− L2
iL2
VO
VIN L1 C1
iL3 (b)
VIN L3 C2
+ L2
C
L3
iL1 VIN L1
−
C1
VO VIN C2
iL3
iL2
(c)
FIGURE 14.27 P/O Luoconverter relift circuit: (a) circuit diagram; (b) switch on; and (c) switch off.
274
F. L. Luo and H. Ye
and
P/O Luoconverter triplelift circuit is shown in Fig. 14.28a. The equivalent circuits during switchon and off periods are shown in Figs. 14.28b and c. Its output voltage and current are
1−k II 2
IO =
The voltage transfer gain in CCM is MR =
VO II 2 = = 1−k VI IO
VO =
3 VI 1−k
IO =
1−k II 3
(14.40) and
The variation ratio of the output voltage vO in CCM is ε=
vO /2 1 k = VO 16MR f 2 CO L2
(14.41)
The voltage transfer gain in CCM is
This converter may work in discontinuous conduction mode if the frequency f is small, conduction duty k is small, inductance L is small, and load current is high. The condition for DCM is MR ≤ kzN (14.42)
MT =
R VO = 2 + k (1 − k) VI 2fL 2
with
√
k
R 2 ≥ fL 1−k (14.43)
S +
Vs
−
−
vO /2 1 k = VO 16MT f 2 CO L2
ε=
iL1
iC
+
+ VL2 −
iL3 C1
L3 iC2
L2
D
D2
L1 iC1
(14.45)
This converter may work in discontinuous conduction mode if the frequency f is small, conduction duty k is small, inductance L is small, and load current is high. The condition for DCM is
c D1
VIN
VC
(14.44)
The variation ratio of the output voltage vO in CCM is
The output voltage in DCM is
VO II 3 = = VI IO 1−k
iL2
D4 iL4 C2 D3 S1
L4 iC3
R C3
+ VO −
CO
+ VS1 −
(a) −
VC
+ VL2 −
+
C1 VIN
iL1
iL3
L1 iC1
L2
iL2
c
iL4
iC2
(b)
C3 L4 iC3
VC
+ VL2 −
+
L2
c
CO
C2 L3
−
R
+ VO −
iL2
iL1
+ L1
iL3 C1
L3
iL4
R
L4
C2
C3
(c)
FIGURE 14.28 P/O Luoconverter triplelift circuit: (a) circuit diagram; (b) switch on; and (c) switch off.
CO
VO −
14
275
DC/DC Conversion Technique and 12 Series Luoconverters
MT ≤
3kzN 2
The variation ratio of the output voltage vO in CCM is
(14.46)
ε=
The output voltage in DCM is R 2 VI with VO = 3 + k (1 − k) 2fL
√
k
1 vO /2 k = 2 VO 16MQ f CO L2
This converter may work in discontinuous conduction mode if the frequency f is small, conduction duty k is small, inductance L is small, and load current is high. The condition for DCM is MQ ≤ 2kzN (14.50)
3R 3 ≥ 2fL 1−k (14.47)
P/O Luoconverter quadruplelift circuit is shown in Fig. 14.29a. The equivalent circuits during switchon and off periods are shown in Figs. 14.29b and c. Its output voltage and current are
The output voltage in DCM is R VO = 4 + k (1 − k) VI 2fL
4 VO = VI 1−k
2
with
√
k
and IO =
M=
VO II 4 = = VI IO 1−k
VO II = ; VI IO
− VC +
Vs
−
L=
L1 L2 ; L1 + L 2
zN =
R ; fL
R=
VO IO
To write common formulas for all circuits parameters, we deﬁne that subscript j = 0 for the elementary circuit, j = 1
(14.48)
S +
4 2R ≥ fL 1−k (14.51)
Summary for all P/O Luoconverters:
1−k II 4
The voltage transfer gain in CCM is MQ =
(14.49)
iC
+ VL2 − L2 i L2
c D
iL1 VIN
D2
D1
VL1
D4
L1
iL3
L3
iL4
L4
iC1
C1
iC2
C2
iC3
D6 R
L5
iL5
−
iC4
C3
+ VO
C4 CO
D3
D5 S1
+ V − S1
(a) − VC + i C c
− VC +
+ VL2 − L2 iL2
VL1 L1
iL3
L3
iL4
L4
iC1
C1
iC2
C2
iC3
(b)
iL5 C3
L5 iC4
L2 iL2
c
iL1 VIN
+ VL2 −
C4 CO
R
iL1 + VO VL1 L1
iL3
−
C1
L3 C2
iL4
L4 C3
iL5
R
L5 C4 CO
(c)
FIGURE 14.29 P/O Luoconverter quadruplelift circuit: (a) circuit diagram; (b) switch on; and (c) switch off.
+ VO −
276
F. L. Luo and H. Ye
for the selflift circuit, j = 2 for the relift circuit, j = 3 for the triplelift circuit, j = 4 for the quadruplelift circuit, and so on. The voltage transfer gain is Mj =
k h(j) [j + h(j)] 1−k
14.3.2 Simpliﬁed Positive Output (S P/O) Luoconverters Carefully check P/O Luoconverters, we can see that there are two switches required from relift circuit. In order to use only one switch in all P/O Luoconverters, we modify the circuits. In this section we introduce following four circuits:
(14.52)
The variation ratio of the output voltage is εj =
• •
1 vO /2 k = 2 VO 16Mj f CO L2
•
(14.53)
•
Further lift circuits can be derived from the above circuits. In all S P/O Luoconverters, we deﬁne normalized impedance zN = R/fL. S P/O Luoconverter selflift circuit is shown in Fig. 14.30a. The equivalent circuits during switchon and off periods are shown in Figs. 14.30b and c. Its output voltage and current are
The condition for discontinuous conduction mode is k [1+h(j)] j + h(j) zN ≥ 1 2 Mj2
(14.54)
The output voltage in discontinuous conduction mode is 1−k VO−j = j + k [2−h(j)] zN V I 2
Simpliﬁed selflift circuit; Simpliﬁed relift circuit; Simpliﬁed triplelift circuit; Simpliﬁed quadruplelift circuit.
VO =
(14.55)
1 VI 1−k
and where IO = (1 − k)II
h(j) =
j≥1 j=0
0 if 1 if
The voltage transfer gain in CCM is
(14.56)
MS =
is the Hong function.
iI
VC
− S
+
C
iL
VI −
iLO
+ D1
VC1 − D
L
iO
LO
+
VO II 1 = = VI IO 1−k
+
C1
R −
CO
VO
(a)
iI
+ VI −
−
VC
iLO
+
C
iL
−
LO
iLO
+
VC1 L
+
(b)
C1
CO
iO
iO
R −
iL
VO
− VC L
+
LO
−
+
VC1 C
+
C1
CO
R −
VO
(c)
FIGURE 14.30 S P/O Luoconverter selflift circuit: (a) circuit diagram; (b) switch on; and (c) switch off.
(14.57)
14
277
DC/DC Conversion Technique and 12 Series Luoconverters
The variation ratio of the output voltage vO in CCM is ε=
vO /2 1 k = 3 VO 128 f LO C1 CO R
The voltage transfer gain in CCM is MR =
(14.58)
ε=
√
with
k
R 1 ≥ 2fL 1−k (14.60)
2 VI 1−k
IO =
1−k II 2
R VO = 2 + k (1 − k) VI 2fL 2
VO =
iI D11
S
C
D10 +
VI
VC2
iLO
VC +
−
iL
k
2 R ≥ fL 1−k (14.64)
iL1
−
L1
D
L
3 VI 1−k
iO LO
D1
C2
−
with
√
S P/O Luo triplelift circuit is shown in Fig. 14.32a. The equivalent circuits during switchon and off periods are shown in Figs. 14.32b and c. Its output voltage and current are
and
+
(14.62)
The output voltage in DCM is
S P/O Luoconverter relift circuit is shown in Fig. 14.31a. The equivalent circuits during switchon and off periods are shown in Figs. 14.31b and c. Its output voltage and current are VO =
vO /2 k 1 = VO 128 f 3 LO C1 CO R
This converter may work in discontinuous conduction mode if the frequency f is small, conduction duty k is small, inductance L is small, and load current is high. The condition for DCM is MR ≤ kzN (14.63)
The output voltage in DCM is R 2 VO = 1 + k (1 − k) VI 2fL
(14.61)
The variation ratio of the output voltage vO in CCM is
This converter may work in discontinuous conduction mode if the frequency f is small, conduction duty k is small, inductance L is small, and load current is high. The condition for DCM is √ zN MS ≤ k (14.59) 2
VO II 2 = = VI IO 1−k
+
+ VC1 −
CO
C1
VO R
−
D2 (a)
iI
− VC +
+ VC2 iL
+ −
iL1
iO
LO
C
VI −
iLO
L1
R +
C2
VC1 −
L (b)
C1
CO
+ VO −
+
i VC2 L1 − C2
iL
L
− VC +
iLO
C
LO
L1
iO
R
+ VC1 −
C1
CO
(c)
FIGURE 14.31 S P/O Luoconverter relift circuit: (a) circuit diagram; (b) switch on; and (c) switch off.
+ VO −
278
F. L. Luo and H. Ye iI
iLO
− VC + D11
S
+
D10 D12
+
C
VC2 − C2
C3
− iL
LO
D1
iL1
VC3 + −
VI
iO
L2
R +
+
L1 D
VC1 −
C1
CO
VO −
L D3
D2 (a)
+ VI −
iLO
V − C+
iI +
VC3 − C3
+
C2
LO
C
VC2 − iL1 L1
iL
L
+ VC1 C 1 −
L2
iO
− VC2 + −
R + VO
VC3 + − C L 3
− CO
i
iL1 C2
VC
iLO
+
LO + VC1 C 1 −
C i
L1
iO R CO
+ VO −
L1
L2
L
(b)
(c)
FIGURE 14.32 S P/O Luoconverter triplelift circuit: (a) circuit diagram; (b) switch on; and (c) switch off.
and IO =
S P/O Luo quadruplelift circuit is shown in Fig. 14.33a. The equivalent circuits during switchon and off periods are shown in Figs. 14.33b and c. Its output voltage and current are
1−k II 3
The voltage transfer gain in CCM is MT =
VO II 3 = = VI IO 1−k
(14.65)
VO =
4 VI 1−k
IO =
1−k II 4
and
The variation ratio of the output voltage vO in CCM is ε=
vO /2 k 1 = 3 VO 128 f LO C1 CO R
(14.66)
This converter may work in discontinuous conduction mode if the frequency f is small, conduction duty k is small, inductance L is small, and load current is high. The condition for DCM is 3kzN MT ≤ (14.67) 2 The output voltage in DCM is R 2 VO = 3 + k (1 − k) VI 2fL
with
√
k
3 3R ≥ 2fL 1−k (14.68)
The voltage transfer gain in CCM is MQ =
VO II 4 = = VI IO 1−k
(14.69)
The variation ratio of the output voltage vO in CCM is ε=
vO /2 1 k = 3 VO 128 f LO C1 CO R
(14.70)
This converter may work in discontinuous conduction mode if the frequency f is small, conduction duty k is small, inductance L is small, and load current is high. The condition for DCM is MQ ≤
2kzN
(14.71)
14
279
DC/DC Conversion Technique and 12 Series Luoconverters iI
− D11
S
D12 V iL2 − C3+ D13 C3 i
+
D10 VC4 L3 − +
VI −
VC
VC2iL1 + − C2 L1 L2
L3
D3
D4
L
iO
LO
D1
C
+ VC1 D −
C4 iL
iLO
+
C1
+ VO R −
CO
D2 (a)
iI
−
+
VC4 − +
VI
C4
−
L iL
VC2iL1 iL2 + − VC3 C2 − + iL3
C3
iLO
VC + C
+
iL1
LO
VC1 − C1
L1
iO
L2
VC4 − +
R + VO CO −
C4 iL L
L3
V − C3+ iL3
C3
VC2 iL2 + − C2
−
VC
iLO
+
C
L1
+ VC1 −
iO
LO R C1
CO
+ VO −
L2
L3
(b)
(c)
FIGURE 14.33 S P/O Luoconverter quadruplelift circuit: (a) circuit diagram; (b) switch on; and (c) switch off.
The output voltage in DCM is
The output voltage in discontinuous mode is
R 2 VI VO = 4 + k (1 − k) 2fL
with
√
k
R zN = ; fL
VO R= IO
To write common formulas for all circuits parameters, we deﬁne that subscript j = 1 for the selflift circuit, j = 2 for the relift circuit, j = 3 for the triplelift circuit, j = 4 for the quadruplelift circuit, and so on. The voltage transfer gain is j Mj = 1−k
vO /2 k 1 = 3 VO 128 f LO C1 CO R
(14.73)
(14.74)
The condition for discontinuous mode is Mj ≤
jkzN 2
Negative output (N/O) Luoconverters perform the voltage conversion from positive to negative voltages using the voltagelift technique. They work in the thirdquadrant with large voltage ampliﬁcation. Their voltage transfer gains are high. Five circuits are introduced in the literature. They are: • • • •
The variation ratio of the output voltage is εj =
(14.76)
14.3.3 Negative Output Luoconverters
Summary for all S P/O Luoconverters: II VO = ; M= VI IO
zN
VI VO−j = j + k 2 (1 − k) 2
4 2R ≥ fL 1−k (14.72)
(14.75)
•
Elementary circuit; Selflift circuit; Relift circuit; Triplelift circuit; Quadruplelift circuit.
Further lift circuits can be derived from above circuits. In all N/O Luoconverters, we deﬁne normalized impedance zN = R/fL. N/O Luoconverter elementary circuit is shown in Fig. 14.34a. The equivalent circuits during switchon and off periods are shown in Figs. 14.34b and c. Its output voltage and current (the absolute value) are VO =
k VI 1−k
280
F. L. Luo and H. Ye iD
iI
+
VS
− +
VIN
VL −
+
iL
VD
−VLO +
−
L
LO
iC
D −
iLO
C
VC +
IO iCO
−
CO
R VO +
(a) D LO
LO
+ L C
VIN
CO
C
L
R
CO
R
−
(b)
(c)
FIGURE 14.34 N/O Luoconverter elementary circuit: (a) circuit diagram; (b) switch on; and (c) switch off.
and IO =
shown in Figs. 14.35b and c. Its output voltage and current (the absolute value) are
1−k II k
VO =
When k is greater than 0.5, the output voltage can be higher than the input voltage. The voltage transfer gain in CCM is ME =
VO II k = = VI IO 1−k
(14.77)
and IO = (1 − k)II The voltage transfer gain in CCM is MS =
The variation ratio of the output voltage vO in CCM is ε=
k 1 vO /2 = VO 128 f 3 CCO LO R
(14.78)
This converter may work in discontinuous conduction mode if the frequency f is small, conduction duty k is small, inductance L is small, and load current is high. The condition for DCM is zN (14.79) ME ≤ k 2 The output voltage in DCM is R VI VO = k(1 − k) 2fL
with
1 R ≥ 2fL 1−k
1 VI 1−k
VO II 1 = = VI IO 1−k
(14.81)
The variation ratio of the output voltage vO in CCM is ε=
vO /2 1 k = VO 128 f 3 CCO LO R
(14.82)
This converter may work in discontinuous conduction mode if the frequency f is small, conduction duty k is small, inductance L is small, and load current is high. The condition for DCM is √ zN MS ≤ k (14.83) 2 The output voltage in DCM is
(14.80)
N/O Luoconverter selflift circuit is shown in Fig. 14.35a. The equivalent circuits during switchon and off periods are
R 2 VO = 1 + k (1 − k) VI 2fL
with
√
k
1 R ≥ 2fL 1−k (14.84)
14
281
DC/DC Conversion Technique and 12 Series Luoconverters S
+
VC1
iC1
iIN VIN
C1
−
−
L VD1 +
iL
+
VD
− VLO +
−
LO
iD D iD1 − VC +
iO iLO
iC C
−
iCO CO
R VO +
(a) C1 LO
LO
+ C1
L
C
CO
R
L
C
CO
R
−
(b)
(c)
FIGURE 14.35 N/O Luoconverter selflift circuit: (a) circuit diagram; (b) switch on; and (c) switch off.
N/O Luoconverter relift circuit is shown in Fig. 14.36a. The equivalent circuits during switchon and off periods are shown in Figs. 14.36b and c. Its output voltage and current (the absolute value) are VO =
2 VI 1−k
R 2 VI VO = 2 + k (1 − k) 2fL
with
√
k
R 2 ≥ fL 1−k (14.88)
N/O Luoconverter triplelift circuit is shown in Fig. 14.37a. The equivalent circuits during switchon and off periods are shown in Figs. 14.37b and c. Its output voltage and current (the absolute value) are
and IO =
The output voltage in DCM is
1−k II 2
VO =
3 VI 1−k
IO =
1−k II 3
The voltage transfer gain in CCM is and MR =
VO II 2 = = VI IO 1−k
(14.85)
The variation ratio of the output voltage vO in CCM is ε=
1 k vO /2 = VO 128 f 3 CCO LO R
(14.86)
This converter may work in discontinuous conduction mode if the frequency f is small, conduction duty k is small, inductance L is small, and load current is high. The condition for DCM is MR ≤
kzN
(14.87)
The voltage transfer gain in CCM is MT =
VO II 3 = = VI IO 1−k
(14.89)
The variation ratio of the output voltage vO in CCM is ε=
1 k vO /2 = VO 128 f 3 CCO LO R
(14.90)
This converter may work in discontinuous conduction mode if the frequency f is small, conduction duty k is small,
282
F. L. Luo and H. Ye iD11
iC1
S − VS +
iL1
D11
iIN
iD D
C1
iO
− VLO + iC
LO
iLO
iCO
L1
D10
− C2
VIN iL
R VO
CO
C
+
L
D2
D1
(a) C2
C1 LO
+ VIN
C2
C1 L1
L
C
L1 CO
LO
L
R
CO
C
R
− (b)
(c)
FIGURE 14.36 N/O Luoconverter relift circuit: (a) circuit diagram; (b) switch on; and (c) switch off.
iC1 D11 iC2
S iIN
−V + S
D12
D
C2 L2 iL2
D10
iD
C1
iC
LO
iLO iCO
L1 iL1
−
C3
VIN
iO
− VLO +
R VO
CO
C
+ iL
D2
D3
L
D1 iD1
iD2
iD3
(a) iC1 iC2
iIN C3
VIN iL
L
C1
C2
L2 i L1 iL2 L1
− VLO + iC
(b)
LO i LO iCO R
C
− VLO +
iO
CO
C3
− VO +
iL
L
C2 L2 iL2
C1 iL1
L1
LO
iLO
iC C
CO
(c)
FIGURE 14.37 N/O Luoconverter triplelift circuit: (a) circuit diagram; (b) switch on; and (c) switch off.
iO iCO R
− VO +
14
283
DC/DC Conversion Technique and 12 Series Luoconverters
inductance L is small, and load current is high. The condition for DCM is 3kzN MT ≤ (14.91) 2
The voltage transfer gain in CCM is VO II 4 = = VI IO 1−k
MQ =
(14.93)
The variation ratio of the output voltage vO in CCM is
The output voltage in DCM is R VI VO = 3 + k (1 − k) 2fL
2
√
with
k
3 3R ≥ 2fL 1−k (14.92)
ε=
MQ ≤
4 VO = VI 1−k
R VO = 4 + k (1 − k) VI 2fL 2
iD11 iD12 iD13
D10
iC2
C1
iD D
L3
L2
iL3
k
2R 4 ≥ fL 1−k (14.96)
iO
− VLO +
C2
C3
iC4
with
√
iC1
D11 iC3
D12
D13
LO
iC
iLO
iCO
L1
iL2
iL1
−
C4
VIN
(14.95)
1−k IO = II 4
iIN
2kzN
The output voltage in DCM is
and
− VS +
(14.94)
This converter may work in discontinuous conduction mode if the frequency f is small, conduction duty k is small, inductance L is small, and load current is high. The condition for DCM is
N/O Luoconverter quadruplelift circuit is shown in Fig. 14.38a. The equivalent circuits during switchon and off periods are shown in Figs. 14.38b and c. Its output voltage and current (the absolute value) are
S
vO /2 k 1 = VO 128 f 3 CCO LO R
R VO
CO
C
+ L iL
D3
D4 iD4
D2 iD1
iD2
iD3
D1
(a)
iC2 iC3
iIN VIN
iL
C1
C2
C3
C4 L iL3
L3
iL2
L2
(b)
iL1
iO
− VLO +
iC1
L1
iO
− VLO + iC C
LO
iLO CO
iCO R
iL3 − VO +
C3
C2
C1
L3
L2
L1
iL2
iL1
iC
LO
iLO iCO −
C
C4
CO
L iL (c)
FIGURE 14.38 N/O Luoconverter quadruplelift circuit: (a) circuit diagram; (b) switch on; and (c) switch off.
R
VO +
284
F. L. Luo and H. Ye
Summary for all N/O Luoconverters: M=
VO II = ; IO VI
zN =
R ; fL
R=
VO IO
To write common formulas for all circuits parameters, we deﬁne that subscript j = 0 for the elementary circuit, j = 1 for the selflift circuit, j = 2 for the relift circuit, j = 3 for the triplelift circuit, j = 4 for the quadruplelift circuit, and so on. The voltage transfer gain is Mj =
k h(j) [j + h(j)] 1−k
Further lift circuits can be derived from above circuits. In all D/O Luoconverters, each circuit has two conversion paths – positive conversion path and negative conversion path. The positive path likes P/O Luoconverters, and the negative path likes N/O Luoconverters. We deﬁne normalized impedance zN + = R/fL for positive path, and normalized impedance zN − = R1 /fL11 . We usually purposely select R = R1 and L = L11 , so that we have zN = zN + = zN − . D/O Luoconverter elementary circuit is shown in Fig. 14.7. Its output voltages and currents (absolute values) are VO+ = VO−  =
(14.97)
IO+ =
The variation ratio of the output voltage is vO /2 1 k = 3 128 f CCO LO R VO
ε=
(14.98)
(14.99)
The output voltage in discontinuous conduction mode is
VO−j = j + k [2−h(j)]
1−k zN V I 2
(14.100)
where
IO− =
h(j) =
0 if 1 if
j≥1 j=0
is the Hong function.
14.4 Double Output Luoconverters Double output (D/O) Luoconverters perform the voltage conversion from positive to positive and negative voltages simultaneously using the voltagelift technique. They work in the ﬁrst and thirdquadrants with high voltage transfer gain. There are ﬁve circuits introduced in this section: • • • • •
D/O Luoconverter elementary circuit; D/O Luoconverter selflift circuit; D/O Luoconverter relift circuit; D/O Luoconverter triplelift circuit; D/O Luoconverter quadruplelift circuit.
1−k II − k
When k is greater than 0.5, the output voltage can be higher than the input voltage. The voltage transfer gain in CCM is ME =
VO+ VO−  k = = VI VI 1−k
(14.101)
The variation ratio of the output voltage vO+ in CCM is ε+ =
1−k II + k
and
The condition for discontinuous conduction mode is k [1+h(j)] j + h(j) zN ≥ 1 2 Mj2
k VI 1−k
1 vO+ /2 k = VO+ 16ME f 2 CO L2
(14.102)
The variation ratio of the output voltage vO− in CCM is ε− =
1 vO− /2 k = VO− 128 f 3 C11 C10 L12 R1
(14.103)
This converter may work in discontinuous conduction mode if the frequency f is small, conduction duty k is small, inductance L is small, and load current is high. The condition for DCM is ME ≤ k
zN 2
(14.104)
The output voltages in DCM are VO = VO+ = VO−  = k(1 − k)
zN VI 2
with
1 zN ≥ 2 1−k (14.105)
14
285
DC/DC Conversion Technique and 12 Series Luoconverters S
iIN
VS
iIN+ iL1
+ VIN −
C1
D20 −
D1
+ VC1
L1
Io+
L2
+
iL2 D0
C2
R Vo+
Co
− iIN− iL11
L11
+
+ VC11 D11 − D10
D21
R1 Vo−
C10
C11 iL2
− Io−
L12
C12
FIGURE 14.39 Double output Luoconverter selflift circuit.
D/O Luoconverter selflift circuit is shown in Fig. 14.39. Its output voltages and currents (absolute values) are VO+ = VO−  =
The output voltages in DCM are zN
VI VO = VO+ = VO−  = 1 + k 2 (1 − k) 2 kzN 1 with ≥ (14.110) 2 1−k
1 VI 1−k
IO+ = (1 − k)II +
D/O Luoconverter relift circuit is shown in Fig. 14.40. Its output voltages and currents (absolute values) are
and IO− = (1 − k)II −
VO+ = VO−  =
The voltage transfer gain in CCM is MS =
VO+ VO−  1 = = VI VI 1−k
IO+ = (14.106)
1 vO+ /2 k = VO+ 128 f 3 L2 CO C2 R
1−k II + 2
and IO− =
The variation ratio of the output voltage vO+ in CCM is ε+ =
2 VI 1−k
1−k II − 2
The voltage transfer gain in CCM is (14.107) MR =
The variation ratio of the output voltage vO− in CCM is
VO+ VO−  2 = = VI VI 1−k
(14.111)
The variation ratio of the output voltage vO+ in CCM is vO− /2 k 1 ε− = = 3 VO− 128 f C11 C10 L12 R1
(14.108)
This converter may work in discontinuous conduction mode if the frequency f is small, conduction duty k is small, inductance L is small, and load current is high. The condition for DCM is √ MS ≤ k
zN 2
(14.109)
ε+ =
vO+ /2 k 1 = VO+ 128 f 3 L2 CO C2 R
(14.112)
The variation ratio of the output voltage vO− in CCM is ε− =
vO− /2 k 1 = 3 VO− 128 f C11 C10 L12 R1
(14.113)
This converter may work in discontinuous conduction mode if the frequency f is small, conduction duty k is small,
286
F. L. Luo and H. Ye VS
S
iIN+
iIN +
VIN −
− VC1 +
D20
iL1
D2 C3 L1
D21
IO+
L2
C1
+
iL2 D0
L3
iIN− iL11
D1
C2
R VO+
C0
D3
−
D11
+ D12 + VC11 −
L11 L13
C12
C13
D22
C11
R1 VO−
C10
iL12
D10
− IO−
L12
FIGURE 14.40 D/O Luoconverter relift circuit.
inductance L is small, and load current is high. The condition for DCM is MR ≤
kzN
D/O Luoconverter triplelift circuit is shown in Fig. 14.41. Its output voltages and currents (absolute values) are
The output voltages in DCM are
IO+ =
zN
VI VO = VO+ = VO−  = 2 + k 2 (1 − k) 2 2 with kzN ≥ (14.115) 1−k
S
VS iIN+
iIN +
VIN −
iL1
iL11
IO− =
D2
D20
C1
C3 L1
C4 L3
L4
iIN− L11 C12 D21
1−k II + 3
and
− VC1 +
D4
3 VI 1−k
VO+ = VO−  =
(14.114)
D1
1−k II − 3
IO+
L2
+
iL2
D0
C2
C0
R VO+
D3
D5
−
D11
D12
+
L13
L14
C13
D13 + VC11 − D10
D22 D23
C11
C10
R1 VO−
iL12
−
C14 L12
FIGURE 14.41 D/O Luoconverter triplelift circuit.
IO−
14
287
DC/DC Conversion Technique and 12 Series Luoconverters S VS iIN + VIN −
D20 iIN+
iL1
VC1
D2
D4
D6
C1
C3 L1
C4 L3
C5 L4
L5
iIN− iL11
−
L11
+
Io+
L2
+
iL2 C2
D0
Co
R Vo+ −
D3
D5
D7
D11
D12
D13
D14 + VC11 −
L13
C12
D21
D1
C11
C10
R1
Vo−
C13
D22
−
C14
D23
C15
D24
+
iL12
D10
Io−
L12
FIGURE 14.42 D/O Luoconverter quadruplelift circuit.
The voltage transfer gain in CCM is MT =
VO+ VO−  3 = = VI VI 1−k
D/O Luoconverter quadruplelift circuit is shown in Fig. 14.42. Its output voltages (absolute values) are (14.116)
VO+ = VO−  =
The variation ratio of the output voltage vO+ in CCM is 1 vO+ /2 k = ε+ = VO+ 128 f 3 L2 CO C2 R
IO+ = (14.117)
1 vO− /2 k = 3 VO− 128 f C11 C10 L12 R1
(14.118)
This converter may work in discontinuous conduction mode if the frequency f is small, conduction duty k is small, inductance L is small, and load current is high. The condition for DCM is MT ≤
3kzN 2
1−k II + 4
and
The variation ratio of the output voltage vO− in CCM is ε− =
4 VI 1−k
(14.119)
The output voltages in DCM are zN
VI VO = VO+ = VO−  = 3 + k 2 (1 − k) 2 3 3kzN with ≥ (14.120) 2 1−k
IO− =
1−k II − 4
The voltage transfer gain in CCM is MQ =
VO+ VO−  4 = = VI VI 1−k
(14.121)
The variation ratio of the output voltage vO+ in CCM is ε+ =
1 vO+ /2 k = 3 VO+ 128 f L2 CO C2 R
(14.122)
The variation ratio of the output voltage vO− in CCM is ε− =
vO− /2 k 1 = VO− 128 f 3 C11 C10 L12 R1
(14.123)
This converter may work in discontinuous conduction mode if the frequency f is small, conduction duty k is small,
288
F. L. Luo and H. Ye
inductance L is small, and load current is high. The condition for DCM is MQ ≤ 2kzN (14.124) The output voltages in DCM are zN
VI VO = VO+ = VO−  = 4 + k 2 (1 − k) 2 4 (14.125) with 2kzN ≥ 1−k
14.5 Superlift Luoconverters Voltagelift (VL) technique has been successfully applied in DC/DC converter’s design. However, the output voltage of all VL converters increases in arithmetic progression stagebystage. Superlift (SL) technique is more powerful than VL technique. The output voltage of all SL converters increases in geometric progression stagebystage. All superlift converters are outstanding contributions in DC/DC conversion technology, and invented by Professor Luo and Dr. Ye in 2000–2003. There are four series SL Converters introduced in this section:
Summary for all D/O Luoconverters: M=
VO−  VO+ = ; VI VI
L= zN + =
L 1 L2 ; L1 + L 2 R ; fL
L = L11 ;
zN − =
R = R1 ;
R1 fL11
There are several subseries of P/O superlift Luoconverters:
zN = zN + = zN −
•
To write common formulas for all circuits parameters, we deﬁne that subscript j = 0 for the elementary circuit, j = 1 for the selflift circuit, j = 2 for the relift circuit, j = 3 for the triplelift circuit, j = 4 for the quadruplelift circuit, and so on. The voltage transfer gain is k h(j) [j + h(j)] 1−k
(14.126)
The variation ratio of the output voltage vO+ in CCM is ε+j =
vO+ /2 k 1 = VO+ 128 f 3 L2 CO C2 R
Positive output (P/O) superlift Luoconverters; Negative output (N/O) superlift Luoconverters; Positive output (P/O) cascade boostconverter; Negative output (N/O) cascade boostconverter;
14.5.1 P/O Superlift Luoconverters
so that
Mj =
1. 2. 3. 4.
• • • •
Main series; Additional series; Enhanced series; Reenhanced series; Multienhanced series.
We only introduce three circuits of main series and additional series. P/O SL Luoconverter elementary circuit is shown in Fig. 14.43a. The equivalent circuits during switch on and switch off are shown in Figs. 14.43b and c. Its output voltage and current are
(14.127) VO =
2−k VI 1−k
IO =
1−k II 2−k
The variation ratio of the output voltage vO− in CCM is ε−j =
vO− /2 k 1 = VO− 128 f 3 C11 C10 L12 R1
(14.128)
and
The condition for DCM is k [1+h(j)] j + h(j) zN ≥ 1 2 Mj2 The output voltage in DCM is 1−k zN V I VO−j = j + k [2−h(j)] 2 where
0 if h(j) = 1 if is the Hong function.
j≥1 j=0
(14.129)
The voltage transfer gain is ME =
(14.130)
2−k VO = VI 1−k
(14.131)
The variation ratio of the output voltage vO is ε=
vO /2 k = VO 2RfC2
(14.132)
P/O SL Luoconverter relift circuit is shown in Fig. 14.44a. The equivalent circuits during switch on and switch off are
14
289
DC/DC Conversion Technique and 12 Series Luoconverters Iin
D1
D2
+ L1
+ VC1 −
C1
Vin
C2
S
−
+ VC2 R −
(a) Iin
Iin
IO
+ Vin
L1
+ VC2
+ Vin C2
C1
−
−
−
R
+
+ VO
L1
C1
VL1
− Vin +
Vin
−
IO + VC2
C2
R
−
−
(b)
+ VO −
(c)
FIGURE 14.43 P/O SL Luoconverter elementary circuit: (a) circuit diagram; (b) switch on; and (c) switch off.
Iin +
D1
L1
C1
D2
V1
D4
+ VC1 −
L2
D5
C3
IO
+ VC3 −
Vin
R D3 C2
−
+ VC2 −
S
C4
+ VC4 −
+ VO −
(a) V1 + Vin L1 −
C1
+ VC2 L2 −
+ Vin C2 −
IO C3
+ C4 V1 −
+ VC4 R −
+ VO −
Iin
L1
+
VL1
Vin
C1 −V + in C2
−
(b)
L2
V1 + V1 −
C3
VL2
−V + 1
C4
IO + VC4 R −
+ VO −
(c)
FIGURE 14.44 P/O SL Luoconverter relift circuit: (a) circuit diagram; (b) switch on; and (c) switch off.
shown in Figs. 14.44b and c. Its output voltage and current are VO =
2−k 1−k
2 VI
The voltage transfer gain is VO MR = = VI
2−k 1−k
2 (14.133)
The variation ratio of the output voltage vO is
and IO =
1−k 2−k
2 II
ε=
vO /2 k = VO 2RfC4
(14.134)
290
F. L. Luo and H. Ye Iin +
D2
D1
L1
V1
+ VC1 −
C1
D4
L2
D5
V2
+ VC3 −
C3
D7
L3
D8 IO
+ VC5 −
C5
Vin
R D3 C2
−
D6
+ VC2 −
C4
+ VC4 −
S
C6
+ VC6 −
V1
L2
C3
+ VO −
(a) Iin + Vin L1 −
V1
V2
Iin IO
L1
+
VL1 −
+ C4 + + C + + C1 + C2 + L 6 L3 R V Vin VC2 2 C3 Vin V1 VC4 C5 V2 O VC6 − − − − − − − − (b)
C1 +
VL2 −
Vin
+
C2
V1 −
V1
V2 L3 +
C4
+ V2
VL3 −
−
C5 V2
IO +
C6
+ + R VC6 VO − −
(c)
FIGURE 14.45 P/O SL Luoconverter triplelift circuit: (a) circuit diagram; (b) switch on; and (c) switch off.
P/O SL Luoconverter triplelift circuit is shown in Fig. 14.45a. The equivalent circuits during switch on and switch off are shown in Figs. 14.45b and c. Its output voltage and current are VO =
2−k 1−k
3
and IO = The voltage transfer gain is
VI MA =
and IO =
1−k 2−k
3
ε=
2−k 1−k
3
vO /2 k = VO 2RfC6
(14.135)
(14.136)
P/O SL Luoconverter additional circuit is shown in Fig. 14.46a. The equivalent circuits during switch on and switch off are shown in Figs. 14.46b and c. Its output voltage and current are VO =
3−k VI 1−k
(14.137)
vO /2 k = VO 2RfC12
(14.138)
P/O SL Luoconverter additional relift circuit is shown in Fig. 14.47a. The equivalent circuits during switch on and switch off are shown in Figs. 14.47b and c. Its output voltage and current are
The variation ratio of the output voltage vO is ε=
VO 3−k = VI 1−k
The variation ratio of the output voltage vO is II
The voltage transfer gain is VO MT = = VI
1−k II 3−k
VO =
2−k 3−k VI 1−k 1−k
IO =
1−k 1−k II 2−k 3−k
and
The voltage transfer gain is MAR =
VO 2−k 3−k = VI 1−k 1−k
(14.139)
14
291
DC/DC Conversion Technique and 12 Series Luoconverters Iin
V1 D11
D2
D1
D12
+
+
L1
C1
C11
VC1 −
+ VC11 −
Vin
+ VO
R S
−
+ VC2 −
C2
−
+ VC12 −
C12
(a) C11 Iin
V1
+ Vin L1
C1
+ Vin
C2
−
−
Iin
IO
+ V1 C11
+ C12 V1
−
−
+ VC12 −
C1
− VL1 +
+
+ VO
R
L1
Vin
−
V1
− V + in
+ V1 −
C2
−
(b)
IO
−V + 1 + VC12 R −
C12
+ VO −
(c)
FIGURE 14.46 P/O SL Luoconverter additional circuit: (a) circuit diagram; (b) switch on; and (c) switch off. Iin +
D2
D1
D4
V1
D5
+ L1
C1
−
L2
VC1
V2 D11
+ VC3 −
C3
D12
IO
+ VC11 −
C11
Vin
+ VO
R D3 C2
−
+ −
VC2
S
C4
+ VC4 −
−
+ VC12 −
C12
(a) C11
Iin
V1 C1 + L1
C2 + Vin V1 L2 − −
V2
IO
+
+ C4 + C11 + C12 + R V V2 V1 V2 VC12 O Vin − − − − − − +
C3
Iin
L1
C1 − Vin + C2
L2
V1 + −
− V1 + C4
V1
(b)
C3 V − V2 + 2 + −
C12 V2
(c)
FIGURE 14.47 P/O SL Luoconverter additional relift circuit: (a) circuit diagram; (b) switch on; and (c) switch off.
The variation ratio of the output voltage vO is k vO /2 = ε= VO 2RfC12
voltage and current are (14.140)
P/O SL Luoconverter additional triplelift circuit is shown in Fig. 14.48a. The equivalent circuits during switch on and switch off are shown in Figs. 14.48b and c. Its output
VO = and
IO =
2−k 1−k
1−k 2−k
2
2
3−k VI 1−k
1−k II 3−k
IO + R + VC12 VO − −
292
F. L. Luo and H. Ye D1
Iin +
D2 + VC1 −
C1
L1
D4
V1
L2
D5
V2
D7
+ VC3 −
C3
+ VC5 −
C5
L3
D12
D11
D8
IO
+ VC11 −
C11
+ R
Vin
D3
+ VC2 −
C2
−
D6 C4
+ VC4 −
+ VC6 −
C6
S
VO
− + VC12 −
C12
(a) Iin
V1 +
C1 L1
+
C2 V in
VC2
L2
C3
+
C4 V1
−
−
V2 +
C5
+
VC4 L3
+
C6 V2
−
−
V3
IO
C11
VC6 −
−
+
C12 V3
+
+
VC12 R −
−
VO −
(b) C11 Iin
C1
L1 −
V1 +
Vin
− +
C2
C3
L2
V1
V1
V2
L3
− C5
+
+
−
V2
C4
−
−
V1
V3
V3
+
IO +
+
+
+ V3
C6
VO
VC12 R
C12
−
−
− (c)
FIGURE 14.48 P/O SL Luoconverter additional triplelift circuit: (a) circuit diagram; (b) switch on; and (c) switch off.
The voltage transfer gain is MAT
VO = = VI
2−k 1−k
2
3−k 1−k
(14.141)
We only introduce three circuits of main series and additional series. N/O SL Luoconverter elementary circuit is shown in Fig. 14.49. Its output voltage and current are
The variation ratio of the output voltage vO is ε=
k vO /2 = VO 2RfC12
VO = (14.142)
1 2−k −1 = VI 1−k 1−k
Iin
14.5.2 N/O Superlift Luoconverters
+
There are several subseries of N/O Superlift Luoconverters:
Vin
• • • • •
Main series; Additional series; Enhanced series; Reenhanced series; Multienhanced series.
−
IO
+
S L1
C1 D1
−
VC1
D2 C2
− R
− +
VC2
VO +
FIGURE 14.49 N/O SL Luoconverter elementary circuit.
14
293
DC/DC Conversion Technique and 12 Series Luoconverters
and
Iin
IO = (1 − k)II
D3
S +
The voltage transfer gain is
+
Vin
VO 1 ME = = VI 1−k
(14.143)
L1
−
+ L2
VC1 − V1
C1 D1
− D4 VC2 +
C2
C5
VC5 −
− D7 VC4 +
D5 C4
IO
+
L3
VC3 − V2
C3
D2
The variation ratio of the output voltage vO is ε=
D6
D8 C6
_
− +
R
VO
VC6
+
FIGURE 14.51 N/O SL Luoconverter triplelift circuit.
vO /2 k = VO 2RfC2
(14.144)
N/O SL Luoconverter relift circuit is shown in Fig. 14.50. Its output voltage and current are
2−k 2 VO = − 1 VI 1−k
The voltage transfer gain is VO MT = = VI
2−k 1−k
3 −1
(14.147)
The variation ratio of the output voltage vO is and II
IO =
2
(2 − k)/(1 − k)
ε= −1
2−k 1−k
(14.148)
N/O SL Luoconverter additional circuit is shown in Fig. 14.52. Its output voltage and current are
The voltage transfer gain is VO MR = = VI
vO /2 k = VO 2RfC6
2 −1
(14.145)
The variation ratio of the output voltage vO is
VO =
3−k 2 − 1 VI = VI 1−k 1−k
and
vO /2 k ε= = 2RfC4 VO
(14.146)
N/O SL Luoconverter triplelift circuit is shown in Fig. 14.51. Its output voltage and current are
2−k 3 VO = − 1 VI 1−k
1−k II 2
IO = The voltage transfer gain is MA =
VO 3−k 2 = −1= VI 1−k 1−k
(14.149)
The variation ratio of the output voltage vO is
and II
IO =
3
(2 − k)/(1 − k)
ε=
−1
Iin
Vin −
(14.150)
Iin S
+
vO /2 k = VO 2RfC12
− L1
C1 D1
+
D3
C3
VC1 V1 D2 C2
− +
VC3
− R
− +
D4 VC2
D5 C4
− +
VC4
FIGURE 14.50 N/O SL Luoconverter relift circuit.
VO +
+
S
IO L2
+
L1
C1
−
C11
VC1
− +
Vin −
D1
D2 C2
− +
D11 VC2
IO
VC11
D12 C12
− − +
R VC12
VO +
FIGURE 14.52 N/O SL Luoconverter additional circuit.
294
F. L. Luo and H. Ye Iin S
D3
+
+ Vin −
+
L2 VC1 − V1
C1
L1
D2
D1
D4
−
C2
+
VC2
+
V2
D5 C4
+
VC11
− R
D11
−
IO
−
C11
VC3 −
C3
−
D12
VC4
C12
+
VO +
VC12
FIGURE 14.53 N/O SL Luoconverter additional relift circuit.
NO SL Luoconverter additional relift circuit is shown in Fig. 14.53. Its output voltage and current are VO =
and II 2 (2 − k)/(1 − k) (3 − k)/(2 − k) − 1
IO =
2−k 3−k − 1 VI 1−k 1−k
The voltage transfer gain is and MAT =
II IO = (2 − k)/(1 − k) (3 − k)/(1 − k) − 1
ε=
VO 2−k 3−k −1 = = VI 1−k 1−k
(14.151)
vO /2 k ε= = VO 2RfC12
VO =
2
3−k −1 1−k
2
vO /2 k = VO 2RfC12
(14.152)
• • • •
•
3−k − 1 VI 1−k
We only introduce three circuits of main series and additional series.
D3
S
−
D6 +
+ L1
C1
Vin D1
VC1 −
L2
C3
V1
D2
− C2
+
(14.154)
Main series; Additional series; Double series; Triple series; Multiple series.
Iin
+
(14.153)
There are several subseries of P/O cascade boostconverters (CBC):
N/O SL Luoconverter additional triplelift circuit is shown in Fig. 14.54. Its output voltage and current are 2−k 1−k
2−k 1−k
14.5.3 P/O Cascade Boostconverters
The variation ratio of the output voltage vO is
The variation ratio of the output voltage vO is
The voltage transfer gain is MAR
VO = VI
D4 VC2
VC3 −
+
L3 C5 V2 −
D5 C4
+
D7 VC4
−
C11
VC5
V3 D8 C6
− +
IO
− +
VC11
− R
D11 VC6
D12 C12
FIGURE 14.54 N/O SL Luoconverter additional triplelift circuit.
VO + − VC12 +
14
295
DC/DC Conversion Technique and 12 Series Luoconverters iIN
+ VIN −
L1
P/O CBC twostage circuit is shown in Fig. 14.56. Its output voltage and current are
D1 iO +
+ VC1
S
C1 R −
VO =
VO −
1 1−k
2 VI
and FIGURE 14.55 P/O CBC elementary circuit.
IO = (1 − k)2 II The voltage transfer gain is
P/O CBC elementary circuit is shown in Fig. 14.55. Its output voltage and current are
VO M2 = = VI
1 VO = VI 1−k
1 1−k
ε=
IO = (1 − k)II
VO 1 = VI 1−k
vO /2 k = VO 2RfC2
(14.155) VO =
The variation ratio of the output voltage vO is
1 1−k
3 VI
and vO /2 k ε= = VO 2RfC1
iIN
(14.156)
L1
D1
+ VIN −
IO = (1 − k)3 II
L2
V1
+
D2 C1
−
VC1
D3
C2
S
+ −
iO + R VC2
VO −
FIGURE 14.56 P/O CBC twostage circuit.
D3
+ VIN −
(14.157)
(14.158)
P/O CBC threestage circuit is shown in Fig. 14.57. Its output voltage and current are
The voltage transfer gain is
iIN
2
The variation ratio of the output voltage vO is
and
ME =
L1
D1
D2 C1
L2
V1
L3
D5
D4
iO + +
+
+ −
V2
VC1
C2 −
VC2
S
FIGURE 14.57 P/O CBC threestage circuit.
C3 −
R VC3
VO −
296
F. L. Luo and H. Ye iIN
+ VIN −
D1
L1
+ VC1 −
D11
D12
+ VC11 C1 −
C11
P/O CBC additional twostage circuit is shown in Fig. 14.59. Its output voltage and current are iO
C12 S
+ R VC12 −
+
1 VO = 2 1−k
VO −
2 VI
and FIGURE 14.58 P/O CBC additional circuit.
IO =
(1 − k)2 II 2
The voltage transfer gain is The voltage transfer gain is M3 =
VO = VI
1 1−k
3
MA2 (14.159)
2 VO 1 = =2 VI 1−k
The variation ratio of the output voltage vO is
The variation ratio of the output voltage vO is ε=
vO /2 k ε= = VO 2RfC3
(14.160)
P/O CBC additional circuit is shown in Fig. 14.58. Its output voltage and current are VO =
(14.163)
vO /2 k = VO 2RfC12
(14.164)
P/O CBC additional threestage circuit is shown in Fig. 14.60. Its output voltage and current are
1 VO = 2 1−k
2 VI 1−k
3 VI
and
and 1−k IO = II 2
IO =
The voltage transfer gain is
The voltage transfer gain is VO 2 MA = = VI 1−k
MA3
(14.161)
vO /2 k = VO 2RfC12
iIN
L1
ε=
(14.162)
D1
D3
L2
D2
−
C1
D11 + VC11 −
+ VIN
3 VO 1 = =2 VI 1−k
(14.165)
The variation ratio of the output voltage vO is
The variation ratio of the output voltage vO is ε=
(1 − k)3 II 2
+ VC1 −
S
C2
+ VC2 −
vO /2 k = VO 2RfC12
D12 iO C11 C12
+ −
FIGURE 14.59 P/O CBC additional twostage circuit.
R VC12
+ VO −
(14.166)
14
297
DC/DC Conversion Technique and 12 Series Luoconverters L3
D3 V2 iIN
L1
D1 V1
L2
D5 V3 D11
D12 iO
D4
+
+ VC11 −
C11 D2
VIN
+ VC1 −
C1
−
C2
+ VC2 −
S
C3
C12
+ VC3 −
R
+
VC12
−
+ VO −
FIGURE 14.60 P/O CBC additional threestage circuit.
14.5.4 N/O Cascade Boostconverters +
There are several subseries of N/O CBC: • • • • •
iIN
Main series; Additional series; Double series; Triple series; Multiple series.
+
L2 D3
S
VIN
D2
L1
R
−
We only introduce three circuits of main series and additional series. N/O CBC elementary circuit is shown in Fig. 14.61. Its output voltage and current are
1 k VO = VI − 1 VI = 1−k 1−k
N/O CBC twostage circuit is shown in Fig. 14.62. Its output voltage and current are
VO =
IO =
1−k II k
iO − VO +
FIGURE 14.62 N/O CBC twostage circuit.
and
1 1−k
2
− 1 VI
and
The voltage transfer gain is
II
IO =
2 1/(1 − k) − 1
VO k ME = = VI 1−k
(14.167) The voltage transfer gain is
The variation ratio of the output voltage vO is ε=
−
D1
+ C − 2
C1
vO /2 k = VO 2RfC1
(14.168)
M2 =
VO = VI
1 1−k
2 −1
(14.169)
The variation ratio of the output voltage vO is ε=
C1 iIN + VIN
k vO /2 = VO 2RfC2
(14.170)
D1
N/O CBC threestage circuit is shown in Fig. 14.63. Its output voltage and current are
S L1
R
VO
−
VO = FIGURE 14.61 N/O CBC elementary circuit.
1 1−k
3
− 1 VI
298
F. L. Luo and H. Ye
+ C − 2
+ iIN
−
D1
+
C1 L2
L3
D3
S
VIN
+ C − 3 iO
D5
− VO +
D2
L1
R
D4
−
FIGURE 14.63 N/O CBC threestage circuit.
and
The voltage transfer gain is II
IO =
1/(1 − k)
3
MA =
−1
VO 1+k = VI 1−k
(14.173)
The variation ratio of the output voltage vO is The voltage transfer gain is VO M3 = = VI
1 1−k
ε=
3 −1
(14.171)
vO /2 k = VO 2RfC3
2 1 VO = 2 − 1 VI 1−k
(14.172) and
N/O CBC additional circuit is shown in Fig. 14.64. Its output voltage and current are VO =
2 1+k − 1 VI = VI 1−k 1−k
IO =
MA2
+ VIN −
D1
2 2 1/(1 − k) − 1
2 VO 1 = =2 −1 VI 1−k
ε=
D11
C12
(14.175)
C11
3 1 VO = 2 − 1 VI 1−k
iO − R
VO +
FIGURE 14.64 N/O CBC additional circuit.
vO /2 k = 2RfC12 VO
(14.176)
N/O CBC additional threestage circuit is shown in Fig. 14.66. Its output voltage and current are
D12
S L1
II
The variation ratio of the output voltage vO is
1−k II 1+k
C1 iIN
The voltage transfer gain is
and IO =
(14.174)
N/O CBC additional twostage circuit is shown in Fig. 14.65. Its output voltage and current are
The variation ratio of the output voltage vO is ε=
vO /2 k = VO 2RfC12
and IO =
II
3 2 1/(1 − k) − 1
14
299
DC/DC Conversion Technique and 12 Series Luoconverters
C1 iIN +
C2
L2
D1
D3
C12
D11
D12 iO −
S D2
VIN
L1
R
C11
−
VO +
FIGURE 14.65 N/O CBC additional twostage circuit.
C1 iIN
D1 S
+ VIN
L2
C2 D3
C3 L3
C12
D11
D5
D12 iO −
D2 L1
D4
−
R
C11
VO +
FIGURE 14.66 N/O CBC additional threestage circuit.
The voltage transfer gain is MA3 =
3 VO 1 =2 −1 VI 1−k
voltage transfer gain (14.177)
(14.178)
14.6 Ultralift Luoconverters Ultralift (UL) Luoconverter performs very high voltage transfer gain conversion. Its voltage transfer gain is the product of those of VL Luoconverter and SL Luoconverter. We know that the gain of P/O VL Luoconverters (as in Eq. (14.52)) is M=
VO k = VI 1−k
The voltage transfer gain of P/O SL Luoconverters is
The variation ratio of the output voltage vO is vO /2 k ε= = VO 2RfC12
ME =
VO k h(n) [n + h(n)] = VI 1−k
where n is the stage number, h(n) (as in Eq. (14.56)) is the Hong function. 1 n=0 h(n) = 0 n>0 (from Eq. (14.32)) n = 0 for the elementary circuit with the
VO M= = VI
j +2−k 1−k
n (14.179)
where n is the stage number, j is the multipleenhanced number. n = 1 and j = 0 for the elementary circuit with gain (as in Eq. (14.131)) ME =
VO 2−k = VI 1−k
The circuit diagram of UL Luoconverter is shown in Fig. 14.67a, which consists of one switch S, two inductors L1 and L2 , two capacitors C1 and C2 , three diodes, and the load R. Its switchon equivalent circuit is shown in Fig. 14.67b. Its switchoff equivalent circuit for the continuous conduction mode is shown in Fig. 14.67c and switchoff equivalent circuit for the discontinuous conduction mode is shown in Fig. 14.67d.
14.6.1 Continuous Conduction Mode Referring to Figs. 14.67b and c, we have got the current iL1 increases with the slope +VI /L1 during switch on, and
300
F. L. Luo and H. Ye iI
S
D3
D1
VI
L1
−
iL2
− VC1 + iL1 C1
+
L2
V1
iC1
iO
D2
iI −
− VC2 + C2
R iC2
− VC1 + iL1 C1
+
VO
VI
+
L1
−
(a)
V1
L1
− VC1 + C1
iL1
iO
L2
V1
iL2
− VC2 + C2
iC1
− R iC2
VO +
(b)
iO
L2 iL2 iC1
− VC2 + C2
− R iC2
VO
− VC1 + C1 i
L1
+
iO
L2
V1
iL2 iC1
L1
(c)
−
− VC2 + C2
R iC2
VO +
(d)
FIGURE 14.67 Ultralift (UL) Luoconverter: (a) circuit diagram; (b) switch on; (c) switch off in CCM; and (d) switch off in DCM.
decreases with the slope −V1 /L1 during switch off. In the steady state, the current increment is equal to the decrement in a whole period T. The relation below is obtained kT
VI V1 = (1 − k)T L1 L1
(14.180)
k VI 1−k
(14.181)
Thus, VC1 = V1 =
The current iL2 increases with the slope +(VI − V1 )/L2 during switch on, and decreases with the slope −(V1 − VO )/L2 during switch off. In the steady state, the current increment is equal to the decrement in a whole period T. We obtain the relation below V I + V1 V O − V1 kT = (1 − k)T L2 L2 VO = VC2
(1 − k)2 II k(2 − k)
k Buck Boost Buck–Boost VL Luoconverter SL Luoconverter UL Luoconverter
0.2 0.2 1.25 0.25 0.25 2.25 0.56
0.33 0.33 1.5 0.5 0.5 2.5 1.25
0.5 0.5 2 1 1 3 3
0.67 0.67 3 2 2 4 8
0.8 0.8 5 4 4 6 24
0.9 0.9 10 9 9 11 99
VL Luoconverter and SL Luoconverter. We list the transfer gains of various converters in Table 14.3 for reference. The variation of inductor current iL1 is iL1 = kT
(14.182)
2−k k 2−k k(2 − k) = VI V1 = VI = 1−k 1−k 1−k (1 − k)2 (14.183) IO =
TABLE 14.3 Comparison of various converters gains
VI L1
(14.186)
and its variation ratio is ξ1 =
(1 − k)4 TR iL1 /2 k(1 − k)2 TVI k(1 − k)2 TR = = = IL1 2L1 I2 2L1 M 2(2 − k)fL1 (14.187)
(14.184) The variation of inductor current iL2 is
The voltage transfer gain is VO k(2 − k) k 2−k M= = = = ME−VL × ME−SL 2 VI (1 − k) 1−k 1−k (14.185) From Eq. (14.185) we can see that the voltage transfer gain of UL Luoconverter is very high which is the product of those of
iL2 =
kTVI (1 − k)L2
(14.188)
and its variation ratio is ξ2 =
(1 − k)2 TR iL2 /2 kTVI kTR = = = IL2 2L2 I2 2L2 M 2(2 − k)fL2
(14.189)
14
301
DC/DC Conversion Technique and 12 Series Luoconverters
The variation of capacitor voltage vC1 is vC1 =
QC1 kTIL2 kTIO = = C1 C1 (1 − k)C1
Thus,
and its variation ratio is σ1 =
VC1 = V1 =
(14.190)
kT
The variation of capacitor voltage vC2 is vC2 =
QC2 kTIO = C2 C2
VI + V1 V O − V1 = (1 − k)T L2 L2
VO = VC2 = (14.192)
vC2 /2 kTIO k ε = σ2 = = = VC2 2VO C2 2fC2 R
MDCM = (14.193)
From the analysis and calculations, we can see that all variations are very small. A design example is that VI = 10 V, L1 = L2 = 1 mH, C1 = C2 = 1 µF, R = 3000 , f = 50 kHz, and conduction duty cycle k varies from 0.1 to 0.9. We then obtain the output voltage variation ratio ε, which is less than 0.003. The output voltage is very smooth DC voltage nearly no ripple.
14.6.2 Discontinuous Conduction Mode Referring to Fig. 14.67d, we have got the current iL1 decreases to zero before t = T , i.e. the current becomes zero before next time the switch turns on. The DCM operation condition is deﬁned as ξ≥1
ZN =
R fL1
(14.195)
We deﬁne the ﬁlling factor m to describe the current exists time. For DCM operation, 0 < m ≤ 1, 1 2L1 G 2(2 − k) = = 2 ξ1 k(1 − k) TR (1 − k)4 ZN VI V1 = (1 − k)mT L1 L1
(14.196)
VO k(2 − k) MCCM = = 2 m VI m(1 − k)
with m < 1
Multiplequadrant operating converters are the secondgeneration converters. These converters usually perform between two voltage sources: V1 and V2 . Voltage source V1 is proposed positive voltage and voltage V2 is the load voltage. In the investigation both voltages are proposed constant voltage. Since V1 and V2 are constant values, voltage transfer gain is constant. Our interesting research will concentrate the working current, minimum conduction duty kmin , and the power transfer efﬁciency η. Multiplequadrant operating Luoconverters are the secondgeneration converters and they have three modes:
•
The normalized impedance ZN is,
(14.199)
14.7 Multiplequadrant Operating Luoconverters
•
(14.194)
2−k k(2 − k) V1 = VI 1−k m(1 − k)2
(14.200)
or (1 − k)4 TR k(1 − k)2 TR ξ1 = = ≥1 2L1 M 2(2 − k)fL1
(14.198)
The voltage transfer gain in DCM is higher than that in CCM.
and its variation ratio is
kT
(14.197)
We ﬁnally obtain the relation below
vC1 /2 kTIO k(2 − k) = = (14.191) VC1 2(1 − k)V1 C1 2(1 − k)2 fC1 R
m=
k VI (1 − k)m
•
Twoquadrant DC/DC Luoconverter in forward operation; Twoquadrant DC/DC Luoconverter in reverse operation; Fourquadrant DC/DC Luoconverter.
The twoquadrant DC/DC Luoconverter in forward operation has been derived from the positive output Luoconverter. It performs in the ﬁrstquadrant QI and the secondquadrant QII corresponding to the DC motor forward operation in motoring and regenerative braking states. The twoquadrant DC/DC Luoconverter in reverse operation has been derived from the N/O Luoconverter. It performs in the thirdquadrant QIII and the fourthquadrant QIV corresponding to the DC motor reverse operation in motoring and regenerative braking states. The fourquadrant DC/DC Luoconverter has been derived from the double output Luoconverter. It performs fourquadrant operation corresponding to the DC motor forward
302
F. L. Luo and H. Ye
and reverse operation in motoring and regenerative braking states. In the following analysis the input source and output load are usually constant voltages as shown, V1 and V2 . Switches S1 and S2 in this diagram are power metal oxide semiconductor ﬁeld effect transistor (MOSFET) devices, and they are driven by a PWM switching signal with repeating frequency f and conduction duty k. In this paper the switch repeating period is T = 1/f , so that the switchon period is kT and switchoff period is (1 − k)T . The equivalent resistance is R for each inductor. During switchon the voltage drop across the switches and diodes are VS and VD respectively.
The minimum conduction duty k corresponding to I2 = 0 is kmin =
V2 V1 + V 2 − V S − V D
(14.203)
The power transfer efﬁciency is ηA = =
P O V 2 I2 = PI V 1 I1
1 1+ (VS +VD )/V2 (k/(1−k))+(RI2 /V2 ) 1+((1−k)/k)2
(14.204) The variation ratio of capacitor voltage vC is
14.7.1 Forward Twoquadrant DC/DC Luoconverter
ρ=
Forward Twoquadrant (F 2Q) Luoconverter is shown in Fig. 14.68. The source voltage (V1 ) and load voltage (V2 ) are usually considered as constant voltages. The load can be a battery or motor back electromotive force (EMF). For example, the source voltage is 42 V and load voltage is +14 V. There are two modes of operation: 1. Mode A (Quadrant I): electrical energy is transferred from source side V1 to load side V2 ; 2. Mode B (Quadrant II): electrical energy is transferred from load side V2 to source side V1 . Mode A: The equivalent circuits during switchon and off periods are shown in Figs. 14.69a and b. The typical output voltage and current waveforms are shown in Fig. 14.69c. We have the output current I2 as I2 =
1−k I1 k
(14.201)
vC /2 (1 − k)I2 = VC 2fC(V1 − RI2 (1/(1 − k)))
The variation ratio of inductor current iL1 is ξ1 =
iL1 /2 V1 − VS − RI1 =k IL1 2fL1 I1
ξ2 =
iL2 /2 V1 − VS − RI1 =k IL2 2fL2 I2
S1
C − + VC
L2
ζD2 =
V1 − VS − RI1 iD2 /2 V1 − VS − RI1 =k = k2 IL1 + IL2 2fL(I1 + I2 ) 2fLI1 (14.208)
If the diode current becomes zero before S1 switch on again, the converter works in discontinuous region. The condition is
+ −
L1
S2 D2
V1
i.e. k 2 =
R
+ V2 −
R
FIGURE 14.68 Forward twoquadrant operating Luoconverter.
2fLI1 V1 − VS − RI1
(14.209)
Mode B: The equivalent circuits during switchon and off periods are shown in Figs. 14.70a and b. The typical output voltage and current waveforms are shown in Fig. 14.70c. We have the output current I1 as I1 =
I2
D1 I1
(14.202)
(14.207)
The variation ratio of diode current iD2 is
ζD2 = 1, V1 − VS − VD − V2 ((1 − k)/k) R (k/(1 − k)) + ((1 − k)/k)
(14.206)
The variation ratio of inductor current iL2 is
and I2 =
(14.205)
1−k I2 k
(14.210)
and I1 =
V2 − (V1 + VS + VD )((1 − k)/k) R (k/(1 − k)) + ((1 − k)/k)
(14.211)
The minimum conduction duty k corresponding to I1 = 0 is kmin =
V1 + V S + V D V1 + V 2 + V S + V D
(14.212)
14
303
DC/DC Conversion Technique and 12 Series Luoconverters i iL1 −
S1
C
C + VC
L2 iL2
S2 + V1 −
iL1
−
R +
L1
V2 −
D2 R
+ VC
L2
iL1
0
+
D2
L1
iL2 R V2 −
iL2
t
v vC
R 0 (a)
t
(b)
(c)
FIGURE 14.69 Mode A: (a) switch on; (b) switch off; and (c) waveforms.
i iL1 C S1
−
D1 + V1 −
iL2
C
+ VC
L2
R + V2 −
S2
L1 iL1
−
D1
+ VC
L2
iD1
+ V1 iL1 −
R
iL2 + V2 −
L1
0
t
v vC
iL2 R
R
0 (a)
(b)
t (c)
FIGURE 14.70 Mode B: (a) switch on; (b) switch off; and (c) waveforms.
The power transfer efﬁciency ηB = =
The variation ratio of diode current iD1 is
PO V1 I1 = PI V2 I2
ζD1 =
1 1 + ((VS + VD )/V1 ) + (RI1 /V1 )[1 + ((1 − k)/k)2 ] (14.213)
V2 − VS − RI2 iD2 /2 V2 − VS − RI2 =k = k2 IL1 + IL2 2fL(I1 + I2 ) 2fLI2 (14.217)
If the diode current becomes zero before S2 switch on again, the converter works in discontinuous region. The condition is
The variation ratio of capacitor voltage vC is ρ=
vC /2 kI1 = VC 2fC[(V2 /(1 − k)) − V1 − RI1 (k/(1 − k)2 )] (14.214)
V2 − VS − RI2 iL1 /2 =k 2fL1 I1 IL1
(14.215)
The variation ratio of inductor current iL2 is ξ2 =
iL2 /2 V2 − VS − RI2 =k IL2 2fL2 I2
i.e. k 2 =
2fLI2 V2 − VS − RI2
(14.218)
14.7.2 Twoquadrant DC/DC Luoconverter in Reverse Operation
The variation ratio of inductor current iL1 is ξ1 =
ζD1 = 1,
(14.216)
Reverse twoquadrant operating (R 2Q) Luoconverter is shown in Fig. 14.71, and it consists of two switches with two passive diodes, two inductors and one capacitor. The source voltage (V1 ) and load voltage (V2 ) are usually considered as constant voltages. The load can be a battery or motor back EMF. For example, the source voltage is 42 V and load voltage
304
F. L. Luo and H. Ye
The power transfer efﬁciency is
I1
S1
S2
D1
D2 L1
+ V1 −
L2
R
iL2 − VC +
C
ηC =
− V2 +
R
PO V2 I2 = PI V1 I1 1 1 + ((VS + VD )/V2 )(k/(1 − k)) + (RI2 /V2 )[1 + (1/(1 − k))2 ]
=
(14.222)
I2
The variation ratio of capacitor voltage vC is FIGURE 14.71 Reverse twoquadrant operating Luoconverter.
ρ= is −14 V. There are two modes of operation:
The variation ratio of inductor current iL1 is
1. Mode C (Quadrant III): electrical energy is transferred from source side V1 to load side −V2 ; 2. Mode D (Quadrant IV): electrical energy is transferred from load side −V2 to source side V1 .
ξ1 =
Mode C: The equivalent circuits during switchon and off periods are shown in Figs. 14.72a and b. The typical output voltage and current waveforms are shown in Fig. 14.72c. We have the output current I2 as I2 =
1−k I1 k
vC /2 kI2 = VC 2fC (k/(1 − k))V1 − ((RI2 )/(1 − k)2 ) (14.223)
iL1 /2 V1 − VS − RI1 =k IL1 2fL1 I1
(14.224)
The variation ratio of inductor current iD2 is ζD2 = ξ1 =
iD2 /2 V1 − VS − RI1 =k IL1 2fL1 I1
(14.225)
(14.219) The variation ratio of inductor current iL2 is
and ξ2 =
V1 − VS − VD − V2 ((1 − k)/k) I2 = R [(1/(k(1 − k))) + ((1 − k)/k)]
(14.220)
V2 V1 + V 2 − V S − V D
(14.226)
If the diode current becomes zero before S1 switch on again, the converter works in discontinuous region. The condition is
The minimum conduction duty k corresponding to I2 = 0 is kmin =
iL2 /2 k = I2 16f 2 CL2
ζD2 = 1,
(14.221)
i.e. k =
i
2fL1 I1 V1 − VS − RI1
(14.227)
iL1 iL2
S1 + V1 iL1 −
L2 L1
R
− C VC +
R
− V2 + iL2
(a)
L2
D2
L1
R
− C VC + iL1
− V2 +
0
t
v VC A
iL2
R (b)
0
FIGURE 14.72 Mode C: (a) switch on; (b) switch off; and (c) waveforms.
(c)
t
14
305
DC/DC Conversion Technique and 12 Series Luoconverters i iL1 iL2 D1
L2
S2
L1 + V1 − R
C
− V + C
R − V2 +
iL2
i + L1 V1 −
0
L2
D1 L1
− C +VC
t
R iL2
v
VC
− V2 +
B
R
iL1
0 (a)
t
(b)
(c)
FIGURE 14.73 Mode D: (a) switch on; (b) switch off; and (c) waveforms.
Mode D: The equivalent circuits during switchon and off periods are shown in Figs. 14.73a and b. The typical output voltage and current waveforms are shown in Fig. 14.73c. We have the output current I1 as I1 =
1−k I2 k
(14.228)
And the variation ratio of inductor current iD1 is ζD1 = ξ1 =
iD1 /2 V2 − VS − RI2 =k IL1 2fL1 I2
The variation ratio of inductor current iL2 is ξ2 =
and I1 =
V2 − (V1 + VS + VD )((1 − k)/k) R[(1/(k(1 − k))) + (k/(1 − k))]
(14.229)
The minimum conduction duty k corresponding to I1 = 0 is kmin =
V1 + V S + V D V1 + V 2 + V S + V D
1 1 + ((VS + VD )/V1 ) + (RI1 /V1 )[(1/(1 − k)2 ) + (k/(1 − k))2 ]
(14.231) The variation ratio of capacitor voltage vC is kI1 vC /2 = VC 2fC [((1 − k)/k)V1 + ((RI1 )/(k(1 − k)))] (14.232)
The variation ratio of inductor current iL1 is ξ1 =
iL1 /2 V2 − VS − RI2 = (1 − k) IL1 2fL1 I1
(14.235)
If the diode current becomes zero before S2 switch on again, the converter works in discontinuous region. The condition is ζD1 = 1,
i.e. k =
2fL1 I2 V2 − VS − RI2
(14.236)
14.7.3 Fourquadrant DC/DC Luoconverter
PO V1 I1 ηD = = PI V2 I2
ρ=
iL2 /2 1−k = I2 16f 2 CL2
(14.230)
The power transfer efﬁciency is
=
(14.234)
(14.233)
Fourquadrant DC/DC Luoconverter is shown in Fig. 14.74, which consists of two switches with two passive diodes, two inductors, and one capacitor. The source voltage (V1 ) and load voltage (V2 ) are usually considered as constant voltages. The load can be a battery or motor back EMF. For example, the source voltage is 42 V and load voltage is ±14 V. There are four modes of operation: 1. Mode A (Quadrant I): electrical energy is transferred from source side V1 to load side V2 ; 2. Mode B (Quadrant II): electrical energy is transferred from load side V2 to source side V1 ; 3. Mode C (Quadrant III): electrical energy is transferred from source side V1 to load side −V2 ; 4. Mode D (Quadrant IV): electrical energy is transferred from load side −V2 to source side V1 . Each mode has two states: “on” and “off.” Usually, each state is operating in different conduction duty k. The switches
306
F. L. Luo and H. Ye C S1
− + VC
L2
I2
D1 L1
I1
S1
R
S2
+ V1 −
V2 −
D2
R iL2
D1 I1
+
L2
S2 D2 L1
+ V1 −
− V + C
C
− V2 + I2
R
R
(b)
(a)
FIGURE 14.74 Fourquadrant operating Luoconverter: (a) circuit 1 and (b) circuit 2.
are the power MOSFET devices. The circuit 1 in Fig. 14.74 implements Modes A and B, and the circuit 2 in Fig. 14.74 implements Modes C and D. Circuits 1 and 2 can changeover by auxiliary switches (not in the ﬁgure). Mode A: During stateon switch S1 is closed, switch S2 and diodes D1 and D2 are not conducted. In this case inductor currents iL1 and iL2 increase, and i1 = iL1 + iL2 . During stateoff switches S1 , S2 , and diode D1 are off and diode D2 is conducted. In this case current iL1 ﬂows via diode D2 to charge capacitor C, in the meantime current iL2 is kept to ﬂow through load battery V2 . The freewheeling diode current iD2 = iL1 + iL2 . Mode A implements the characteristics of the buck–boost conversion. Mode B: During stateon switches S2 is closed, switch S1 and diodes D1 and D2 are not conducted. In this case inductor current iL2 increases by biased V2 , inductor current iL1 increases by biased VC . Therefore capacitor voltage VC reduces. During stateoff switches S1 , S2 , and diode D2 are not on, and only diode D1 is on. In this case source current i1 = iL1 + iL2 which is a negative value to perform the regenerative operation. Inductor current iL2 ﬂows through capacitor C, it is charged by current iL2 . After capacitor C, iL2 then ﬂows through the source V1 . Inductor current iL1 ﬂows through the source V1 as well via diode D1 . Mode B implements the characteristics of the boost conversion. Mode C: During stateon switch S1 is closed, switch S2 and diodes D1 and D2 are not conducted. In this case inductor
TABLE 14.4
14.8 Switchedcapacitor Multiquadrant Luoconverters Switchedcomponent converters are the thirdgeneration converters. These converters are made of only inductor
Switch’s status (the blank status means OFF)
Switch or diode
Mode A (QI) Stateon
Mode B (QII)
Stateoff
Circuit S1 D1 S2 D2
currents iL1 and iL2 increase, and i1 = iL1 . During stateoff switches S1 , S2 , and diode D1 are off and diode D2 is conducted. In this case current iL1 ﬂows via diode D2 to charge capacitor C and the load battery V2 via inductor L2 . The freewheeling diode current iD2 = iL1 = iC + i2 . Mode C implements the characteristics of the buck–boost conversion. Mode D: During stateon switches S2 is closed, switch S1 and diodes D1 and D2 are not conducted. In this case inductor current iL1 increases by biased V2 , inductor current iL2 decreases by biased (V2 − VC ). Therefore capacitor voltage VC reduces. Current iL1 = iC−on + i2 . During stateoff switches S1 , S2 , and diode D2 are not on, and only diode D1 is on. In this case source current i1 = iL1 which is a negative value to perform the regenerative operation. Inductor current i2 ﬂows through capacitor C that is charged by current i2 , i.e. iC−off = i2 . Mode D implements the characteristics of the boost conversion. Summary: The switch status is shown in Table 14.4. The operation of all modes A, B, C, and D is same to the description in Sections 14.7.1 and 14.7.2.
Stateon
Stateoff
Mode C (QIII) Stateon
Stateoff
Circuit 1
Mode D (QIV) Stateon
Stateoff
Circuit 2
ON
ON ON
ON
ON ON
ON ON
14
307
DC/DC Conversion Technique and 12 Series Luoconverters S1
S2
D1
D3
D2
S3
D4
S4
iL iH
+
C1
VH
+ −
D5
S5
C2
+
D6
−
S6
C3
+ −
S7
+ VL −
− S8
D8
S9
D9
S10
D10
FIGURE 14.75 Twoquadrant switchedcapacitor DC/DC Luoconverter.
or capacitors. They usually perform in the systems between two voltage sources: V1 and V2 . Voltage source V1 is proposed positive voltage and voltage V2 is the load voltage that can be positive or negative. In the investigation both voltages are proposed constant voltage. Since V1 and V2 are constant values, so that voltage transfer gain is constant. Our interesting research will concentrate on the working current and the power transfer efﬁciency η. The resistance R of the capacitors and inductor has to be considered for the power transfer efﬁciency η calculation. Reviewing the papers in the literature, we can ﬁnd that almost of the papers investigating the switchedcomponent converters are working in singlequadrant operation. Professor Luo and colleagues have developed this technique into multiquadrant operation. We describe these in this and next sections. Switchedcapacitor multiquadrant Luoconverters are the thirdgeneration converters, and they are made of only capacitors. Because these converters implement voltagelift and currentampliﬁcation techniques, they have the advantages of high power density, high power transfer efﬁciency, and low EMI. They have two modes:
polarity. It performs fourquadrant operation corresponding to the DC motor forward and reverse operation in motoring and regenerative braking states. From the analysis and calculation, the conduction duty k does not affect the power transfer efﬁciency. It affects the input and output power in a small region. The maximum output power corresponds at k = 0.5.
14.8.1 Twoquadrant Switchedcapacitor DC/DC Luoconverter This converter is shown in Fig. 14.75. It consists of nine switches, seven diodes, and three capacitors. The high source voltage VH and low load voltage VL are usually considered as constant voltages, e.g. the source voltage is 48 V and load voltage is 14 V. There are two modes of operation: • •
Mode A (Quadrant I): electrical energy is transferred from VH side to VL side; Mode B (Quadrant II): electrical energy is transferred from VL side to VH side.
Each mode has two states: “on” and “off.” Usually, each state is operating in different conduction duty k. The switch• Twoquadrant switchedcapacitor DC/DC Luoconverter; ing period is T where T = 1/f , where f is the switching • Fourquadrant switchedcapacitor DC/DC Luoconverter. frequency. The switches are the power MOSFET devices. The The twoquadrant switchedcapacitor DC/DC Luoconverter parasitic resistance of all switches is rS . The equivalent resisin forward operation has been derived for the energy transmis tance of all capacitors is rC and the equivalent voltage drop of sion of a dualvoltage system in twoquadrant operation. The all diodes is VD . Usually we select the three capacitors having both, source and load voltages are positive polarity. It performs same capacitance C = C1 = C2 = C3 . Some reference data are in the ﬁrstquadrant QI and the secondquadrant QII corre useful: rS = 0.03 , rC = 0.02 , and VD = 0.5 V, f = 5 kHz, sponding to the DC motor forward operation in motoring and and C = 5000 µF. The switch’s status is shown in Table 14.5. For Mode A, stateon is shown in Fig. 14.76a: switches regenerative braking states. The fourquadrant switchedcapacitor DC/DC Luo S1 and S10 are closed and diodes D5 and D5 are conconverter has been derived for the energy transmission of a ducted. Other switches and diodes are open. In this case dualvoltage system in fourquadrant operation. The source capacitors C1 , C2 , and C3 are charged via the circuit VH – voltage is positive and load voltage can be positive or negative S1 –C1 –D5 –C2 –D6 –C3 –S10 , and the voltage across capacitors
308
F. L. Luo and H. Ye
TABLE 14.5
Switch’s status (the blank status means OFF)
Switch or diode
Mode A Stateon
S1 D1 S2 ,S3 ,S4 D2 ,D3 ,D4 S5 ,S6 ,S7 D5 ,D6 S8 ,S9 S10 D8 ,D9 ,D10
The variation of the voltage across capacitor C1 is:
Mode B
Stateoff
Stateon
vC1 =
Stateoff
ON
=
ON ON
k(VH − 3VC1 − 2VD ) fCRAN 2.4k(1 − k)(VH − 3VL − 5VD ) (2.4 + 0.6k)fCRAN
(14.237)
ON ON
After calculation,
ON ON ON
ON
VC1 =
ON
k(VH − 2VD ) + 2.4(1 − k)(VL + VD ) 2.4 + 0.6k
(14.238)
The average output current is
IL =
C1 , C2 , and C3 is increasing. The equivalent circuit resistance is RAN = (2rS + 3rC ) = 0.12 , and the voltage deduction is 2VD = 1 V. Stateoff is shown in Fig. 14.76b: switches S2 , S3 , and S4 are closed and diodes D8 , D9 , and D10 are conducted. Other switches and diodes are open. In this case capacitor C1 (C2 and C3 ) is discharged via the circuit S2 (S3 and S4 )– VL –D8 (D9 and D10 )–C1 (C2 and C3 ), and the voltage across capacitor C1 (C2 and C3 ) is decreasing. Mode A implements the currentampliﬁcation technique. The voltage and current waveforms are shown in Fig. 14.76c. All three capacitors are charged in series during stateon. The input current ﬂows through three capacitors and the charges accumulated on the three capacitors should be the same. These three capacitors are discharged in parallel during stateoff. Therefore, the output current is ampliﬁed by three times.
3 T
T iC1 (t )dt ≈ 3(1 − k)
VC1 − VL − VD RAF
(14.239)
kT
The average input current is 1 IH = T
kT iC1 (t )dt ≈ k 0
VH − 3VC1 − 2VD RAN
(14.240)
Therefore, we have 3IH = IL . Output power is PO = VL IL = 3(1 − k)VL
VC1 − VL − VD RAF
(14.241)
vC1 VC1 S1, S10, D5, D6 On S1 iC1
S2, S3, S4, D8,D9, D10 On
+ −
C1 D5
+
C2
VH
D6
−
C3
iC1
+ − + −
+
+
VL
VH
−
−
S3
S2
C1 +C2 − D8
iC2
iC3
kT
T
+
VL
−
−
−
S10
(a)
(b)
t
+
+ C3 D10
T
iC1
S4
D9
kT
(c)
FIGURE 14.76 Mode A operation: (a) stateon; (b) stateoff; and (c) voltage and current waveforms.
t
14
309
DC/DC Conversion Technique and 12 Series Luoconverters
Input power
After calculation
PI = VH IH = kVH
VH − 3VC1 − VD RAN
VC1 = k(VL − VD ) +
(14.242)
3VL PO 1 − k 3VL VC1 − VL − VD RAN = = VH PI k VH VH − 3VC1 − VD RAF (14.243)
0
≈ 3k
For Mode B, stateon is shown in Fig. 14.77a: switches S8 , S9 , and S10 are closed and diodes D2 , D3 , and D4 are conducted. Other switches and diodes are off. In this case all three capacitors are charged via each circuit VL –D2 (and D3 , D4 )– C1 (and C2 , C3 )–S8 (and S9 , S10 ), and the voltage across three capacitors are increasing. The equivalent circuit resistance is RBN = rS + rC and the voltage deduction is VD in each circuit. Stateoff is shown in Fig. 14.77b: switches S5 , S6 , and S7 are closed and diode D1 is on. Other switches and diodes are open. In this case all capacitors is discharged via the circuit VL –S7 –C3 –S6 –C2 –S5 –C1 –D1 –VH , and the voltage across all capacitors is decreasing. Mode B implements the voltagelift technique. The voltage and current waveforms are shown in Fig. 14.77c. All three capacitors are charged in parallel during stateon. The input voltage is applied to the three capacitors symmetrically, so that the voltages across these three capacitors should be same. They are discharged in series during stateoff. Therefore, the output voltage is lifted by three times. The variation of the voltage across capacitor C is: vC1 =
k(1 − k)[4(VL − VD ) − VH ] fCRBN
(14.245)
The average input current is kT T 1 IL = 3 iC1 (t )dt + iC1 (t )dt T
The transfer efﬁciency is ηA =
1−k (VH − VL + VD ) 3
kT
VL − VC1 − VD 3VC1 + VL − VH − VD + (1 − k) RBN RBF (14.246)
The average output current is 1 IH = T
T iC1 (t )dt ≈ (1 − k)
3VC1 + VL − VH − VD RBF
kT
(14.247) From this formula, we have 4IH = IL . Input power is P I = V L IL VL −VC −VD 3VC +VL −VH −VD = VL 3k +(1−k) RBN RBF (14.248) Output power is PO = VH IH = VH (1 − k)
(14.244)
3VC + VL − VH − VD (14.249) RBF
νC1 VC1 S8, S9, S10, D2, D3, D4 On
D4 + VL −
D3 +
C3 S10
−
S7, S6, S5, D1 On
S7
D2
C2
+
C1
−
S9
(a)
+
+
− iC1
VH
VL
−
−
C3 S6 C2
+
iC1
S5
C1 D1
kT
T
kT
T
t
+ VH
iC1
−
S8
(b)
(c)
FIGURE 14.77 Mode B operation: (a) stateon; (b) stateoff; and (c) voltage and current waveforms.
t
310
F. L. Luo and H. Ye TABLE 14.6 Switch’s status (mentioned switches are not open)
The efﬁciency is ηB =
PO VH = PI 4VL
(14.250)
14.8.2 Fourquadrant Switchedcapacitor DC/DC Luoconverter Fourquadrant switchedcapacitor DC/DC Luoconverter is shown in Fig. 14.78. Since it performs the voltagelift technique, it has a simple structure with fourquadrant operation. This converter consists of eight switches and two capacitors. The source voltage V1 and load voltage V2 (e.g. a battery or DC motor back EMF) are usually constant voltages. In this paper they are supposed to be ±21 V and ±14 V. Capacitors C1 and C2 are same and C1 = C2 = 2000 µF. The circuit equivalent resistance R = 50 m. Therefore, there are four modes of operation for this converter: 1. Mode A: energy is converted from source to positive voltage load; the ﬁrstquadrant operation, QI ; 2. Mode B: energy is converted from positive voltage load to source; the secondquadrant operation, QII ; 3. Mode C: energy is converted from source to negative voltage load; the thirdquadrant operation, QIII ; 4. Mode D: energy is converted from negative voltage load to source; the fourthquadrant operation, QIV . The ﬁrstquadrant (Mode A) is so called the forward motoring (Forw. Mot.) operation. V1 and V2 are positive, and I1 and I2 are positive as well. The secondquadrant (Mode B) is so called the forward regenerative (Forw. Reg.) braking operation. V1 and V2 are positive, and I1 and I2 are negative. The thirdquadrant (Mode C) is socalled the reverse motoring (Rev. Mot.) operation. V1 and I1 are positive, and V2 and I2 are negative. The fourthquadrant (Mode D) is socalled the reverse regenerative (Rev. Reg.) braking operation. V1 and I2 are positive, and I1 and V2 are negative. Each mode has two conditions: V1 > V2 and V1 < V2 (or V2  for QIII and QIV ). Each condition has two states: “on” and
Quadrant No. and mode
Condition
QI, Mode A Forw. Mot.
State OFF
V1 > V2 V1 < V2
S1,4,6,8 S1,4,6,8
S2,4,6,8 S2,4,7
V1 + I1 +
V2 + I2 +
QII, Mode B Forw. Reg.
V1 > V2 V1 < V2
S2,4,6,8 S2,4,6,8
S1,4,7 S1,4,6,8
V1 + I1 −
V2 + I2 −
QIII, Mode C Rev. Mot.
V1 > V2  V1 < V2 
S1,4,6,8 S1,4,6,8
S3,5,6,8 S3,5,7
V1 + I1 +
V2 − I2 −
QIV Mode D Rev. Reg.
V1 > V2  V1 < V2 
S3,5,6,8 S3,5,6,8
S1,4,7 S1,4,6,8
V1 + I1 −
V2 − I2 +
“off.” Usually, each state is operating in various conduction duty k for different currents. As usual, the efﬁciency of all SC DC/DC converters is independent from the conduction duty cycle k. The switching period is T where T = 1/f . The switch status is shown in Table 14.6. As usual, the transfer efﬁciency only relies on the ratio of the source and load voltages, and it is independent on R, C, f, and k. We select k = 0.5 for our description. Other values for the reference are f = 5 kHz, V1 = 21 V, V2 = 14 V, and total C = 4000 µF, R = 50 m. For Mode A1, condition V1 > V2 is shown in Fig. 14.78a. Since V1 > V2 , two capacitors C1 and C2 are connected in parallel. During switchon state, switches S1 , S4 , S6 , and S8 are closed and other switches are open. In this case, capacitors C1 //C2 are charged via the circuit V1 –S1 –C1 //C2 –S4 , and the voltage across capacitors C1 and C2 is increasing. During switchoff state, switch S2 , S4 , S6 , and S8 are closed and other switches are open. In this case capacitors C1 //C2 are discharged via the circuit S2 –V2 –S4 –C1 //C2 , and the voltage across capacitors C1 and C2 is decreasing. Capacitors C1 and C2 transfer the energy from the source to the load. The average capacitor voltage VC = kV1 + (1 − k)V2
S6 i1 V1
+ −
S3
+ VC1 C1 −
iC1
Load side
ON
S2
S1
Source side
i2
S5
S7
C2
S8 S4
FIGURE 14.78 Fourquadrant sc DC/DC Luoconverter.
+ _
V2
(14.251)
14
311
DC/DC Conversion Technique and 12 Series Luoconverters vC1 S1
S2 +
+
V2
V1
S6
V1
+ + VC1 − −
C1
S2
S1 C2 S5
S7 S8 S4
−
VC1
S6 + VC1 −
C1
C2 S5
S7
+
S8
−
iC1
V2
T
i1
S4
−
kT
kT
T i2
(i)
FIGURE 14.78a (iii) waveforms.
(ii)
Mode A1 (QI): forward motoring with V1 > V2 : (i) switch on: S1 , S4 , S6 , and S8 on; (ii) switch off: S2 , S4 , S6 , and S8 , on; and
The average current is 1 I2 = T
(iii)
T iC (t )dt ≈ (1 − k)
V C − V2 R
(14.252)
kT
and 1 I1 = T
kT iC (t )dt ≈ k
V1 − VC R
V1 –S1 –C1 //C2 –S4 , and the voltage across capacitors C1 and C2 is increasing. During switchoff state, switches S2 , S4 , and S7 are closed and other switches are open. In this case, capacitors C1 and C2 are discharged via the circuit S2 –V2 –S4 –C1 –S7 –C2 , and the voltage across capacitor C1 and C2 is decreasing. Capacitors C1 and C2 transfer the energy from the source to the load. The average capacitor voltage is
(14.253)
VC =
0
(14.255)
The average current is
The transfer efﬁciency is ηA1
0.5V1 + V2 = 11.2 2.5
PO 1 − k V 2 VC − V 2 V2 = = = k V1 V1 − V C V1 PI
1 I2 = T
(14.254)
T iC (t )dt ≈ (1 − k)
2VC − V2 R
(14.256)
kT
For Mode A2, condition V1 < V2 is shown in Fig. 14.78b. Since V1 < V2 , two capacitors C1 and C2 are connected in parallel during switch on and in series during switch off. This is socalled the voltagelift technique. During switchon state, switches S1 , S4 , S6 , and S8 are closed and other switches are open. In this case, capacitors C1 //C2 are charged via the circuit
and 1 I1 = T
kT iC (t )dt ≈ k
V1 − VC R
(14.257)
0
vC1 S1
S2 +
S6 V1
+ + VC1 − −
C1
S2
S1
C2 S5
S7 S8 S4
V2
−
+
V1
+ VC1 −
VC1
S6 C1
C2 S5
S7 S8
− S4
−
+ V2
iC1
T
kT i1 kT
T i2
(i)
(ii)
(iii)
FIGURE 14.78b Mode A2 (QI): forward motoring with V1 < V2 : (i) switch on: S1 , S4 , S6 , and S8 , on; (ii) switch off: S2 , S4 , and S7 , on; and (iii) waveforms.
312
F. L. Luo and H. Ye vC1 S2
S1 +
S6
V2
+
S5 C2
S7
C1
S8
−
S1
S2
+ VC1 V1 −
+
VC1
S6 S5 C 2
S7
V2
C1
S8
+ VC1 −
+ −
S4
−
iC1
V1
i1
S4
−
T
kT
kT
T i2
(i)
(ii)
(iii)
FIGURE 14.78c Mode B1 (QII): forward regenerative braking with V1 > V2 : (i) switch on: S2 , S4 , S6 , and S8 , on; (ii) switch off; S1 , S4 (S5 ), and S7 on; and (iii) waveforms.
The transfer efﬁciency is ηA2 =
The average current is
PO 1 − k V2 2VC − V2 V2 = = PI k V 1 V1 − V C 2V1
T
1 I1 = T
(14.258)
iC (t )dt ≈ (1 − k)
2VC − V1 R
(14.260)
kT
For Mode B1, condition V1 > V2 is shown in Fig. 14.78c. Since V1 > V2 , two capacitors C1 and C2 are connected in parallel during switch on and in series during switch off. The voltagelift technique is applied. During switchon state, switches S2 , S4 , S6 , and S8 are closed. In this case, capacitors C1 //C2 are charged via the circuit V2 –S2 –C1 //C2 –S4 , and the voltage across capacitors C1 and C2 is increasing. During switchoff state, switches S1 , S4 , and S7 are closed. In this case, capacitors C1 and C2 are discharged via the circuit S1 –V1 – S4 –C2 –S7 –C1 , and the voltage across capacitor C1 and C2 is decreasing. Capacitors C1 and C2 transfer the energy from the load to the source. Therefore, we have I2 = 2I1 . The average capacitor voltage is VC =
0.5V2 + V1 = 11.2 2.5
V2
C2
S7 S8
−
kT iC (t )dt ≈ k
(14.261)
The transfer efﬁciency is ηB1 =
PO 1 − k V1 2VC − V1 V1 = = PI k V 2 V2 − V C 2V2
(14.262)
For Mode B2, condition V1 < V2 is shown in Fig. 14.78d. Since V1 < V2 , two capacitors C1 and C2 are connected in parallel. During switchon state, switches S2 , S4 , S6 , and S8 are closed. In this case, capacitors C1 //C2 are charged via the circuit V2 –S2 –C1 //C2 –S4 , and the voltage across capacitors C1 and C2
+ C1
S1
+ VC1 V1 −
+ S5 V2
VC1
S6 S7
C2
S8
C1
+ VC1 −
+ −
S4
V2 − VC R
0
S2
S1
S6 S5
1 I2 = T
vC1
S2
+
(14.259)
and
−
−
S4
V1
iC1
T
kT i1 kT
T i2
(i)
(ii)
(iii)
FIGURE 14.78d Mode B2 (QII): forward regenerative braking with V1 < V2 : (i) switch on: S2 , S4 , S6 , and S8 , on; (ii) switch off: S1 , S4 (S5 ), S6 , and S8 on; and (iii) waveforms.
14
313
DC/DC Conversion Technique and 12 Series Luoconverters
is increasing. During switchoff state, switches S1 , S4 , S6 , and S8 are closed. In this case capacitors C1 //C2 is discharged via the circuit S1 –V1 –S4 –C1 //C2 , and the voltage across capacitors C1 and C2 is decreasing. Capacitors C1 and C2 transfer the energy from the load to the source. Therefore, we have I2 = I1 . The average capacitor voltage is VC = kV2 + (1 − k)V1
The average capacitor voltage is VC = kV1 + (1 − k)V2  The average current (absolute value) is
1 T
T
1 I2 = T
(14.263)
iC (t )dt ≈ (1 − k)
VC − V2  R
(14.268)
kT
The average current is
I1 =
(14.267)
and the average input current is
T iC (t )dt ≈ (1 − k)
V C − V1 R
(14.264) 1 I1 = T
kT
kT iC (t )dt ≈ k
V1 − VC R
(14.269)
0
and 1 T
I2 =
The transfer efﬁciency is
kT iC (t )dt ≈ k
V2 − VC R
(14.265)
ηC1 =
0
The transfer efﬁciency is PO 1 − k V 1 VC − V 1 V1 = = PI k V2 V2 − V C V2
ηB2 =
(14.266)
For Mode C1, condition V1 > V2  is shown in Fig. 14.78e. Since V1 > V2 , two capacitors C1 and C2 are connected in parallel. During switchon state, switches S1 , S4 , S6 , and S8 are closed. In this case, capacitors C1 //C2 are charged via the circuit V1 –S1 –C1 //C2 –S4 , and the voltage across capacitors C1 and C2 is increasing. During switchoff state, switches S3 , S5 , S6 , and S8 are closed. Capacitors C1 and C2 are discharged via the circuit S3 –V2 –S5 –C1 //C2 , and the voltage across capacitors C1 and C2 is decreasing. Capacitors C1 and C2 transfer the energy from the source to the load. We have I1 = I2 .
V2  PO 1 − k V2  VC − V2  = = PI k V1 V1 − V C V1
(14.270)
For Mode C2, condition V1 < V2  is shown in Fig. 14.78f. Since V1 < V2 , two capacitors C1 and C2 are connected in parallel during switch on and in series during switch off, applying the voltagelift technique. During switchon state, switches S1 , S4 , S6 , and S8 , are closed. Capacitors C1 and C2 are charged via the circuit V1 –S1 –C1 //C2 –S4 , and the voltage across capacitors C1 and C2 is increasing. During switchoff state, switches S3 , S5 , and S7 are closed. Capacitors C1 and C2 is discharged via the circuit S3 –V2 –S5 –C1 –S7 –C2 , and the voltage across capacitor C1 and C2 is decreasing. Capacitors C1 and C2 transfer the energy from the source to the load. We have I1 = 2I2 . The average capacitor voltage is VC =
0.5V1 + V2  = 11.2 2.5
(14.271)
vC1 S1
S2
−
S6 V1
+ + VC1 − −
C1
+
C2 S5
S7
V2
S8
S2
S1
V1
VC1
S6 + VC1 −
C1
S7
C2
S8
S5
− +
S4
+
−
S3
S4
V2
iC1
kT
T
i1 kT
T i2
(i)
FIGURE 14.78e (iii) waveforms.
(ii)
(iii)
Mode C1 (QIII): reverse motoring with V1 > V2 : (i) switch on: S1 , S4 , S6 , and S8 on; (ii) switch off: S3 , S5 , S6 , and S8 on; and
314
F. L. Luo and H. Ye vC1 S1
S2
−
S6 V1
+ C1 + VC1 − −
+
C2 S5
S7
V1
V2
S8 S4
S2
S1
+
VC1
S6 + VC1 −
C1
S7
C2
−
S8
V2
kT
iC1
+
S3
−
S5
T
i1
S4
kT
T i2
(i)
(ii)
Mode C2 (QIII): reverse motoring with V1 < V2 : (i) switch on: S1 , S4 , S6 , and S8 , on; (ii) switch off: S3 , S5 , and S7 , on; and
FIGURE 14.78f (iii) waveforms.
The average currents are 1 I2 = T
(iii)
T iC (t )dt ≈ (1 − k)
2VC − V2  R
(14.272)
kT
and 1 I1 = T
kT iC (t )dt ≈ k
V1 − V C R
S3 , S5 , S6 , and S8 are closed. In this case, capacitors C1 //C2 are charged via the circuit V2 –S3 –C1 //C2 –S5 , and the voltage across capacitors C1 and C2 is increasing. During switchoff state, switches S1 , S4 , and S7 are closed. Capacitors C1 and C2 are discharged via the circuit S1 –V1 –S4 –C2 –S7 –C1 , and the voltage across capacitor C1 and C2 is decreasing. Capacitors C1 and C2 transfer the energy from the load to the source. We have I2 = 2I1 . The average capacitor voltage is
(14.273)
VC =
0
(14.275)
The average currents are
The transfer efﬁciency is ηC2
0.5V2  + V1 = 11.2 2.5
PO 1 − k V2  2VC − V2  V2  = = = PI k V 1 V1 − V C 2V1
1 I1 = T
(14.274)
T iC (t )dt ≈ (1 − k)
2VC − V1 R
(14.276)
kT
For Mode D1, condition V1 > V2  is shown in Fig. 14.78g. Since V1 > V2 , two capacitors C1 and C2 are connected in parallel during switch on and in series during switch off, applying the voltagelift technique. During switchon state, switches
and 1 I2 = T
kT iC (t )dt ≈ k
V2  − VC R
(14.277)
0
vC1 S2
+
S6 S5 V2
C2
S7
−
S8
+
C1
+ VC1 − S3
S4
S1
S2
S1 − S5 V1
−
C2
S7
V2
+
VC1
S6
S8 S4
C1
+ VC1 + − −
V1
iC1
kT
T
i1 kT
T i2
(i)
(ii)
(iii)
FIGURE 14.78g Mode D1 (QIV): reverse regenerative braking with V1 > V2 : (i) switch on: S3 , S4 , S6 , and S8 , on; (ii) switch off: S1 , S4 , and S7 on; and (iii) waveforms.
14
315
DC/DC Conversion Technique and 12 Series Luoconverters
S2
+
S6 S5
C2
S7
−
V2
C1
S8
+
+ VC1 − S3
S4
−
−
C2
S7
V2
+
VC1
S6 S5
V1
vC1
S1
S2
S1
C1
S8
+ VC1 + − −
V1
iC1
kT
T
i1
S4
kT
T i2
(i)
(ii)
(iii)
FIGURE 14.78h Mode D2 (QIV): reverse regenerative braking with V1 < V2 : (i) switch on: S3 , S5 , S6 , and S8 , on; (ii) switch off: S1 , S4 , S6 , and S8 on; and (iii) waveforms.
14.9 Multiplelift Push–Pull Switchedcapacitor Luoconverters
The transfer efﬁciency is ηD1 =
PO 1 − k V1 2VC − V1 V1 = = PI k V2  V2  − VC 2V2 
(14.278)
For Mode D2, condition V1 < V2  is shown in Fig. 14.78h. Since V1 < V2 , two capacitors C1 and C2 are connected in parallel. During switchon state, switches S3 , S5 , S6 , and S8 are closed. In this case, capacitors C1 //C2 are charged via the circuit V2 –S3 –C1 //C2 –S5 , and the voltage across capacitors C1 and C2 is increasing. During switchoff state, switches S1 , S4 , S6 , and S8 are closed. Capacitors C1 and C2 are discharged via the circuit S1 –V1 –S4 –C1 //C2 , and the voltage across capacitors C1 and C2 is decreasing. Capacitors C1 and C2 transfer the energy from the load to the source. We have I2 = I1 . The average capacitor voltage is VC = kV2  + (1 − k)V1
T iC (t )dt ≈ (1 − k)
V C − V1 R
• •
(14.279)
The average currents are 1 I1 = T
Micropowerconsumption technique requires high power density DC/DC converters and power supply source. Voltagelift (VL) technique is a popular method to apply in electronic circuit design. Since switchedcapacitor can be integrated into power integrated circuit (IC) chip, its size is small. Combining switchedcapacitor and VL techniques the DC/DC converters with small size, high power density, high voltage transfer gain, high power efﬁciency, and low EMI can be constructed. This section introduces a new series DC/DC converters – multiplelift push–pull switchedcapacitor DC/DC Luoconverters. There are two subseries:
(14.280)
14.9.1 P/O Multiplelift Push–Pull Switchedcapacitor DC/DC Luoconverter P/O MLPP SC DC/DC Luoconverters have several subseries:
kT
•
and
• •
I2 =
1 T
kT iC (t )dt ≈ k
V2  − VC R
•
(14.281)
The transfer efﬁciency is 1 − k V 1 VC − V 1 V1 PO = = PI k V2  V2  − VC V2 
•
Main series; Additional series; Enhanced series; Reenhanced series; Multipleenhanced series.
We only introduce three circuits of main series and additional series in this section. P/O MLPP SC Luoconverter elementary circuit is shown in Fig. 14.79a. Its output voltage and current are
0
ηD2 =
P/O multiplelift (ML) push–pull (PP) switchedcapacitor (SC) DC/DC Luoconverter; N/O multiplelift push–pull switchedcapacitor DC/DC Luoconverter.
(14.282)
VO = 2VI
316
F. L. Luo and H. Ye Iin
+ Vin −
D1
Iin
D2
IO
+
S1
C1
−
VC1 +
C2
S
R
−
VC2
−
VO
S1
C1
−
+ Vin −
D2
VC1
S2
D5 C2
−
D4
V1
+ C1
IO
C3 _
+ VC2 −
VC3
+ R
S
VO
+ − V − C4
C4
(b)
D1
S1
D4 +
(a) Iin
D3
+
+ Vin −
+
D2 V1
D1
S2
VC1
D5
V2
+ C3
_
S3
VC3
D7
D8 IO
+ C5
_
VC5
+ R
C2
−
+
D6
+
D3
C4
VC2
_
VC4
S
C6
+ V − C6
VO −
(c)
FIGURE 14.79 P/O MLPP SC Luoconverter: (a) elemental; (b) relift; and (c) triplelift circuits.
and
The voltage transfer gain is 1 I O = II 2
MT = 8
P/O MLPP SC Luoconverter additional circuit is shown in Fig. 14.80a. Its output voltage and current are
The voltage transfer gain is ME =
(14.285)
VO =2 VI
VO = 3VI
(14.283)
P/O MLPP SC Luoconverter relift circuit is shown in Fig. 14.79b. Its output voltage and current are
and 1 I O = II 3
VO = 4VI
The voltage transfer gain is and MA =
1 I O = II 4
(14.284)
P/O MLPP SC Luoconverter triplelift circuit is shown in Fig. 14.79c. Its output voltage and current are VO = 8VI
(14.286)
P/O MLPP SC Luoconverter additional relift circuit is shown in Fig. 14.80b. Its output voltage and current are
The voltage transfer gain is MR = 4
VO =3 VI
VO = 6VI and 1 I O = II 6 The voltage transfer gain is
and 1 I O = II 8
MAR =
VO =6 VI
(14.287)
14
317
DC/DC Conversion Technique and 12 Series Luoconverters Iin
+ Vin −
D2 V1 D11
D1 + C1
S1
−
Iin
D12 +
VC1
C11
VC11
−
R S
+
C2
C12
VC2
−
−
+
VO
S1
C1
−
VC12
S2 C3
VC1 + −
_
VC2
+ Vin −
S1
D2
D4
V1
+ −
C11 + −
−
VC11
C12
VC4
+ R +
−
VO
V
− C12
(b)
D1
C1
C4
IO
+
VC3
S
(a) Iin
D12
+
D3 C2
−
D5 V2 D11
D4
V1
+
+ Vin −
+
D2
D1
IO
S2
VC1
D3 C2
+ −
+ C3
_
VC3
D8 +
S3
C5
_
D11
C11
VC5
D12 IO
+ −
VC11
+ R
D6 VC2
D7
V2
D5
C4
+ −
S
VC4
C6
+
+ V − C6
C12
−
VO
VC12
−
(c)
FIGURE 14.80 P/O MLPP SC Luoconverter relift circuit: (a) additional; (b) relift; and (c) triplelift circuits.
P/O MLPP SC Luoconverter additional triplelift circuit is shown in Fig. 14.80c. Its output voltage and current are
and IO = II
VO = 12VI
The voltage transfer gain is and IO =
ME =
1 II 12
VO = 12 VI
(14.288)
14.9.2 N/O Multiplelift Push–Pull Switchedcapacitor DC/DC Luoconverter N/O MLPP SC DC/DC Luoconverters have several subseries: • • • • •
(14.289)
N/O MLPP SC Luoconverter relift circuit is shown in Fig. 14.81b. Its output voltage and current are
The voltage transfer gain is MAT =
VO =1 VI
Main series; Additional series; Enhanced series; Reenhanced series; Multipleenhanced series.
We only introduce three circuits of main series and additional series in this section. N/O MLPP SC Luoconverter elementary circuit is shown in Fig. 14.81a. Its output voltage and current are VO = VI
VO = 3VI and 1 I O = II 3 The voltage transfer gain is MR = 3
(14.290)
N/O MLPP SC Luoconverter triplelift circuit is shown in Fig. 14.81c. Its output voltage and current are VO = 7VI and 1 I O = II 7
318
F. L. Luo and H. Ye Iin
Iin S
+
C1
S1
IO
+ VC1 − −
Vin D1
D2
C2
R
VC2
IO
+ VC1 −
C1
S1
−
Vin D1
+
+
−
− VO
S
+
D2
R
VC2
C2
+
+
−
(a)
− VO
(b)
Iin S
+
D3
S1
C1
+ VC1 −
D6
S2
C3
C5
S3
VC5 +
V2
V1
Vin
IO
−
+ VC3 −
R D1
−
D2 C2
− D4
D5
VC2
C4
+
− D7 VC4
D8
−
− VO +
VC6
C6
+
+ (c)
FIGURE 14.81 N/O MLPP SC Luoconverter: (a) elemental; (b) relift; and (c) triplelift circuits.
The voltage transfer gain is
The voltage transfer gain is
MT = 7
(14.291)
N/O MLPP SC Luoconverter additional circuit is shown in Fig. 14.82a. Its output voltage and current are VO = 2VI
VO =5 VI
MAR =
(14.293)
N/O MLPP SC Luoconverter additional triplelift circuit is shown in Fig. 14.82c. Its output voltage and current are VO = 11VI
and and
1 I O = II 2
IO =
The voltage transfer gain is MA =
VO =2 VI
(14.292)
N/O MLPP SC Luoconverter additional relift circuit is shown in Fig. 14.82b. Its output voltage and current are
1 II 11
The voltage transfer gain is MAT =
VO = 11 VI
(14.294)
VO = 5VI
14.10 Switchedinductor Multiquadrant Operation Luoconverters
1 I O = II 5
Switchedcapacitor converters usually have many switches and capacitors, especially for the system with high ratio between
and
14
319
DC/DC Conversion Technique and 12 Series Luoconverters Iin
Iin +
+ VC1 −
S C1
S1 Vin
D1
D2 C2
−
+ VC11 −
C11
− +
− R VO + −
D12
D11
C12
VC2
S
+
IO
S1
C1
Vin
+ D3 VC1 S2 − D2 C2
D1
VC12
−
+
(a)
+ VC3 C11 −
C3 − D4 V + C2
+ VC11 −
IO − R VO
D D5 D12 − + − 11 C4 C VC12 VC4 12 + +
(b)
Iin S
+
S1
D3
C1
+ VC1 −
Vin D1 −
D2 C2
D6
C3
S2 V1
+ VC3 S3 − V2
C5
+ VC5 −
C11
+ VC11 −
IO
V3 R
− +
D4 VC2
D5
−
C4
+
D7
D8
VC4
C6
D11 + VC6 −
D12 C12
− VO +
− VC12
+
(c)
FIGURE 14.82 N/O MLPP SC Luoconverter relift circuit: (a) additional; (b) relift; and (c) triplelift circuits.
source and load voltages. Switchedinductor converter usually has only one inductor even if it works in single, two, and/or fourquadrant operation. Simplicity is the main advantage of all switched inductor converters. Switchedinductor multiquadrant Luoconverters are the thirdgeneration converters, and they are made of only inductor. These converters have been derived from chopper circuits. They have three modes: • •
Twoquadrant switchedinductor DC/DC Luoconverter in forward operation; Twoquadrant switchedinductor DC/DC Luoconverter in reverse operation; Fourquadrant switchedinductor DC/DC Luoconverter.
in the thirdquadrant QIII and the fourthquadrant QIV corresponding to the DC motor reverse operation in motoring and regenerative braking states. The fourquadrant switchedinductor DC/DC Luoconverter has been derived for the energy transmission of a dualvoltage system. The source voltage is positive and load voltage can be positive or negative polarity. It performs fourquadrant operation corresponding to the DC motor forward and reverse operation in motoring and regenerative braking states.
14.10.1 Twoquadrant Switchedinductor DC/DC Luoconverter in The twoquadrant switchedinductor DC/DC Luoconverter Forward Operation •
in forward operation has been derived for the energy transmission of a dualvoltage system. The both, source and load voltages are positive polarity. It performs in the ﬁrstquadrant QI and the secondquadrant QII corresponding to the DC motor forward operation in motoring and regenerative braking states. The twoquadrant switchedinductor DC/DC Luoconverter in reverse operation has been derived for the energy transmission of a dualvoltage system. The source voltage is positive and load voltage is negative polarity. It performs
Forward operation (F) 2Q SI Luoconverter is shown in Fig. 14.83, and it consists of two switches with two passive diodes, two inductors, and one capacitor. The source voltage (V1 ) and load voltage (V2 ) are usually considered as constant voltages. The load can be a battery or motor back EMF. For example, the source voltage is 42 V and load voltage is +14 V. There are two modes of operation: 1. Mode A (QI): electrical energy is transferred from source side V1 to load side V2 ;
320
F. L. Luo and H. Ye
The power transfer efﬁciency is D1
L1
R1
ηA =
S1 + −
Vhigh
+ S2
D2
−
Ihigh
Vlow Ilow
PO V2 = PI kV1
(14.297)
The boundary between continuous and discontinuous regions is deﬁned as ζ≥1 k(1 − k)V1 R ≥1 kV1 − V2 2fL
FIGURE 14.83 Switchedinductor QI and II DC/DC Luoconverter.
or
i.e.
k≤
R V2 (14.298) + k(1 − k) 2fL V1
Average inductor current IL in discontinuous region is 2. Mode B (QII): electrical energy is transferred from load side V2 to source side V1 .
IL =
Mode A: The equivalent circuits during switchon and off periods are shown in Figs. 14.84a and b. The typical output voltage and current waveforms are shown in Fig. 14.84c. We have the average inductor current IL as IL =
kV1 − V2 R
(14.295)
The variation ratio of the inductor current iL is
ζ=
k(1 − k)V1 R iL /2 = kV1 − V2 2fL IL
L1
S1
iI
+ −
Vhigh
ηA−dis =
i1
Vlow
−
Vhigh
(a)
with
k≤
V2 R + k(1 − k) V1 2fL (14.300)
Mode B: The equivalent circuits during switchon and off periods are shown in Figs. 14.85a and b. The typical output voltage and current waveforms are shown in Fig. 14.85c. The average inductor current IL is IL =
V2 − (1 − k)V1 R
iI
L1
−
V2 PO = PI V2 + RIL
(14.296)
+
(14.299)
The power transfer efﬁciency is
R1 +
V1 − V2 − RIL 2 V1 k V2 + RIL 2fL
R1 io +
D2
i2
−
Vlow
io
(14.301)
i1
i1
(b)
kT T i2
t
kT
t
T (c)
FIGURE 14.84 Mode A of F 2Q SI Luoconverter: (a) stateon: S1 on; (b) stateoff: D2 on, S1 , off; and (c) input and output current waveforms. iI R1 iI
+ −
Vlow
R1
L1
i1
(a)
S2
+ −
Vhigh
+ −
Vlow
L1
i2
(b)
D1 io + Vhigh −
io
i1
i2
kT T i2
t
kT T (c)
t
FIGURE 14.85 Mode B of F 2Q SI Luoconverter: (a) stateon: S2 on; (b) stateoff: D1 on, S2 off; and (c) input and output current waveforms.
14
321
DC/DC Conversion Technique and 12 Series Luoconverters
The variation ratio of the inductor current iL is iL /2 R k(1 − k)V1 ζ= = IL V2 − (1 − k)V1 2fL
(14.302) + −
The power transfer efﬁciency ηB =
PO (1 − k)V1 = PI V2
L1
Vlow
− +
Ihigh
Ilow
1. Mode C (QIII): electrical energy is transferred from source side V1 to load side −V2 ; 2. Mode D (QIV): electrical energy is transferred from load side −V2 to source side V1 .
(14.305) Mode C: The equivalent circuits during switchon and off periods are shown in Figs. 14.87a and b. The typical output voltage and current waveforms are shown in Fig. 14.87c. We have the average inductor current IL as
The power transfer efﬁciency is ηB−dis = with
Vhigh
voltages. The load can be a battery or motor back EMF. For example, the source voltage is 42 V and load voltage is −14 V. There are two modes of operation:
Average inductor current IL in discontinuous region is
PO V2 − RIL = PI V2 R V2 + k(1 − k) k ≤ 1− V1 2fL
S2
FIGURE 14.86 Switchedinductor QIII and IV DC/DC Luoconverter.
i.e. R V2 +k(1−k) or k ≤ 1− V1 2fL (14.304)
V2 − RIL 2 V1 k V1 − V2 + RIL 2fL
S1
(14.303)
ζ ≥ 1,
IL =
D2
R1
The boundary between continuous and discontinuous regions is deﬁned as
k(1−k)V1 R ≥1 V2 −(1−k)V1 2fL
D1
IL =
(14.306)
kV1 − (1 − k)V2 R
(14.307)
The variation ratio of the inductor current iL is
14.10.2 Twoquadrant Switchedinductor DC/DC Luoconverter in Reverse Operation
ζ=
iL /2 k(1 − k)(V1 + V2 ) R = IL kV1 − (1 − k)V2 2fL
The power transfer efﬁciency is
Reverse operation (R) 2Q SI Luoconverter is shown in Fig. 14.86, and it consists of two switches with two passive diodes, two inductors, and one capacitor. The source voltage (V1 ) and load voltage (V2 ) are usually considered as constant
ηC =
S1 +V high −
R1 i1
(a)
L1
− +
Vlow
+ Vhigh −
PO (1 − k)V2 = PI kV1
iI
D2 iI
(14.308)
(14.309)
i1
io
R1 i2
L1
(b)
− +
Vlow
io
kT T i2
t
kT T
t
(c)
FIGURE 14.87 Mode C of F 2Q SI Luoconverter: (a) stateon; S1 on; (b) stateoff: D2 on, S1 off; and (c) input and output current waveforms.
322
F. L. Luo and H. Ye
The boundary between continuous and discontinuous regions is deﬁned as ζ ≥ 1, k(1−k)(V1 +V2 ) R ≥1 kV1 −(1−k)V2 2fL
The boundary between continuous and discontinuous regions is deﬁned as ζ ≥ 1,
i.e.
or k ≤
R V2 +k(1−k) V1 +V2 2fL (14.310)
k(1−k)(V1 +V2 ) R ≥1 kV2 −(1−k)V1 2fL
t4
V1 + V2 V1 − RIL 2 k V2 + RIL 2fL
IL =
(14.311)
= 0
The power transfer efﬁciency is ηC−dis = with
k≤
PO V2 V1 − RIL = PI V1 V2 + RIL
ηD−dis =
V2 R + k(1 − k) V1 + V 2 2fL
(14.312)
kV2 − (1 − k)V1 IL = R
(14.313)
The variation ratio of the inductor current iL is iL /2 k(1 − k)(V1 + V2 ) R = IL kV2 − (1 − k)V1 2fL
(14.314)
The power transfer efﬁciency is ηD =
V1 + V2 V2 − RIL 2 k V1 + RIL 2fL
PO (1 − k)V1 = PI kV2
S2
R1 i1
L1
(a)
(14.317)
(14.315)
with
k≤
PO V1 V2 − RIL = PI V2 V1 + RIL R V1 + k(1 − k) V1 + V 2 2fL
iI − +
io Vlow
+ Vhigh −
(14.318)
14.10.3 Fourquadrant Switchedinductor DC/DC Luoconverter Switchedinductor DC/DC converters successfully overcome the disadvantage of switchedcapacitor converters. Usually, only one inductor is required for each converter with oneor two or fourquadrant operation, no matter how large the difference between the input and output voltage is. Therefore, switchedinductor converter has very simple topology and circuit. Consequently, it has high power density. This paper introduces a switchedinductor fourquadrant DC/DC Luoconverter. This converter, shown in Fig. 14.89, consists of three switches, two diodes, and only one inductor L. The source voltage V1 and load voltage V2 (e.g. a battery or DC motor back EMF) are usually constant voltages. R is the equivalent resistance of the circuit, it is usually small. In this paper, V1 > V2 ,
iI
D1 + V − high
V1 R +k(1−k) V1 +V2 2fL (14.316)
The power transfer efﬁciency is
Mode D: The equivalent circuits during switchon and off periods are shown in Figs. 14.88a and b. The typical output voltage and current waveforms are shown in Fig. 14.88c. The average inductor current IL is
ζ=
k≤
or
Average inductor current IL in discontinuous region is
Average inductor current IL in discontinuous region is IL =
i.e.
R1 i2
L1
(b)
− +
Vlow
io
i1
kT T i2
t
kT
t
T (c)
FIGURE 14.88 Mode D of F 2Q SI Luoconverter: (a) stateon: S2 on; (b) stateoff: D1 on, S2 off; and (c) input and output waveforms.
14
323
DC/DC Conversion Technique and 12 Series Luoconverters
D1
D2
S1
S2 L1
II
R1 Switch S
V1
3,4
1,2 V2
3,4 + _
1,2
I2
FIGURE 14.89 Fourquadrant switchedinductor DC/DC Luoconverter.
they are supposed as +42 V and ±14 V, respectively. Therefore, there are fourquadrants (modes) of operation: 1. Mode A: energy is transferred from source to positive voltage load; the ﬁrstquadrant operation, QI ; 2. Mode B: energy is transferred from positive voltage load to source; the secondquadrant operation, QII ; 3. Mode C: energy is transferred from source to negative voltage load; the thirdquadrant operation, QIII ; 4. Mode C: energy is transferred from negative voltage load to source; the fourthquadrant operation, QIV . The ﬁrstquadrant is socalled the forward motoring (Forw. Mot.) operation. V1 and V2 are positive, and I1 and I2 are positive as well. The secondquadrant is socalled the forward regenerative (Forw. Reg.) braking operation. V1 and V2 are positive, and I1 and I2 are negative. The thirdquadrant is socalled the reverse motoring (Rev. Mot.) operation. V1 and I1 are positive, and V2 and I2 are negative. The fourthquadrant is socalled the reverse regenerative (Rev. Reg.) braking operation. V1 and I2 are positive, and I1 and V2 are negative. Each mode has two states: “on” and “off.” Usually, each state is operating in different conduction duty k. The switching period is T, where T = 1/f . The switch status is shown in Table 14.7. Mode A is shown in Fig. 14.84. During switchon state, switch S1 is closed. In this case the source voltage V1 supplies the load V2 and inductor L, inductor current iL increases. TABLE 14.7
Switch’s status (mentioned switches are not off)
Q no.
State
S1
QI , Mode A Forw. Mot.
ON OFF
ON
QII , Mode B Forw. Reg.
ON OFF
QIII , Mode C Rev. Mot.
ON OFF
QIV , Mode D Rev. Reg.
ON OFF
D1
S2
D2
S3
Source
Load
ON
ON 1/2 ON 1/2
V1 + I1 +
V2 + I2 +
ON 1/2 ON 1/2
V1 + I1 −
V2 + I2 −
ON 3/4 ON 3/4
V1 + I1 +
V2 − I2 −
ON 3/4 ON 3/4
V1 + I1 −
V2 − I2 +
ON ON ON ON ON ON
During switchoff state, diode D2 is on. In this case current iL ﬂows through the load V2 via the freewheeling diode D2 , and it decreases. Mode B is shown in Fig. 14.85. During switchon state, switch S2 is closed. In this case the load voltage V2 supplies the inductor L, inductor current iL increases. During switchoff state, diode D1 is on, current iL ﬂows through the source V1 and load V2 via the diode D1 , and it decreases. Mode C is shown in Fig. 14.87. During switchon state, switch S1 is closed. The source voltage V1 supplies the inductor L, inductor current iL increases. During switchoff state, diode D2 is on. Current iL ﬂows through the load V2 via the freewheeling diode D2 , and it decreases. Mode D is shown in Fig. 14.88. During switchon state, switch S2 is closed. The load voltage V2 supplies the inductor L, inductor current iL increases. During switchoff state, diode D1 is on. Current iL ﬂows through the source V1 via the diode D1 , and it decreases. All description of the Modes A, B, C, and D is same as in Sections 14.10.1 and 14.10.2.
14.11 Multiquadrant ZCS Quasiresonant Luoconverters Softswitching converters are the fourthgeneration converters. These converters are made of only inductor or capacitors. They usually perform in the systems between two voltage sources: V1 and V2 . Voltage source V1 is proposed positive voltage and voltage V2 is the load voltage that can be positive or negative. In the investigation, both voltages are proposed constant voltage. Since V1 and V2 are constant value, the voltage transfer gain is constant. Our interesting research will concentrate on the working current and the power transfer efﬁciency η. The resistance R of the inductor has to be considered for the power transfer efﬁciency η calculation. Reviewing the papers in the literature, we can ﬁnd that most of the papers investigating the switchedcomponent converters
324
F. L. Luo and H. Ye
are working in singlequadrant operation. Professor Luo and colleagues have developed this technique into multiquadrant operation. We describe these in this section and the next sections. Multiquadrant ZCS quasiresonant Luoconverters are the fourthgeneration converters. Because these converters implement ZCS technique, they have the advantages of high power density, high power transfer efﬁciency, low EMI, and reasonable EMC. They have three modes: • • •
Twoquadrant ZCS quasiresonant DC/DC Luoconverter in forward operation; Twoquadrant ZCS quasiresonant DC/DC Luoconverter in reverse operation; Fourquadrant ZCS quasiresonant DC/DC Luoconverter.
The twoquadrant ZCS quasiresonant DC/DC Luoconverter in forward operation is derived for the energy transmission of a dualvoltage system. Both, the source and load voltages are positive polarity. It performs in the ﬁrstquadrant QI and the secondquadrant QII corresponding to the DC motor forward operation in motoring and regenerative braking states. The twoquadrant ZCS quasiresonant DC/DC Luoconverter in reverse operation is derived for the energy transmission of a dualvoltage system. The source voltage is positive and load voltage is negative polarity. It performs in the thirdquadrant QIII and the fourthquadrant QIV corresponding to the DC motor reverse operation in motoring and regenerative braking states. The fourquadrant ZCS quasiresonant DC/DC Luoconverter is derived for the energy transmission of a dualvoltage system. The source voltage is positive, and load voltage can be positive or negative polarity. It performs fourquadrant operation corresponding to the DC motor forward and reverse operation in motoring and regenerative braking states.
TABLE 14.8 Switch’s status (the blank status means off) Switch or diode
Mode A (QI) Stateon
S1 D1 S2 D2
i1
S1
V1 –
D1
Stateoff ON
ON
two switches with their auxiliary components. A switch Sa is used for twoquadrant operation. Assuming the main inductance is sufﬁciently large, the current iL is constant. The source voltage V1 and load voltage V2 are usually constant, V1 = 42 V and V2 = 14 V. There are two modes of operation: 1. Mode A (Quadrant I): electrical energy is transferred from V1 side to V2 side, switch Sa links to D2 ; 2. Mode B (Quadrant II): electrical energy is transferred from V2 side to V1 side, switch Sa links to D1 . Each mode has two states: “on” and “off.” The switch status of each state is shown in Table 14.8. Mode A is a ZCS buck converter. The equivalent circuit, current, and voltage waveforms are shown in Fig. 14.91. There are four time regions for the switching on and off period. The conduction duty cycle is k = (t1 + t2 ) when the input current
iLr1
S1
IL
Lr1
+
+
+ VC Cr −
V1 −
D2
−
V2
(a)
iLr1
0
V1/Z1
IL t1
t2
t3
t4
t3
t4
vc0 V1
2
+
Stateon
ON
iL
Lr1
Stateoff
ON
14.11.1 Twoquadrant ZCS Quasiresonant Luoconverter in Forward Operation Since both voltages are low, this converter is designed as a ZCS quasiresonant converter (ZCSQRC). It is shown in Fig. 14.90. This converter consists of one main inductor L and
Mode B (QII)
Sa 1
D2
Cr
Lr2 S2
L + V2 –
vc
V1 0
t1
t2 (b)
FIGURE 14.90 Twoquadrant (QI+QII) DC/DC ZCS quasiresonant Luoconverter.
FIGURE 14.91 Mode A operation: (a) equivalent circuit and (b) waveforms.
14
325
DC/DC Conversion Technique and 12 Series Luoconverters
ﬂows through the switch S1 and inductor L. The whole period is T = (t1 + t2 + t3 + t4 ). Some formulas are listed below Lr1 1 V1 ω1 = √ ; Z1 = ; i1−peak = IL + Cr Z1 Lr1 Cr (14.319) IL Z1 IL Lr1 (14.320) t1 = ; α1 = sin−1 V1 V1 1 t2 = (π + α1 ); ω1 t3 =
vCO = V1 (1 + cos α1 )
IL V2 t1 + t2 = V1 T
vCO Cr ; IL
IL +
V1 (t1 + t2 ) V1 cos α1 t4 = IL + V2 IL Z1 π/2 + α1 t1 + t2 ; t1 + t 2 + t 3 + t 4
1 ω2 = √ ; Lr2 Cr t1 =
(14.321)
V1 cos α1 Z1 π/2 + α1 (14.322)
t2 =
− (t1 + t2 + t3 );
T = t1 + t2 + t3 + t4 ;
f = 1/T
Z2 =
IL Lr2 ; V1
Lr2 ; Cr
(V1 −vCO )Cr ; IL
t1 +t2 ; t1 +t2 +t3 +t4
IL Z2 V1
V1 Z2
(14.326) (14.327)
IL V2 t4 = IL V1 T t4 =
(14.325)
vCO = −V1 cosα2
V2 t4 t4 = = ; V1 T t1 +t2 +t3 +t4 k=
i2−peak = IL +
α2 = sin−1
1 (π +α2 ); ω2
t3 =
(14.323)
k=
are four time regions for the switching on and off period. The conduction duty cycle is k = (t1 + t2 ), but the output current only ﬂows through the source V1 in the period t4 . The whole period is T = (t1 + t2 + t3 + t4 ). Some formulas are listed below
(14.328)
t1 +t2 +t3 (V1 /V2 )−1
T = t1 +t2 +t3 +t4 ;
(14.329)
f = 1/T (14.330)
(14.324) Mode B is a ZCS boost converter. The equivalent circuit, current, and voltage waveforms are shown in Fig. 14.92. There
IL
D1 Lr2 +
+ VC Cr −
V1 −
+
iLr2
−
S2
V2
(a)
iLr2
0
IL t2
t3
Twoquadrant ZCS quasiresonant Luoconverter in reverse operation is shown in Fig. 14.93. It is a new softswitching technique with twoquadrant operation, which effectively reduces the power losses and largely increases the power transfer efﬁciency. It consists of one main inductor L and two switches with their auxiliary components. A switch Sa is used for twoquadrant operation. Assuming the main inductance L is sufﬁciently large, the current iL is constant. The source voltage V1 and load voltage V2 are usually constant, e.g. V1 = 42 V and V2 = −28 V. There are two modes of operation: 1. Mode C (Quadrant III): electrical energy is transferred from V1 side to −V2 side, switch Sa links to D2 ; 2. Mode D (Quadrant IV): electrical energy is transferred from −V2 side to V1 side, switch Sa links to D1 .
V1/Z2
t1
14.11.2 Twoquadrant ZCS Quasiresonant Luoconverter in Reverse Operation
t4
vc
D1
V1
V1
i1
0 V1
Sa
3
Lr1
V1
t2
t3
t4
–
D2 S2 Lr2
+ vc0
t1
S1
4
Cr
L
– V2 +
(b)
FIGURE 14.92 Mode B operation: (a) equivalent circuit and (b) waveforms.
FIGURE 14.93 Twoquadrant (QIII+IV) DC/DC ZCS quasiresonant Luoconverter.
326
F. L. Luo and H. Ye
Each mode has two states: “on” and “off.” The switch status of each state is shown in Table 14.9. Mode C is a ZCS buck–boost converter. The equivalent circuit, current, and voltage waveforms are shown in Fig. 14.94. There are four time regions for the switching on and off period. The conduction duty cycle is kT = (t1 + t2 ) when the input current ﬂows through the switch S1 and the main inductor L. The whole period is T = (t1 + t2 + t3 + t4 ). Some formulas are listed below ω1 = √
1 ; Lr1 Cr
TABLE 14.9
Lr1 ; Cr
Z1 =
V1 Z1 (14.331)
i1−peak = IL +
Switch’s status (the blank status means off)
Switch or diode
Mode C (QIII) Stateon
S1 D1 S2 D2
Stateoff
Stateon
1 (π + α1 ); ω1
t2 =
IL Z1 V1 + V 2
(14.332)
vCO = (V1 − V2 ) + V1 sin(π/2 + α1 ) = V1 (1 + cos α1 ) − V2
(vCO + V2 )Cr V1 (1 + cos α1 )Cr = ; IL IL V1 + V2 cos α1 t1 + t2 I1 = ; IL + Z1 π/2 + α1 T
(14.333)
t3 =
t4 = k=
I2 =
V1 (t1 + t2 ) V1 + V2 cos α1 IL + V2 IL Z1 π/2 + α1
t1 + t 2 ; t1 + t 2 + t 3 + t 4
T = t1 + t2 + t3 + t4 ;
ON ON
Lr1
t4 IL T (14.334) (14.335)
f = 1/T (14.336)
Stateoff
ON
S1
α1 = sin
−1
Mode D (QIV)
ON
iLr1
IL Lr1 t1 = ; V1 + V 2
Mode D is a cross ZCS buck–boost converter. The equivalent circuit, current, and voltage waveforms are shown in Fig. 14.95. There are four time regions for the switching on and off period. The conduction duty cycle is kT = (t1 + t2 ), but the output current only ﬂows through the source V1 in S2
D1
D2
Lr2 iLr2
+ VC Cr −
+ V1 −
IL
+
+ VC Cr −
+
− V2
V1 −
IL 0
iLr2
(V1+V2) /Z1 t2'
t1
t2
t3
t4
IL 0
vc0 V1
t3'
vc
t2
V2
t3
V2 t3
t4
V1
t3'
V1−V2
0 t2
t4
vc
V1 t1
V2
(V1+V2) /Z2
t2'
t1
V1
V1−V2 V2 0
+
(a)
(a)
iLr1
− IL
t1
vc0
t2
t3
t4
(b)
(b)
FIGURE 14.94 Mode C operation: (a) equivalent circuit and (b) waveforms.
FIGURE 14.95 Mode D operation: (a) equivalent circuit and (b) waveforms.
14
327
DC/DC Conversion Technique and 12 Series Luoconverters
the period t4 . The whole period is T = (t1 + t2 + t3 + t4 ). Some formulas are listed below 1 V2 Lr2 ω2 = √ ; Z2 = ; i2−peak = IL + Cr Z2 Lr2 Cr (14.337) I L Z2 IL Lr2 −1 t1 = (14.338) ; α2 = sin V1 + V 2 V2 + V 2 1 (π + α2 ); ω2
t2 =
(V1 − vCO )Cr V2 (1 + cos α2 )Cr = ; IL IL t1 + t2 V1 + V2 cos α2 I2 = ; IL + T Z2 π/2 + α2
(14.339)
t3 =
k=
I1 =
V2 (t1 + t2 ) V1 + V2 cos α2 IL + V1 IL Z2 π/2 + α2
t1 + t 2 ; t1 + t 2 + t 3 + t 4
T = t1 + t2 + t3 + t4 ;
t4 IL T (14.340) (14.341)
f = 1/T (14.342)
14.11.3 Fourquadrant ZCS Quasiresonant Luoconverter Fourquadrant ZCS quasiresonant Luoconverter is shown in Fig. 14.96. Circuit 1 implements the operation in quadrants I and II, circuit 2 implements the operation in quadrants III and IV. Circuit 1 and 2 can be converted to each other by auxiliary switch. Each circuit consists of one main inductor L and two switches. A switch Sa is used for fourquadrant operation. Assuming that the main inductance L is sufﬁciently large,
D1 S1
2/4
Sa
1/3
Lr1 iL ir
D2
Lr2 L
S2
+ V1 –
1. Mode A (Quadrant I): electrical energy is transferred from V1 side to V2 side, switch Sa links to D2 ; 2. Mode B (Quadrant II): electrical energy is transferred from V2 side to V1 side, switch Sa links to D1 ; 3. Mode C (Quadrant III): electrical energy is transferred from V1 side to −V2 side, switch Sa links to D2 ; 4. Mode D (Quadrant IV): electrical energy is transferred from −V2 side to V1 side, switch Sa links to D1 .
vCO = (V1 − V2 ) − V2 sin(π/2 + α2 ) = V1 − V2 (1 + cos α2 )
t4 =
the current iL remains constant. The source and load voltages are usually constant, e.g. V1 = 42 V and V2 = ±28 V [7–9]. There are four modes of operation:
S3
Cr 1/2
3/4
1/2 + V 2 –
3/4
FIGURE 14.96 Fourquadrant DC/DC ZCS quasiresonant Luoconverter.
Each mode has two states: “on” and “off.” The switch status of each state is shown in Table 14.10. The operation of Mode A, B, C, and D is same as in the previous Sections 14.11.1 and 14.11.2.
14.12 Multiquadrant ZVS Quasiresonant Luoconverters Multiquadrant ZVS quasiresonant Luoconverters are the fourthgeneration converters. Because these converters implement ZCS technique, they have the advantages of high power density, high power transfer efﬁciency, low EMI, and reasonable EMC. They have three modes: • • •
Twoquadrant ZVS quasiresonant DC/DC Luoconverter in forward operation; Twoquadrant ZVS quasiresonant DC/DC Luoconverter in reverse operation; Fourquadrant ZVS quasiresonant DC/DC Luoconverter.
The twoquadrant ZVS quasiresonant DC/DC Luoconverter in forward operation is derived for the energy transmission of a dualvoltage system. Both, the source and load voltages are positive polarity. It performs in the ﬁrstquadrant QI and the secondquadrant QII corresponding to the DC motor forward operation in motoring and regenerative braking states. The twoquadrant ZVS quasiresonant DC/DC Luoconverter in reverse operation is derived for the energy transmission of a dualvoltage system. The source voltage is positive and load voltage is negative polarity. It performs in the thirdquadrant QIII and the fourthquadrant QIV corresponding to the DC motor reverse operation in motoring and regenerative braking states. The fourquadrant ZVS quasiresonant DC/DC Luoconverter is derived for the energy transmission of a dualvoltage system. The source voltage is positive, and load voltage can be positive or negative polarity. It performs fourquadrant operation corresponding to the DC motor forward and reverse operation in motoring and regenerative braking states.
328
F. L. Luo and H. Ye TABLE 14.10
Switch’s status (the blank status means off)
Circuit//switch or diode
Mode A (QI) Stateon
Mode B (QII)
Stateoff
Circuit
Stateon
Mode C (QIII)
Stateoff
Stateon
Stateoff
Circuit 1
S1 D1 S2 D2
Mode D (QIV) Stateon
Stateoff
Circuit 2
ON
ON ON
ON
ON
ON
ON
ON
14.12.1 Twoquadrant ZVS Quasiresonant DC/DC Luoconverter in Forward Operation Twoquadrant ZVS quasiresonant Luoconverter in forward operation is shown in Fig. 14.97. It consists of one main inductor L and two switches with their auxiliary components. Assuming the main inductance L is sufﬁciently large, the current iL is constant. The source voltage V1 and load voltage V2 are usually constant, e.g. V1 = 42 V and V2 = 14 V. There are two modes of operation: 1. Mode A (Quadrant I): electrical energy is transferred from V1 side to V2 side; 2. Mode B (Quadrant II): electrical energy is transferred from V2 side to V1 side. Each mode has two states: “on” and “off.” The switch status of each state is shown in Table 14.11. Mode A is a ZVS buck converter shown in Fig. 14.98. There are four time regions for the switching on and off period.
D1 S1 Cr1 +
+
vc1
IL
Lr
+
ir
−
D2
V2
V1
−
− (a)
vC1 V1 0
Z1IL
t1
t2
t3
ir
IL
t4
t3'
IL
0 IL ir01 t1
D1 S1 +
Lr
Cr1
t3
L
ir
t4
(b)
FIGURE 14.98 Mode A operation: (a) equivalent circuit and (b) waveforms.
+
V1
V2
−
Cr2
S2
D2
−
FIGURE 14.97 Twoquadrant (QI+QII) DC/DC ZVS quasiresonant Luoconverter. TABLE 14.11
The conduction duty cycle is kT = (t3 + t4 ) when the input current ﬂows through the switch S1 and the main inductor L. The whole period is T = (t1 + t2 + t3 + t4 ). Some relevant formulas are listed below
Switch’s status (the blank status means off)
Switch
Mode A (QI) Stateon
S1 D1 S2 D2
t2
iL
Stateoff
Mode B (QII) Stateon
ON ON
Z1 =
Lr ; Cr1
vc1−peak = V1 +Z1 IL (14.343)
Stateoff
ON
ON
1 ω1 = √ ; Lr Cr1
V1 Cr1 t1 = ; IL t2 =
α1 = sin
1 (π +α1 ); ω1
−1
V1 Z1 IL
irO1 = −IL cosα1
(14.344) (14.345)
14
329
DC/DC Conversion Technique and 12 Series Luoconverters
(IL −irO1 )Lr ; t3 = V1
I L V2 1 I1 = = V1 T
t4 ir dt ≈ t3
1 t4 (IL t4 ) = IL T T
t2 =
1 (π + α2 ); ω2
irO2 = IL (1 + cos α2 ) t3 =
(14.346) t4 = k=
t3 +t4 ; t1 +t2 +t3 +t4
t1 +t2 +t3 (V1 /V2 )−1
(14.347)
T = t1 +t2 +t3 +t4 ;
IL V2 1 I1 = = V1 T
f = 1/T (14.348)
1 ω2 = √ ; Lr Cr2
Lr ; Cr2
Z2 =
vC2−peak = V1 + Z2 IL (14.349)
t1 =
V1 Cr2 ; IL
D1
α2 = sin−1
V1 Z2 IL
i
(14.350)
IL
Lr
+
+
r
V1
V2
+
−
vc2 Cr2 −
S2
−
D2
V1 0
Z2IL
t1
t2
t3
t3 + t4 ; t1 + t 2 + t 3 + t 4
0
t1
1. Mode C (Quadrant III): electrical energy is transferred from V1 side to −V2 side; 2. Mode D (Quadrant IV): electrical energy is transferred from −V2 side to V1 side.
t4 D1
t3'
+ t3
f = 1/T
Twoquadrant ZVS quasiresonant Luoconverter in reverse operation is shown in Fig. 14.100. It consists of one main inductor L and two switches with their auxiliary components. Assuming the main inductance L is sufﬁciently large, the current iL is constant. The source voltage V1 and load voltage V2 are usually constant, e.g. V1 = +42 V and V2 = −28 V. There are two modes of operation:
D2 S1
t2
(14.353)
14.12.2 Twoquadrant ZVS Quasiresonant DC/DC Luoconverter in Reverse Operation
IL ir
T = t1 + t2 + t3 + t4 ;
(14.352)
(14.354)
ir02
IL
t1
t2 + t3 1 I L t2 + t 3 = IL ; T T
Each mode has two states: “on” and “off.” The switch status of each state is shown in Table 14.12. Mode C is a ZVS buck–boost converter shown in Fig. 14.101. There are four time regions for the switching on and off period. The conduction duty cycle is kT = (t3 + t4 ) when the input current ﬂows through the switch S1 and the main inductor L. The whole period is T = (t1 + t2 + t3 + t4 ).
(a)
vC2
k=
ir dt ≈
irO2 Lr ; V1
t2 + t 3 1 V2 = (t2 + t3 ) = t1 + t 2 + t 3 + t 4 V1 T V1 t4 = − 1 (t2 + t3 ) − t1 ; V2
or Mode B is a ZVS boost converter shown in Fig. 14.99. There are four time regions for the switching on and off period. The conduction duty cycle is kT = (t3 +t4 ), but the output current only ﬂows through the source V1 in the period (t1 + t2 ). The whole period is T = (t1 + t2 + t3 + t4 ). Some relevant formulas are listed below
t3
(14.351)
t4
V1 −
Lr
S2
ir Cr1
L
iL
Cr2
− V2 +
(b)
FIGURE 14.99 Mode B operation: (a) equivalent circuit and (b) waveforms.
FIGURE 14.100 Twoquadrant (QIII+IV) DC/DC ZVS quasiresonant Luoconverter.
330
F. L. Luo and H. Ye TABLE 14.12
Switch’s status (the blank status means off)
Switch
Mode C (QIII) Stateon
Mode D (QIV)
Stateoff
Stateon
t4
ON ON
1 t4 (IL t4 ) = IL T T
ir dt ≈ t3
Stateoff
ON
S1 D1 S2 D2
I L V2 1 = I1 = V1 T t1 +t2 +t3 t4 = ; (V1 /V2 )−1
1 I2 = T
t3 (IL −ir )dt ≈ t1
(14.358)
t1 +t2 +t3 IL T
ON
(14.359) k=
D1 S1 + V1 −
Cr1 +
Lr
D2
ir
− Vc1
− IL
+
V2
t3 +t4 ; t1 +t2 +t3 +t4
T = t1 +t2 +t3 +t4 ;
f = 1/T (14.360)
Mode D is a cross ZVS buck–boost converter shown in Fig. 14.102. There are four time regions for the switching on and off period. The conduction duty cycle is kT = (t3 + t4 ), but the output current only ﬂows through the source V1 in the period (t1 + t2 ). The whole period is T = (t1 + t2 + t3 + t4 ). Some formulae are listed below 1 ω2 = √ ; Lr Cr2
(a)
Lr ; Cr2
Z2 =
vC2−peak = V1 + V2 + Z2 IL (14.361)
vC1 V1+V2 0
Z1IL
t1
t2
t3
(V1 + V2 )Cr2 ; IL
t3'
IL
Lr
D1
Cr2
t2
+
+
ir01 t3
IL
V1
t4
FIGURE 14.101 Mode C operation: (a) equivalent circuit and (b) waveforms.
vC2 V1+V2 0
Z1 =
vc1−peak = V1 +V2 +Z1 IL
Z2IL
t1
t2
1 (π +α1 ); ω1
α1 = sin−1
t3
t4
t3
t4
ir02
(14.355) (V1 +V2 )Cr1 t1 = ; IL
− V2 +
(a)
Some formulas are listed below Lr ; Cr1
− Vc2
−
(b)
t2 =
(14.362)
S2
ir
IL
1 ω1 = √ ; Lr Cr1
V1 + V 2 Z2 IL
t4
0
t1
α2 = sin−1
D2
ir
IL
t1 =
V1 +V2 Z1 IL
IL
(14.356) 0
irO1 = −IL sin(π/2+α1 )
(IL −irO1 )Lr IL (1+cosα1 )Lr t3 = = ; V1 +V2 V1 +V2
(14.357)
ir
IL t1
t3' t2 (b)
FIGURE 14.102 Mode D operation: (a) equivalent circuit and (b) waveforms.
14
331
DC/DC Conversion Technique and 12 Series Luoconverters
t2 =
1 (π + α2 ); ω2
irO2 = IL [1 + sin(π/2 + α2 )] (14.363)
•
irO2 Lr IL (1 + cos α2 )Lr t3 = = ; V1 + V 2 V1 + V 2 I1 =
I2 =
1 T 1 T
t3 ir dt ≈ t1
t4 t3
•
t1 + t2 + t3 IL ; T
•
t3 + t4 ; t1 + t 2 + t 3 + t 4
1 t4 ir dt ≈ (IL t4 ) = IL ; T T
T = t1 + t2 + t3 + t4 ;
Mode A (Quadrant I): electrical energy is from V1 side to V2 side; Mode B (Quadrant II): electrical energy is from V2 side to V1 side; Mode C (Quadrant III): electrical energy is from V1 side to −V2 side; Mode D (Quadrant IV): electrical energy is from −V2 side to V1 side.
transferred transferred transferred transferred
Each mode has two states: “on” and “off.” The switch status of each state is shown in Table 14.13. The description of Modes A, B, C, and D is same as in the previous Sections 14.12.1 and 14.12.2.
1 t1 + t2 + t3 V2 = (t1 + t2 + t3 ) = V1 T t1 + t 2 + t 3 + t 4 (14.364) V1 t4 = − 1 (t1 + t2 + t3 ) (14.365) V2 k=
•
f = 1/T (14.366)
14.12.3 Fourquadrant ZVS Quasiresonant DC/DC Luoconverter Fourquadrant ZVS quasiresonant Luoconverter is shown in Fig. 14.103. Circuit 1 implements the operation in quadrants I and II, circuit 2 implements the operation in quadrants III and IV. Circuit 1 and 2 can be converted to each other by auxiliary switch. Each circuit consists of one main inductor L and two switches. Assuming that the main inductance L is sufﬁciently large, the current iL is constant. The source and load voltages are usually constant, e.g. V1 = 42 V and V2 = ±28 V. There are four modes of operation:
14.13 Synchronousrectiﬁer DC/DC Luoconverters Synchronousrectiﬁer (SR) DC/DC converters are called the ﬁfthgeneration converters. The development of the microelectronics and computer science requires the power supplies with low output voltage and strong current. Traditional diode bridge rectiﬁers are not available for this requirement. Softswitching technique can be applied in SR DC/DC converters. We have created few converters with very low voltage (5 V, 3.3 V, and 1.8 ∼ 1.5 V) and strong current (30 A, 60 A up to 200 A) and high power transfer efﬁciency (86%, 90% up to 93%). In this section, few new circuits, different from the ordinary SR DC/DC converters, are introduced: • • • •
Flat transformer synchronousrectiﬁer DC/DC Luoconverter; Double current synchronousrectiﬁer DC/DC Luoconverter with active clamp circuit; Zerocurrentswitching synchronousrectiﬁer DC/DC Luoconverter; Zerovoltageswitching synchronousrectiﬁer DC/DC Luoconverter.
D1 S1 Cr1
+
Lr iL
ir Cr2
S2
V1
D2
L
S3
− ab cd
ab cd + V 2 −
FIGURE 14.103 Fourquadrant DC/DC ZVS quasiresonant Luoconverter.
14.13.1 Flat Transformer Synchronousrectiﬁer DC/DC Luoconverter Flat transformer SR DC/DC Luoconverter is shown in Fig. 14.104. The switches S1 , S2 , and S3 are the lowresistance MOSFET devices with very low resistance RS (7–8 m). Since we use a ﬂat transformer, the leakage inductance Lm and resistance RL are small. Other parameters are C = 1 µF, Lm = 1 nH, R